From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 937D4C433E0 for ; Fri, 17 Jul 2020 05:21:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6932B206BE for ; Fri, 17 Jul 2020 05:21:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="Um6lylkn" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726046AbgGQFVZ (ORCPT ); Fri, 17 Jul 2020 01:21:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725811AbgGQFVY (ORCPT ); Fri, 17 Jul 2020 01:21:24 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3F72C08C5C0 for ; Thu, 16 Jul 2020 22:21:23 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id f7so9699305wrw.1 for ; Thu, 16 Jul 2020 22:21:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=Txl23SYhqU4CFJgNmtRHcmqgdOnnkrGVMry+7+SHVI0=; b=Um6lylknChyL1OR7eW5Cr5ane6YZUWnV0SXE4vqFXu/ELh4Z7b3fyrNThjGCL0nlwl kuu20mdky7crrzFpwpWiAqj1XCA4BueQSsqfbqaOGn6E1cJ+NDYeJaz3cE8w6cv+w9qE s8R8niwltE0xyz8reBTW1YRDB2reXu4Et0CIoT+qEli3AyaKlvNV6qXSIHkhUtsasM2x s5myGeDLhawzzEWwHoi/dG/4JO5qSc/sC58gphwGEJ8vK3JfZDPIwUAeFzRIb3JdL+nP XQVaf743301pUga7sYiWzothWYzJVdoiGHWfhKXYlWGALc0XzrtvAewI4sSBjE2JkKeX lfyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Txl23SYhqU4CFJgNmtRHcmqgdOnnkrGVMry+7+SHVI0=; b=MQ14v+c9Fi7G08qTvKErjuH4MhGIvbG7Xw2rOKQS/dtmezX99aKpbjidLfroWQTCxN TMkzUUcL8uNywbJ/ku3rWKlrvxj8/ZBHwuJZmXsVlYUkF03TRfnKBF/SmjKjjc9UaVMS xAMVew9j8pbiOAhyq2eDP2IE2KRp0xL1vNt5FuW1qZgQ5s0gr6cpSLaBXf5we+7MxxYo Agyz0wnd9t5B9w/o0uYZHpoHRzknwB8FJhqGBI++XXq8kkccTP0fgVDMAi+0aWr9SgS7 0Fjw9O4aDmXXUn1qrTGRrD/oHghQgSuO9sF+f6n+ewDLn3zL5sWxQ0Rqi8m6n3rFSDCx KyVw== X-Gm-Message-State: AOAM530f6fi8oE2N5vA4I2mx1lTYgPwbbGbJFURcDyzfayGQFfXe1Von 7XHW4oOBIrAuzDSVuwJQLj0Z1OTw2lw0jtxKntsd5g== X-Google-Smtp-Source: ABdhPJybDCXcZ50/toMOuo5zRNW4SflJKE6iLzPyyHW1LE2nGkJvcPBvXVKS3c2n0ukmR1x5G6LOQdUVlYPD8+EA3S4= X-Received: by 2002:adf:b190:: with SMTP id q16mr8608059wra.356.1594963282019; Thu, 16 Jul 2020 22:21:22 -0700 (PDT) MIME-Version: 1.0 References: <20200715071506.10994-1-anup.patel@wdc.com> <20200715071506.10994-3-anup.patel@wdc.com> <9a36824c-ef23-de47-b52c-bf680067be6c@linaro.org> In-Reply-To: <9a36824c-ef23-de47-b52c-bf680067be6c@linaro.org> From: Anup Patel Date: Fri, 17 Jul 2020 10:51:10 +0530 Message-ID: Subject: Re: [PATCH v3 2/4] clocksource/drivers: Add CLINT timer driver To: Daniel Lezcano Cc: Anup Patel , Palmer Dabbelt , Paul Walmsley , Albert Ou , Rob Herring , Thomas Gleixner , Damien Le Moal , Atish Patra , Alistair Francis , linux-riscv , "linux-kernel@vger.kernel.org List" , devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 17, 2020 at 2:57 AM Daniel Lezcano wrote: > > > Hi Anup, > > > On 15/07/2020 09:15, Anup Patel wrote: > > The TIME CSR and SBI calls are not available in RISC-V M-mode so we > > separate add CLINT driver for Linux RISC-V M-mode (i.e. RISC-V NoMMU > > kernel). > > The description is confusing, please reword it and give a bit more > information about the timer itself, especially, the IPI thing. Okay, will update. > > > Signed-off-by: Anup Patel > > --- > > drivers/clocksource/Kconfig | 10 ++ > > drivers/clocksource/Makefile | 1 + > > drivers/clocksource/timer-clint.c | 229 ++++++++++++++++++++++++++++++ > > include/linux/cpuhotplug.h | 1 + > > 4 files changed, 241 insertions(+) > > create mode 100644 drivers/clocksource/timer-clint.c > > > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > > index 91418381fcd4..eabcf1cfb0c0 100644 > > --- a/drivers/clocksource/Kconfig > > +++ b/drivers/clocksource/Kconfig > > @@ -658,6 +658,16 @@ config RISCV_TIMER > > is accessed via both the SBI and the rdcycle instruction. This= is > > required for all RISC-V systems. > > > > +config CLINT_TIMER > > + bool "Timer for the RISC-V platform" > > + depends on GENERIC_SCHED_CLOCK && RISCV_M_MODE > > + default y > > + select TIMER_PROBE > > + select TIMER_OF > > + help > > + This option enables the CLINT timer for RISC-V systems. The CLI= NT > > + driver is usually used for NoMMU RISC-V systems. > > For the timer, we do silent option and let the platform config select > it. Please refer to other timer option below as reference. Okay, I will use "default RISCV" instead of "default y" (just like other timer Kconfig options). > > > config CSKY_MP_TIMER > > bool "SMP Timer for the C-SKY platform" if COMPILE_TEST > > depends on CSKY > > diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefil= e > > index bdda1a2e4097..18e700e703a0 100644 > > --- a/drivers/clocksource/Makefile > > +++ b/drivers/clocksource/Makefile > > @@ -87,6 +87,7 @@ obj-$(CONFIG_CLKSRC_ST_LPC) +=3D clksrc_st_lp= c.o > > obj-$(CONFIG_X86_NUMACHIP) +=3D numachip.o > > obj-$(CONFIG_ATCPIT100_TIMER) +=3D timer-atcpit100.o > > obj-$(CONFIG_RISCV_TIMER) +=3D timer-riscv.o > > +obj-$(CONFIG_CLINT_TIMER) +=3D timer-clint.o > > obj-$(CONFIG_CSKY_MP_TIMER) +=3D timer-mp-csky.o > > obj-$(CONFIG_GX6605S_TIMER) +=3D timer-gx6605s.o > > obj-$(CONFIG_HYPERV_TIMER) +=3D hyperv_timer.o > > diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/ti= mer-clint.c > > new file mode 100644 > > index 000000000000..bfc38bb5a589 > > --- /dev/null > > +++ b/drivers/clocksource/timer-clint.c > > @@ -0,0 +1,229 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2020 Western Digital Corporation or its affiliates. > > + * > > + * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a > > + * CLINT MMIO timer device. > > + */ > > + > > +#define pr_fmt(fmt) "clint: " fmt > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define CLINT_IPI_OFF 0 > > +#define CLINT_TIMER_CMP_OFF 0x4000 > > +#define CLINT_TIMER_VAL_OFF 0xbff8 > > + > > +/* CLINT manages IPI and Timer for RISC-V M-mode */ > > +static u32 __iomem *clint_ipi_base; > > +static u64 __iomem *clint_timer_cmp; > > +static u64 __iomem *clint_timer_val; > > +static unsigned long clint_timer_freq; > > +static unsigned int clint_timer_irq; > > + > > +static void clint_send_ipi(const struct cpumask *target) > > +{ > > + unsigned int cpu; > > + > > + for_each_cpu(cpu, target) > > + writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu)); > > +} > > + > > +static void clint_clear_ipi(void) > > +{ > > + writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id()= )); > > +} > > + > > +static struct riscv_ipi_ops clint_ipi_ops =3D { > > + .ipi_inject =3D clint_send_ipi, > > + .ipi_clear =3D clint_clear_ipi, > > +}; > > + > > +#ifdef CONFIG_64BIT > > +#define clint_get_cycles() readq_relaxed(clint_timer_val) > > +#else > > +#define clint_get_cycles() readl_relaxed(clint_timer_val) > > +#define clint_get_cycles_hi() readl_relaxed(((u32 *)clint_timer= _val) + 1) > > +#endif > > + > > +#ifdef CONFIG_64BIT > > +static u64 clint_get_cycles64(void) > > +{ > > + return clint_get_cycles(); > > +} > > +#else /* CONFIG_64BIT */ > > +static u64 clint_get_cycles64(void) > > +{ > > + u32 hi, lo; > > + > > + do { > > + hi =3D clint_get_cycles_hi(); > > + lo =3D clint_get_cycles(); > > + } while (hi !=3D clint_get_cycles_hi()); > > + > > + return ((u64)hi << 32) | lo; > > +} > > +#endif /* CONFIG_64BIT */ > > +static int clint_clock_next_event(unsigned long delta, > > + struct clock_event_device *ce) > > +{ > > + void __iomem *r =3D clint_timer_cmp + > > + cpuid_to_hartid_map(smp_processor_id()); > > + > > + csr_set(CSR_IE, IE_TIE); > > + writeq_relaxed(clint_get_cycles64() + delta, r); > > + return 0; > > +} > > + > > +static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = =3D { > > + .name =3D "clint_clockevent", > > + .features =3D CLOCK_EVT_FEAT_ONESHOT, > > + .rating =3D 100, > > + .set_next_event =3D clint_clock_next_event, > > +}; > > + > > +static u64 clint_rdtime(struct clocksource *cs) > > +{ > > + return readq_relaxed(clint_timer_val); > > +} > > + > > +static u64 notrace clint_sched_clock(void) > > +{ > > + return readq_relaxed(clint_timer_val); > > +} > > + > > +static struct clocksource clint_clocksource =3D { > > + .name =3D "clint_clocksource", > > + .rating =3D 300, > > + .mask =3D CLOCKSOURCE_MASK(64), > > + .flags =3D CLOCK_SOURCE_IS_CONTINUOUS, > > + .read =3D clint_rdtime, > > What if !CONFIG_64BIT The CLINT counter is 64bit for both 32bit and 64bit systems but I should have used clint_get_cycles64() in clint_rdtime(). I will update it. > > > +}; > > + > > +static int clint_timer_starting_cpu(unsigned int cpu) > > +{ > > + struct clock_event_device *ce =3D per_cpu_ptr(&clint_clock_event,= cpu); > > + > > + ce->cpumask =3D cpumask_of(cpu); > > + clockevents_config_and_register(ce, clint_timer_freq, 200, ULONG_= MAX); > > The function is not immune against registering the same clockevents. If > the CPU is hotplugged several times, this function will be called again > and again. Why not rely on a for_each_possible_cpu loop in the init > function ? > > > + enable_percpu_irq(clint_timer_irq, > > + irq_get_trigger_type(clint_timer_irq)); > > Why do you want to enable / disable the interrrupts ? The should be > already handle by the hotplug framework no ? The perCPU interrupts are not enabled by default. We have to explicitly enable/disable perCPU interrupts in CPU hotplug callbacks. > > > + return 0; > > +} > > + > > +static int clint_timer_dying_cpu(unsigned int cpu) > > +{ > > + disable_percpu_irq(clint_timer_irq); > > + return 0; > > +} > > + > > +static irqreturn_t clint_timer_interrupt(int irq, void *dev_id) > > +{ > > + struct clock_event_device *evdev =3D this_cpu_ptr(&clint_clock_ev= ent); > > + > > + csr_clear(CSR_IE, IE_TIE); > > + evdev->event_handler(evdev); > > + > > + return IRQ_HANDLED; > > +} > > + > > +static int __init clint_timer_init_dt(struct device_node *np) > > +{ > > + int rc; > > + u32 i, nr_irqs; > > + void __iomem *base; > > + struct of_phandle_args oirq; > > + > > + /* > > + * Ensure that CLINT device interrupts are either RV_IRQ_TIMER or > > + * RV_IRQ_SOFT. If it's anything else then we ignore the device. > > + */ > > + nr_irqs =3D of_irq_count(np); > > + for (i =3D 0; i < nr_irqs; i++) { > > + if (of_irq_parse_one(np, i, &oirq)) { > > + pr_err("%pOFP: failed to parse irq %d.\n", np, i)= ; > > + continue; > > + } > > + > > + if ((oirq.args_count !=3D 1) || > > + (oirq.args[0] !=3D RV_IRQ_TIMER && > > + oirq.args[0] !=3D RV_IRQ_SOFT)) { > > + pr_err("%pOFP: invalid irq %d (hwirq %d)\n", > > + np, i, oirq.args[0]); > > + return -ENODEV; > > + } > > + > > + /* Find parent irq domain and map timer irq */ > > + if (!clint_timer_irq && > > + oirq.args[0] =3D=3D RV_IRQ_TIMER && > > + irq_find_host(oirq.np)) > > + clint_timer_irq =3D irq_of_parse_and_map(np, i); > > + } > > + > > + /* If CLINT timer irq not found then fail */ > > + if (!clint_timer_irq) { > > + pr_err("%pOFP: timer irq not found\n", np); > > + return -ENODEV; > > + } > > + > > + base =3D of_iomap(np, 0); > > + if (!base) { > > + pr_err("%pOFP: could not map registers\n", np); > > + return -ENODEV; > > + } > > + > > + clint_ipi_base =3D base + CLINT_IPI_OFF; > > + clint_timer_cmp =3D base + CLINT_TIMER_CMP_OFF; > > + clint_timer_val =3D base + CLINT_TIMER_VAL_OFF; > > + clint_timer_freq =3D riscv_timebase; > > + > > + pr_info("%pOFP: timer running at %ld Hz\n", np, clint_timer_freq)= ; > > + > > + rc =3D clocksource_register_hz(&clint_clocksource, clint_timer_fr= eq); > > + if (rc) { > > + iounmap(base); > > + pr_err("%pOFP: clocksource register failed [%d]\n", np, r= c); > > + return rc; > > + } > > + > > + sched_clock_register(clint_sched_clock, 64, clint_timer_freq); > > + > > + rc =3D request_percpu_irq(clint_timer_irq, clint_timer_interrupt, > > + "clint-timer", &clint_clock_event); > > + if (rc) { > > + iounmap(base); > > + pr_err("registering percpu irq failed [%d]\n", rc); > > + return rc; > > + } > > + > > + rc =3D cpuhp_setup_state(CPUHP_AP_CLINT_TIMER_STARTING, > > + "clockevents/clint/timer:starting", > > + clint_timer_starting_cpu, > > + clint_timer_dying_cpu); > > + if (rc) { > > + free_irq(clint_timer_irq, &clint_clock_event); > > + iounmap(base); > > + pr_err("%pOFP: cpuhp setup state failed [%d]\n", np, rc); > > + return rc; > > + } > > + > > + riscv_set_ipi_ops(&clint_ipi_ops); > > + clint_clear_ipi(); > > + > > + return 0; > > +} > > + > > +TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt); > > +TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt); > > diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h > > index 191772d4a4d7..1451f4625833 100644 > > --- a/include/linux/cpuhotplug.h > > +++ b/include/linux/cpuhotplug.h > > @@ -132,6 +132,7 @@ enum cpuhp_state { > > CPUHP_AP_MIPS_GIC_TIMER_STARTING, > > CPUHP_AP_ARC_TIMER_STARTING, > > CPUHP_AP_RISCV_TIMER_STARTING, > > + CPUHP_AP_CLINT_TIMER_STARTING, > > CPUHP_AP_CSKY_TIMER_STARTING, > > CPUHP_AP_HYPERV_TIMER_STARTING, > > CPUHP_AP_KVM_STARTING, > > > > > -- > Linaro.org =E2=94=82 Open source software for AR= M SoCs > > Follow Linaro: Facebook | > Twitter | > Blog Regards, Anup From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D140C433E2 for ; Fri, 17 Jul 2020 05:21:38 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4E40D206BE for ; Fri, 17 Jul 2020 05:21:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="cnZO8/X9"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="Um6lylkn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4E40D206BE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From:In-Reply-To: References:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=1H7UBDUu9VaFZ9wx19oC5msRjWXCFJS5vMIyDarZTLE=; b=cnZO8/X9BtaV7kpYJSG+tjZ4J YIOyMSBR2TmowdKmYJvNyN3beJkyBFDNUDEZKCG/tzWnYWOFV64OKDf/aH16Q+CkRM9VdSrI39zpf KPVdhQECjZ85oHWo/WfA8kyy5LYYlE/qtzYZ5WEO9Y2vu5UTaI4omSF4j9ZDrSHazi76v4e4U6KLb LzsL7Rf2k5+3ri9H7O72f1DfYhopuW2oBD1tbd7VwKFO0GrzKrAzFIMvDGbnYJ1WcJPBJRjakNyOA zx56xSOi9XEIctCesy3eb1+KNAiQ0+da1daJkoQCkdyPhEs0UpEfwwZXmIDwRITYpNF3W+FzdoGuq 2NJYALs9Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwIoJ-0005CL-5o; Fri, 17 Jul 2020 05:21:27 +0000 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwIoF-0005Bo-VE for linux-riscv@lists.infradead.org; Fri, 17 Jul 2020 05:21:25 +0000 Received: by mail-wr1-x443.google.com with SMTP id s10so9617164wrw.12 for ; Thu, 16 Jul 2020 22:21:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=Txl23SYhqU4CFJgNmtRHcmqgdOnnkrGVMry+7+SHVI0=; b=Um6lylknChyL1OR7eW5Cr5ane6YZUWnV0SXE4vqFXu/ELh4Z7b3fyrNThjGCL0nlwl kuu20mdky7crrzFpwpWiAqj1XCA4BueQSsqfbqaOGn6E1cJ+NDYeJaz3cE8w6cv+w9qE s8R8niwltE0xyz8reBTW1YRDB2reXu4Et0CIoT+qEli3AyaKlvNV6qXSIHkhUtsasM2x s5myGeDLhawzzEWwHoi/dG/4JO5qSc/sC58gphwGEJ8vK3JfZDPIwUAeFzRIb3JdL+nP XQVaf743301pUga7sYiWzothWYzJVdoiGHWfhKXYlWGALc0XzrtvAewI4sSBjE2JkKeX lfyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Txl23SYhqU4CFJgNmtRHcmqgdOnnkrGVMry+7+SHVI0=; b=BHQ8yvt24xyR9y2a6meN4gmWd8Dqi5jhHI0HqZoSHHYZ8mber55wkiRn22jjAfQ4vL ahdCDJQ+ot4Y+CtqxNuTZRiCUKZS9tFvlWdSgsPcDFJCbgy5FegTNvWJ0RYItQ7dFMHM reP1WDji+qamuJqgW5szUVj3tjMwQVKUBFGonTNtkwtrYbflF8qfhMkltsar8Jor7kW7 /24Q8tjr1V6rgGGjagGoEwpMgchOsQdVuYEzfBht9Cy70iC64kmHHvrWvfxmRCGhbsXu r9AJEgXPlDSMcuo8xVyDA6AHcDhHMPRPQ152cpgg7xV+HZGb90ACLqGir3rM+9SWUIB6 WQYw== X-Gm-Message-State: AOAM531hOPDalPPWBZR20OOy3cRWEFNcSFsgNFs+9dHMCPc4934UJFcb w7zticdRzn3lFulTR7utLnSBWLQM+UMquETnlwNQeg== X-Google-Smtp-Source: ABdhPJybDCXcZ50/toMOuo5zRNW4SflJKE6iLzPyyHW1LE2nGkJvcPBvXVKS3c2n0ukmR1x5G6LOQdUVlYPD8+EA3S4= X-Received: by 2002:adf:b190:: with SMTP id q16mr8608059wra.356.1594963282019; Thu, 16 Jul 2020 22:21:22 -0700 (PDT) MIME-Version: 1.0 References: <20200715071506.10994-1-anup.patel@wdc.com> <20200715071506.10994-3-anup.patel@wdc.com> <9a36824c-ef23-de47-b52c-bf680067be6c@linaro.org> In-Reply-To: <9a36824c-ef23-de47-b52c-bf680067be6c@linaro.org> From: Anup Patel Date: Fri, 17 Jul 2020 10:51:10 +0530 Message-ID: Subject: Re: [PATCH v3 2/4] clocksource/drivers: Add CLINT timer driver To: Daniel Lezcano X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200717_012124_147259_6D70669A X-CRM114-Status: GOOD ( 37.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Damien Le Moal , Albert Ou , Anup Patel , "linux-kernel@vger.kernel.org List" , Atish Patra , Rob Herring , Palmer Dabbelt , Paul Walmsley , Alistair Francis , Thomas Gleixner , linux-riscv Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gRnJpLCBKdWwgMTcsIDIwMjAgYXQgMjo1NyBBTSBEYW5pZWwgTGV6Y2Fubwo8ZGFuaWVsLmxl emNhbm9AbGluYXJvLm9yZz4gd3JvdGU6Cj4KPgo+IEhpIEFudXAsCj4KPgo+IE9uIDE1LzA3LzIw MjAgMDk6MTUsIEFudXAgUGF0ZWwgd3JvdGU6Cj4gPiBUaGUgVElNRSBDU1IgYW5kIFNCSSBjYWxs cyBhcmUgbm90IGF2YWlsYWJsZSBpbiBSSVNDLVYgTS1tb2RlIHNvIHdlCj4gPiBzZXBhcmF0ZSBh ZGQgQ0xJTlQgZHJpdmVyIGZvciBMaW51eCBSSVNDLVYgTS1tb2RlIChpLmUuIFJJU0MtViBOb01N VQo+ID4ga2VybmVsKS4KPgo+IFRoZSBkZXNjcmlwdGlvbiBpcyBjb25mdXNpbmcsIHBsZWFzZSBy ZXdvcmQgaXQgYW5kIGdpdmUgYSBiaXQgbW9yZQo+IGluZm9ybWF0aW9uIGFib3V0IHRoZSB0aW1l ciBpdHNlbGYsIGVzcGVjaWFsbHksIHRoZSBJUEkgdGhpbmcuCgpPa2F5LCB3aWxsIHVwZGF0ZS4K Cj4KPiA+IFNpZ25lZC1vZmYtYnk6IEFudXAgUGF0ZWwgPGFudXAucGF0ZWxAd2RjLmNvbT4KPiA+ IC0tLQo+ID4gIGRyaXZlcnMvY2xvY2tzb3VyY2UvS2NvbmZpZyAgICAgICB8ICAxMCArKwo+ID4g IGRyaXZlcnMvY2xvY2tzb3VyY2UvTWFrZWZpbGUgICAgICB8ICAgMSArCj4gPiAgZHJpdmVycy9j bG9ja3NvdXJjZS90aW1lci1jbGludC5jIHwgMjI5ICsrKysrKysrKysrKysrKysrKysrKysrKysr KysrKwo+ID4gIGluY2x1ZGUvbGludXgvY3B1aG90cGx1Zy5oICAgICAgICB8ICAgMSArCj4gPiAg NCBmaWxlcyBjaGFuZ2VkLCAyNDEgaW5zZXJ0aW9ucygrKQo+ID4gIGNyZWF0ZSBtb2RlIDEwMDY0 NCBkcml2ZXJzL2Nsb2Nrc291cmNlL3RpbWVyLWNsaW50LmMKPiA+Cj4gPiBkaWZmIC0tZ2l0IGEv ZHJpdmVycy9jbG9ja3NvdXJjZS9LY29uZmlnIGIvZHJpdmVycy9jbG9ja3NvdXJjZS9LY29uZmln Cj4gPiBpbmRleCA5MTQxODM4MWZjZDQuLmVhYmNmMWNmYjBjMCAxMDA2NDQKPiA+IC0tLSBhL2Ry aXZlcnMvY2xvY2tzb3VyY2UvS2NvbmZpZwo+ID4gKysrIGIvZHJpdmVycy9jbG9ja3NvdXJjZS9L Y29uZmlnCj4gPiBAQCAtNjU4LDYgKzY1OCwxNiBAQCBjb25maWcgUklTQ1ZfVElNRVIKPiA+ICAg ICAgICAgaXMgYWNjZXNzZWQgdmlhIGJvdGggdGhlIFNCSSBhbmQgdGhlIHJkY3ljbGUgaW5zdHJ1 Y3Rpb24uICBUaGlzIGlzCj4gPiAgICAgICAgIHJlcXVpcmVkIGZvciBhbGwgUklTQy1WIHN5c3Rl bXMuCj4gPgo+ID4gK2NvbmZpZyBDTElOVF9USU1FUgo+ID4gKyAgICAgYm9vbCAiVGltZXIgZm9y IHRoZSBSSVNDLVYgcGxhdGZvcm0iCj4gPiArICAgICBkZXBlbmRzIG9uIEdFTkVSSUNfU0NIRURf Q0xPQ0sgJiYgUklTQ1ZfTV9NT0RFCj4gPiArICAgICBkZWZhdWx0IHkKPiA+ICsgICAgIHNlbGVj dCBUSU1FUl9QUk9CRQo+ID4gKyAgICAgc2VsZWN0IFRJTUVSX09GCj4gPiArICAgICBoZWxwCj4g PiArICAgICAgIFRoaXMgb3B0aW9uIGVuYWJsZXMgdGhlIENMSU5UIHRpbWVyIGZvciBSSVNDLVYg c3lzdGVtcy4gVGhlIENMSU5UCj4gPiArICAgICAgIGRyaXZlciBpcyB1c3VhbGx5IHVzZWQgZm9y IE5vTU1VIFJJU0MtViBzeXN0ZW1zLgo+Cj4gRm9yIHRoZSB0aW1lciwgd2UgZG8gc2lsZW50IG9w dGlvbiBhbmQgbGV0IHRoZSBwbGF0Zm9ybSBjb25maWcgc2VsZWN0Cj4gaXQuIFBsZWFzZSByZWZl ciB0byBvdGhlciB0aW1lciBvcHRpb24gYmVsb3cgYXMgcmVmZXJlbmNlLgoKT2theSwgSSB3aWxs IHVzZSAiZGVmYXVsdCBSSVNDViIgaW5zdGVhZCBvZiAiZGVmYXVsdCB5IiAoanVzdCBsaWtlIG90 aGVyCnRpbWVyIEtjb25maWcgb3B0aW9ucykuCgo+Cj4gPiAgY29uZmlnIENTS1lfTVBfVElNRVIK PiA+ICAgICAgIGJvb2wgIlNNUCBUaW1lciBmb3IgdGhlIEMtU0tZIHBsYXRmb3JtIiBpZiBDT01Q SUxFX1RFU1QKPiA+ICAgICAgIGRlcGVuZHMgb24gQ1NLWQo+ID4gZGlmZiAtLWdpdCBhL2RyaXZl cnMvY2xvY2tzb3VyY2UvTWFrZWZpbGUgYi9kcml2ZXJzL2Nsb2Nrc291cmNlL01ha2VmaWxlCj4g PiBpbmRleCBiZGRhMWEyZTQwOTcuLjE4ZTcwMGU3MDNhMCAxMDA2NDQKPiA+IC0tLSBhL2RyaXZl cnMvY2xvY2tzb3VyY2UvTWFrZWZpbGUKPiA+ICsrKyBiL2RyaXZlcnMvY2xvY2tzb3VyY2UvTWFr ZWZpbGUKPiA+IEBAIC04Nyw2ICs4Nyw3IEBAIG9iai0kKENPTkZJR19DTEtTUkNfU1RfTFBDKSAg ICAgICAgICs9IGNsa3NyY19zdF9scGMubwo+ID4gIG9iai0kKENPTkZJR19YODZfTlVNQUNISVAp ICAgICAgICAgICArPSBudW1hY2hpcC5vCj4gPiAgb2JqLSQoQ09ORklHX0FUQ1BJVDEwMF9USU1F UikgICAgICAgICAgICAgICAgKz0gdGltZXItYXRjcGl0MTAwLm8KPiA+ICBvYmotJChDT05GSUdf UklTQ1ZfVElNRVIpICAgICAgICAgICAgKz0gdGltZXItcmlzY3Yubwo+ID4gK29iai0kKENPTkZJ R19DTElOVF9USU1FUikgICAgICAgICAgICArPSB0aW1lci1jbGludC5vCj4gPiAgb2JqLSQoQ09O RklHX0NTS1lfTVBfVElNRVIpICAgICAgICAgICs9IHRpbWVyLW1wLWNza3kubwo+ID4gIG9iai0k KENPTkZJR19HWDY2MDVTX1RJTUVSKSAgICAgICAgICArPSB0aW1lci1neDY2MDVzLm8KPiA+ICBv YmotJChDT05GSUdfSFlQRVJWX1RJTUVSKSAgICAgICAgICAgKz0gaHlwZXJ2X3RpbWVyLm8KPiA+ IGRpZmYgLS1naXQgYS9kcml2ZXJzL2Nsb2Nrc291cmNlL3RpbWVyLWNsaW50LmMgYi9kcml2ZXJz L2Nsb2Nrc291cmNlL3RpbWVyLWNsaW50LmMKPiA+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gPiBp bmRleCAwMDAwMDAwMDAwMDAuLmJmYzM4YmI1YTU4OQo+ID4gLS0tIC9kZXYvbnVsbAo+ID4gKysr IGIvZHJpdmVycy9jbG9ja3NvdXJjZS90aW1lci1jbGludC5jCj4gPiBAQCAtMCwwICsxLDIyOSBA QAo+ID4gKy8vIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBHUEwtMi4wCj4gPiArLyoKPiA+ICsg KiBDb3B5cmlnaHQgKEMpIDIwMjAgV2VzdGVybiBEaWdpdGFsIENvcnBvcmF0aW9uIG9yIGl0cyBh ZmZpbGlhdGVzLgo+ID4gKyAqCj4gPiArICogTW9zdCBvZiB0aGUgTS1tb2RlIChpLmUuIE5vTU1V KSBSSVNDLVYgc3lzdGVtcyB1c3VhbGx5IGhhdmUgYQo+ID4gKyAqIENMSU5UIE1NSU8gdGltZXIg ZGV2aWNlLgo+ID4gKyAqLwo+ID4gKwo+ID4gKyNkZWZpbmUgcHJfZm10KGZtdCkgImNsaW50OiAi IGZtdAo+ID4gKyNpbmNsdWRlIDxsaW51eC9iaXRvcHMuaD4KPiA+ICsjaW5jbHVkZSA8bGludXgv Y2xvY2tzb3VyY2UuaD4KPiA+ICsjaW5jbHVkZSA8bGludXgvY2xvY2tjaGlwcy5oPgo+ID4gKyNp bmNsdWRlIDxsaW51eC9jcHUuaD4KPiA+ICsjaW5jbHVkZSA8bGludXgvZGVsYXkuaD4KPiA+ICsj aW5jbHVkZSA8bGludXgvbW9kdWxlLmg+Cj4gPiArI2luY2x1ZGUgPGxpbnV4L29mX2FkZHJlc3Mu aD4KPiA+ICsjaW5jbHVkZSA8bGludXgvc2NoZWRfY2xvY2suaD4KPiA+ICsjaW5jbHVkZSA8bGlu dXgvaW8tNjQtbm9uYXRvbWljLWxvLWhpLmg+Cj4gPiArI2luY2x1ZGUgPGxpbnV4L2ludGVycnVw dC5oPgo+ID4gKyNpbmNsdWRlIDxsaW51eC9vZl9pcnEuaD4KPiA+ICsjaW5jbHVkZSA8bGludXgv c21wLmg+Cj4gPiArCj4gPiArI2RlZmluZSBDTElOVF9JUElfT0ZGICAgICAgICAgICAgICAgIDAK PiA+ICsjZGVmaW5lIENMSU5UX1RJTUVSX0NNUF9PRkYgIDB4NDAwMAo+ID4gKyNkZWZpbmUgQ0xJ TlRfVElNRVJfVkFMX09GRiAgMHhiZmY4Cj4gPiArCj4gPiArLyogQ0xJTlQgbWFuYWdlcyBJUEkg YW5kIFRpbWVyIGZvciBSSVNDLVYgTS1tb2RlICAqLwo+ID4gK3N0YXRpYyB1MzIgX19pb21lbSAq Y2xpbnRfaXBpX2Jhc2U7Cj4gPiArc3RhdGljIHU2NCBfX2lvbWVtICpjbGludF90aW1lcl9jbXA7 Cj4gPiArc3RhdGljIHU2NCBfX2lvbWVtICpjbGludF90aW1lcl92YWw7Cj4gPiArc3RhdGljIHVu c2lnbmVkIGxvbmcgY2xpbnRfdGltZXJfZnJlcTsKPiA+ICtzdGF0aWMgdW5zaWduZWQgaW50IGNs aW50X3RpbWVyX2lycTsKPiA+ICsKPiA+ICtzdGF0aWMgdm9pZCBjbGludF9zZW5kX2lwaShjb25z dCBzdHJ1Y3QgY3B1bWFzayAqdGFyZ2V0KQo+ID4gK3sKPiA+ICsgICAgIHVuc2lnbmVkIGludCBj cHU7Cj4gPiArCj4gPiArICAgICBmb3JfZWFjaF9jcHUoY3B1LCB0YXJnZXQpCj4gPiArICAgICAg ICAgICAgIHdyaXRlbCgxLCBjbGludF9pcGlfYmFzZSArIGNwdWlkX3RvX2hhcnRpZF9tYXAoY3B1 KSk7Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyB2b2lkIGNsaW50X2NsZWFyX2lwaSh2b2lkKQo+ ID4gK3sKPiA+ICsgICAgIHdyaXRlbCgwLCBjbGludF9pcGlfYmFzZSArIGNwdWlkX3RvX2hhcnRp ZF9tYXAoc21wX3Byb2Nlc3Nvcl9pZCgpKSk7Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyBzdHJ1 Y3QgcmlzY3ZfaXBpX29wcyBjbGludF9pcGlfb3BzID0gewo+ID4gKyAgICAgLmlwaV9pbmplY3Qg PSBjbGludF9zZW5kX2lwaSwKPiA+ICsgICAgIC5pcGlfY2xlYXIgPSBjbGludF9jbGVhcl9pcGks Cj4gPiArfTsKPiA+ICsKPiA+ICsjaWZkZWYgQ09ORklHXzY0QklUCj4gPiArI2RlZmluZSBjbGlu dF9nZXRfY3ljbGVzKCkgICByZWFkcV9yZWxheGVkKGNsaW50X3RpbWVyX3ZhbCkKPiA+ICsjZWxz ZQo+ID4gKyNkZWZpbmUgY2xpbnRfZ2V0X2N5Y2xlcygpICAgcmVhZGxfcmVsYXhlZChjbGludF90 aW1lcl92YWwpCj4gPiArI2RlZmluZSBjbGludF9nZXRfY3ljbGVzX2hpKCkgICAgICAgIHJlYWRs X3JlbGF4ZWQoKCh1MzIgKiljbGludF90aW1lcl92YWwpICsgMSkKPiA+ICsjZW5kaWYKPiA+ICsK PiA+ICsjaWZkZWYgQ09ORklHXzY0QklUCj4gPiArc3RhdGljIHU2NCBjbGludF9nZXRfY3ljbGVz NjQodm9pZCkKPiA+ICt7Cj4gPiArICAgICByZXR1cm4gY2xpbnRfZ2V0X2N5Y2xlcygpOwo+ID4g K30KPiA+ICsjZWxzZSAvKiBDT05GSUdfNjRCSVQgKi8KPiA+ICtzdGF0aWMgdTY0IGNsaW50X2dl dF9jeWNsZXM2NCh2b2lkKQo+ID4gK3sKPiA+ICsgICAgIHUzMiBoaSwgbG87Cj4gPiArCj4gPiAr ICAgICBkbyB7Cj4gPiArICAgICAgICAgICAgIGhpID0gY2xpbnRfZ2V0X2N5Y2xlc19oaSgpOwo+ ID4gKyAgICAgICAgICAgICBsbyA9IGNsaW50X2dldF9jeWNsZXMoKTsKPiA+ICsgICAgIH0gd2hp bGUgKGhpICE9IGNsaW50X2dldF9jeWNsZXNfaGkoKSk7Cj4gPiArCj4gPiArICAgICByZXR1cm4g KCh1NjQpaGkgPDwgMzIpIHwgbG87Cj4gPiArfQo+ID4gKyNlbmRpZiAvKiBDT05GSUdfNjRCSVQg Ki8KPiA+ICtzdGF0aWMgaW50IGNsaW50X2Nsb2NrX25leHRfZXZlbnQodW5zaWduZWQgbG9uZyBk ZWx0YSwKPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHN0cnVjdCBjbG9ja19l dmVudF9kZXZpY2UgKmNlKQo+ID4gK3sKPiA+ICsgICAgIHZvaWQgX19pb21lbSAqciA9IGNsaW50 X3RpbWVyX2NtcCArCj4gPiArICAgICAgICAgICAgICAgICAgICAgICBjcHVpZF90b19oYXJ0aWRf bWFwKHNtcF9wcm9jZXNzb3JfaWQoKSk7Cj4gPiArCj4gPiArICAgICBjc3Jfc2V0KENTUl9JRSwg SUVfVElFKTsKPiA+ICsgICAgIHdyaXRlcV9yZWxheGVkKGNsaW50X2dldF9jeWNsZXM2NCgpICsg ZGVsdGEsIHIpOwo+ID4gKyAgICAgcmV0dXJuIDA7Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyBE RUZJTkVfUEVSX0NQVShzdHJ1Y3QgY2xvY2tfZXZlbnRfZGV2aWNlLCBjbGludF9jbG9ja19ldmVu dCkgPSB7Cj4gPiArICAgICAubmFtZSAgICAgICAgICAgICAgICAgICA9ICJjbGludF9jbG9ja2V2 ZW50IiwKPiA+ICsgICAgIC5mZWF0dXJlcyAgICAgICAgICAgICAgID0gQ0xPQ0tfRVZUX0ZFQVRf T05FU0hPVCwKPiA+ICsgICAgIC5yYXRpbmcgICAgICAgICA9IDEwMCwKPiA+ICsgICAgIC5zZXRf bmV4dF9ldmVudCA9IGNsaW50X2Nsb2NrX25leHRfZXZlbnQsCj4gPiArfTsKPiA+ICsKPiA+ICtz dGF0aWMgdTY0IGNsaW50X3JkdGltZShzdHJ1Y3QgY2xvY2tzb3VyY2UgKmNzKQo+ID4gK3sKPiA+ ICsgICAgIHJldHVybiByZWFkcV9yZWxheGVkKGNsaW50X3RpbWVyX3ZhbCk7Cj4gPiArfQo+ID4g Kwo+ID4gK3N0YXRpYyB1NjQgbm90cmFjZSBjbGludF9zY2hlZF9jbG9jayh2b2lkKQo+ID4gK3sK PiA+ICsgICAgIHJldHVybiByZWFkcV9yZWxheGVkKGNsaW50X3RpbWVyX3ZhbCk7Cj4gPiArfQo+ ID4gKwo+ID4gK3N0YXRpYyBzdHJ1Y3QgY2xvY2tzb3VyY2UgY2xpbnRfY2xvY2tzb3VyY2UgPSB7 Cj4gPiArICAgICAubmFtZSAgICAgICAgICAgPSAiY2xpbnRfY2xvY2tzb3VyY2UiLAo+ID4gKyAg ICAgLnJhdGluZyA9IDMwMCwKPiA+ICsgICAgIC5tYXNrICAgICAgICAgICA9IENMT0NLU09VUkNF X01BU0soNjQpLAo+ID4gKyAgICAgLmZsYWdzICAgICAgICAgID0gQ0xPQ0tfU09VUkNFX0lTX0NP TlRJTlVPVVMsCj4gPiArICAgICAucmVhZCAgICAgICAgICAgPSBjbGludF9yZHRpbWUsCj4KPiBX aGF0IGlmICFDT05GSUdfNjRCSVQKClRoZSBDTElOVCBjb3VudGVyIGlzIDY0Yml0IGZvciBib3Ro IDMyYml0IGFuZCA2NGJpdCBzeXN0ZW1zCmJ1dCBJIHNob3VsZCBoYXZlIHVzZWQgY2xpbnRfZ2V0 X2N5Y2xlczY0KCkgaW4gY2xpbnRfcmR0aW1lKCkuCkkgd2lsbCB1cGRhdGUgaXQuCgo+Cj4gPiAr fTsKPiA+ICsKPiA+ICtzdGF0aWMgaW50IGNsaW50X3RpbWVyX3N0YXJ0aW5nX2NwdSh1bnNpZ25l ZCBpbnQgY3B1KQo+ID4gK3sKPiA+ICsgICAgIHN0cnVjdCBjbG9ja19ldmVudF9kZXZpY2UgKmNl ID0gcGVyX2NwdV9wdHIoJmNsaW50X2Nsb2NrX2V2ZW50LCBjcHUpOwo+ID4gKwo+ID4gKyAgICAg Y2UtPmNwdW1hc2sgPSBjcHVtYXNrX29mKGNwdSk7Cj4gPiArICAgICBjbG9ja2V2ZW50c19jb25m aWdfYW5kX3JlZ2lzdGVyKGNlLCBjbGludF90aW1lcl9mcmVxLCAyMDAsIFVMT05HX01BWCk7Cj4K PiBUaGUgZnVuY3Rpb24gaXMgbm90IGltbXVuZSBhZ2FpbnN0IHJlZ2lzdGVyaW5nIHRoZSBzYW1l IGNsb2NrZXZlbnRzLiBJZgo+IHRoZSBDUFUgaXMgaG90cGx1Z2dlZCBzZXZlcmFsIHRpbWVzLCB0 aGlzIGZ1bmN0aW9uIHdpbGwgYmUgY2FsbGVkIGFnYWluCj4gYW5kIGFnYWluLiBXaHkgbm90IHJl bHkgb24gYSBmb3JfZWFjaF9wb3NzaWJsZV9jcHUgbG9vcCBpbiB0aGUgaW5pdAo+IGZ1bmN0aW9u ID8KPgo+ID4gKyAgICAgZW5hYmxlX3BlcmNwdV9pcnEoY2xpbnRfdGltZXJfaXJxLAo+ID4gKyAg ICAgICAgICAgICAgICAgICAgICAgaXJxX2dldF90cmlnZ2VyX3R5cGUoY2xpbnRfdGltZXJfaXJx KSk7Cj4KPiBXaHkgZG8geW91IHdhbnQgdG8gZW5hYmxlIC8gZGlzYWJsZSB0aGUgaW50ZXJycnVw dHMgPyBUaGUgc2hvdWxkIGJlCj4gYWxyZWFkeSBoYW5kbGUgYnkgdGhlIGhvdHBsdWcgZnJhbWV3 b3JrIG5vID8KClRoZSBwZXJDUFUgaW50ZXJydXB0cyBhcmUgbm90IGVuYWJsZWQgYnkgZGVmYXVs dC4gV2UgaGF2ZSB0bwpleHBsaWNpdGx5IGVuYWJsZS9kaXNhYmxlIHBlckNQVSBpbnRlcnJ1cHRz IGluIENQVSBob3RwbHVnIGNhbGxiYWNrcy4KCj4KPiA+ICsgICAgIHJldHVybiAwOwo+ID4gK30K PiA+ICsKPiA+ICtzdGF0aWMgaW50IGNsaW50X3RpbWVyX2R5aW5nX2NwdSh1bnNpZ25lZCBpbnQg Y3B1KQo+ID4gK3sKPiA+ICsgICAgIGRpc2FibGVfcGVyY3B1X2lycShjbGludF90aW1lcl9pcnEp Owo+ID4gKyAgICAgcmV0dXJuIDA7Cj4gPiArfQo+ID4gKwo+ID4gK3N0YXRpYyBpcnFyZXR1cm5f dCBjbGludF90aW1lcl9pbnRlcnJ1cHQoaW50IGlycSwgdm9pZCAqZGV2X2lkKQo+ID4gK3sKPiA+ ICsgICAgIHN0cnVjdCBjbG9ja19ldmVudF9kZXZpY2UgKmV2ZGV2ID0gdGhpc19jcHVfcHRyKCZj bGludF9jbG9ja19ldmVudCk7Cj4gPiArCj4gPiArICAgICBjc3JfY2xlYXIoQ1NSX0lFLCBJRV9U SUUpOwo+ID4gKyAgICAgZXZkZXYtPmV2ZW50X2hhbmRsZXIoZXZkZXYpOwo+ID4gKwo+ID4gKyAg ICAgcmV0dXJuIElSUV9IQU5ETEVEOwo+ID4gK30KPiA+ICsKPiA+ICtzdGF0aWMgaW50IF9faW5p dCBjbGludF90aW1lcl9pbml0X2R0KHN0cnVjdCBkZXZpY2Vfbm9kZSAqbnApCj4gPiArewo+ID4g KyAgICAgaW50IHJjOwo+ID4gKyAgICAgdTMyIGksIG5yX2lycXM7Cj4gPiArICAgICB2b2lkIF9f aW9tZW0gKmJhc2U7Cj4gPiArICAgICBzdHJ1Y3Qgb2ZfcGhhbmRsZV9hcmdzIG9pcnE7Cj4gPiAr Cj4gPiArICAgICAvKgo+ID4gKyAgICAgICogRW5zdXJlIHRoYXQgQ0xJTlQgZGV2aWNlIGludGVy cnVwdHMgYXJlIGVpdGhlciBSVl9JUlFfVElNRVIgb3IKPiA+ICsgICAgICAqIFJWX0lSUV9TT0ZU LiBJZiBpdCdzIGFueXRoaW5nIGVsc2UgdGhlbiB3ZSBpZ25vcmUgdGhlIGRldmljZS4KPiA+ICsg ICAgICAqLwo+ID4gKyAgICAgbnJfaXJxcyA9IG9mX2lycV9jb3VudChucCk7Cj4gPiArICAgICBm b3IgKGkgPSAwOyBpIDwgbnJfaXJxczsgaSsrKSB7Cj4gPiArICAgICAgICAgICAgIGlmIChvZl9p cnFfcGFyc2Vfb25lKG5wLCBpLCAmb2lycSkpIHsKPiA+ICsgICAgICAgICAgICAgICAgICAgICBw cl9lcnIoIiVwT0ZQOiBmYWlsZWQgdG8gcGFyc2UgaXJxICVkLlxuIiwgbnAsIGkpOwo+ID4gKyAg ICAgICAgICAgICAgICAgICAgIGNvbnRpbnVlOwo+ID4gKyAgICAgICAgICAgICB9Cj4gPiArCj4g PiArICAgICAgICAgICAgIGlmICgob2lycS5hcmdzX2NvdW50ICE9IDEpIHx8Cj4gPiArICAgICAg ICAgICAgICAgICAob2lycS5hcmdzWzBdICE9IFJWX0lSUV9USU1FUiAmJgo+ID4gKyAgICAgICAg ICAgICAgICAgIG9pcnEuYXJnc1swXSAhPSBSVl9JUlFfU09GVCkpIHsKPiA+ICsgICAgICAgICAg ICAgICAgICAgICBwcl9lcnIoIiVwT0ZQOiBpbnZhbGlkIGlycSAlZCAoaHdpcnEgJWQpXG4iLAo+ ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICBucCwgaSwgb2lycS5hcmdzWzBdKTsKPiA+ ICsgICAgICAgICAgICAgICAgICAgICByZXR1cm4gLUVOT0RFVjsKPiA+ICsgICAgICAgICAgICAg fQo+ID4gKwo+ID4gKyAgICAgICAgICAgICAvKiBGaW5kIHBhcmVudCBpcnEgZG9tYWluIGFuZCBt YXAgdGltZXIgaXJxICovCj4gPiArICAgICAgICAgICAgIGlmICghY2xpbnRfdGltZXJfaXJxICYm Cj4gPiArICAgICAgICAgICAgICAgICBvaXJxLmFyZ3NbMF0gPT0gUlZfSVJRX1RJTUVSICYmCj4g PiArICAgICAgICAgICAgICAgICBpcnFfZmluZF9ob3N0KG9pcnEubnApKQo+ID4gKyAgICAgICAg ICAgICAgICAgICAgIGNsaW50X3RpbWVyX2lycSA9IGlycV9vZl9wYXJzZV9hbmRfbWFwKG5wLCBp KTsKPiA+ICsgICAgIH0KPiA+ICsKPiA+ICsgICAgIC8qIElmIENMSU5UIHRpbWVyIGlycSBub3Qg Zm91bmQgdGhlbiBmYWlsICovCj4gPiArICAgICBpZiAoIWNsaW50X3RpbWVyX2lycSkgewo+ID4g KyAgICAgICAgICAgICBwcl9lcnIoIiVwT0ZQOiB0aW1lciBpcnEgbm90IGZvdW5kXG4iLCBucCk7 Cj4gPiArICAgICAgICAgICAgIHJldHVybiAtRU5PREVWOwo+ID4gKyAgICAgfQo+ID4gKwo+ID4g KyAgICAgYmFzZSA9IG9mX2lvbWFwKG5wLCAwKTsKPiA+ICsgICAgIGlmICghYmFzZSkgewo+ID4g KyAgICAgICAgICAgICBwcl9lcnIoIiVwT0ZQOiBjb3VsZCBub3QgbWFwIHJlZ2lzdGVyc1xuIiwg bnApOwo+ID4gKyAgICAgICAgICAgICByZXR1cm4gLUVOT0RFVjsKPiA+ICsgICAgIH0KPiA+ICsK PiA+ICsgICAgIGNsaW50X2lwaV9iYXNlID0gYmFzZSArIENMSU5UX0lQSV9PRkY7Cj4gPiArICAg ICBjbGludF90aW1lcl9jbXAgPSBiYXNlICsgQ0xJTlRfVElNRVJfQ01QX09GRjsKPiA+ICsgICAg IGNsaW50X3RpbWVyX3ZhbCA9IGJhc2UgKyBDTElOVF9USU1FUl9WQUxfT0ZGOwo+ID4gKyAgICAg Y2xpbnRfdGltZXJfZnJlcSA9IHJpc2N2X3RpbWViYXNlOwo+ID4gKwo+ID4gKyAgICAgcHJfaW5m bygiJXBPRlA6IHRpbWVyIHJ1bm5pbmcgYXQgJWxkIEh6XG4iLCBucCwgY2xpbnRfdGltZXJfZnJl cSk7Cj4gPiArCj4gPiArICAgICByYyA9IGNsb2Nrc291cmNlX3JlZ2lzdGVyX2h6KCZjbGludF9j bG9ja3NvdXJjZSwgY2xpbnRfdGltZXJfZnJlcSk7Cj4gPiArICAgICBpZiAocmMpIHsKPiA+ICsg ICAgICAgICAgICAgaW91bm1hcChiYXNlKTsKPiA+ICsgICAgICAgICAgICAgcHJfZXJyKCIlcE9G UDogY2xvY2tzb3VyY2UgcmVnaXN0ZXIgZmFpbGVkIFslZF1cbiIsIG5wLCByYyk7Cj4gPiArICAg ICAgICAgICAgIHJldHVybiByYzsKPiA+ICsgICAgIH0KPiA+ICsKPiA+ICsgICAgIHNjaGVkX2Ns b2NrX3JlZ2lzdGVyKGNsaW50X3NjaGVkX2Nsb2NrLCA2NCwgY2xpbnRfdGltZXJfZnJlcSk7Cj4g PiArCj4gPiArICAgICByYyA9IHJlcXVlc3RfcGVyY3B1X2lycShjbGludF90aW1lcl9pcnEsIGNs aW50X3RpbWVyX2ludGVycnVwdCwKPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAi Y2xpbnQtdGltZXIiLCAmY2xpbnRfY2xvY2tfZXZlbnQpOwo+ID4gKyAgICAgaWYgKHJjKSB7Cj4g PiArICAgICAgICAgICAgIGlvdW5tYXAoYmFzZSk7Cj4gPiArICAgICAgICAgICAgIHByX2Vycigi cmVnaXN0ZXJpbmcgcGVyY3B1IGlycSBmYWlsZWQgWyVkXVxuIiwgcmMpOwo+ID4gKyAgICAgICAg ICAgICByZXR1cm4gcmM7Cj4gPiArICAgICB9Cj4gPiArCj4gPiArICAgICByYyA9IGNwdWhwX3Nl dHVwX3N0YXRlKENQVUhQX0FQX0NMSU5UX1RJTUVSX1NUQVJUSU5HLAo+ID4gKyAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgImNsb2NrZXZlbnRzL2NsaW50L3RpbWVyOnN0YXJ0aW5nIiwKPiA+ ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgIGNsaW50X3RpbWVyX3N0YXJ0aW5nX2NwdSwK PiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgIGNsaW50X3RpbWVyX2R5aW5nX2NwdSk7 Cj4gPiArICAgICBpZiAocmMpIHsKPiA+ICsgICAgICAgICAgICAgZnJlZV9pcnEoY2xpbnRfdGlt ZXJfaXJxLCAmY2xpbnRfY2xvY2tfZXZlbnQpOwo+ID4gKyAgICAgICAgICAgICBpb3VubWFwKGJh c2UpOwo+ID4gKyAgICAgICAgICAgICBwcl9lcnIoIiVwT0ZQOiBjcHVocCBzZXR1cCBzdGF0ZSBm YWlsZWQgWyVkXVxuIiwgbnAsIHJjKTsKPiA+ICsgICAgICAgICAgICAgcmV0dXJuIHJjOwo+ID4g KyAgICAgfQo+ID4gKwo+ID4gKyAgICAgcmlzY3Zfc2V0X2lwaV9vcHMoJmNsaW50X2lwaV9vcHMp Owo+ID4gKyAgICAgY2xpbnRfY2xlYXJfaXBpKCk7Cj4gPiArCj4gPiArICAgICByZXR1cm4gMDsK PiA+ICt9Cj4gPiArCj4gPiArVElNRVJfT0ZfREVDTEFSRShjbGludF90aW1lciwgInJpc2N2LGNs aW50MCIsIGNsaW50X3RpbWVyX2luaXRfZHQpOwo+ID4gK1RJTUVSX09GX0RFQ0xBUkUoY2xpbnRf dGltZXIxLCAic2lmaXZlLGNsaW50MCIsIGNsaW50X3RpbWVyX2luaXRfZHQpOwo+ID4gZGlmZiAt LWdpdCBhL2luY2x1ZGUvbGludXgvY3B1aG90cGx1Zy5oIGIvaW5jbHVkZS9saW51eC9jcHVob3Rw bHVnLmgKPiA+IGluZGV4IDE5MTc3MmQ0YTRkNy4uMTQ1MWY0NjI1ODMzIDEwMDY0NAo+ID4gLS0t IGEvaW5jbHVkZS9saW51eC9jcHVob3RwbHVnLmgKPiA+ICsrKyBiL2luY2x1ZGUvbGludXgvY3B1 aG90cGx1Zy5oCj4gPiBAQCAtMTMyLDYgKzEzMiw3IEBAIGVudW0gY3B1aHBfc3RhdGUgewo+ID4g ICAgICAgQ1BVSFBfQVBfTUlQU19HSUNfVElNRVJfU1RBUlRJTkcsCj4gPiAgICAgICBDUFVIUF9B UF9BUkNfVElNRVJfU1RBUlRJTkcsCj4gPiAgICAgICBDUFVIUF9BUF9SSVNDVl9USU1FUl9TVEFS VElORywKPiA+ICsgICAgIENQVUhQX0FQX0NMSU5UX1RJTUVSX1NUQVJUSU5HLAo+ID4gICAgICAg Q1BVSFBfQVBfQ1NLWV9USU1FUl9TVEFSVElORywKPiA+ICAgICAgIENQVUhQX0FQX0hZUEVSVl9U SU1FUl9TVEFSVElORywKPiA+ICAgICAgIENQVUhQX0FQX0tWTV9TVEFSVElORywKPiA+Cj4KPgo+ IC0tCj4gPGh0dHA6Ly93d3cubGluYXJvLm9yZy8+IExpbmFyby5vcmcg4pSCIE9wZW4gc291cmNl IHNvZnR3YXJlIGZvciBBUk0gU29Dcwo+Cj4gRm9sbG93IExpbmFybzogIDxodHRwOi8vd3d3LmZh Y2Vib29rLmNvbS9wYWdlcy9MaW5hcm8+IEZhY2Vib29rIHwKPiA8aHR0cDovL3R3aXR0ZXIuY29t LyMhL2xpbmFyb29yZz4gVHdpdHRlciB8Cj4gPGh0dHA6Ly93d3cubGluYXJvLm9yZy9saW5hcm8t YmxvZy8+IEJsb2cKClJlZ2FyZHMsCkFudXAKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fCmxpbnV4LXJpc2N2IG1haWxpbmcgbGlzdApsaW51eC1yaXNjdkBs aXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlz dGluZm8vbGludXgtcmlzY3YK