From mboxrd@z Thu Jan  1 00:00:00 1970
From: Anup Patel <anup@brainfault.org>
Date: Fri, 13 Mar 2020 15:32:17 +0530
Subject: [PATCH v5 12/14] riscv: sifive: fu540: enable all cache ways from
 u-boot proper
In-Reply-To: <CAEUhbmWJ4Jn8=1pfUwgH5UcMGVwyexc+wfrOeSvd8sMktMR4XQ@mail.gmail.com>
References: <20200311070320.21323-1-pragnesh.patel@sifive.com>
 <20200311070320.21323-13-pragnesh.patel@sifive.com>
 <CAEUhbmWJ4Jn8=1pfUwgH5UcMGVwyexc+wfrOeSvd8sMktMR4XQ@mail.gmail.com>
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On Fri, Mar 13, 2020 at 2:31 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
> <pragnesh.patel@sifive.com> wrote:
> >
> > Enable all cache ways from u-boot proper.
>
> U-Boot
>
> >
> > Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> > ---
> >  board/sifive/fu540/Makefile |  1 +
> >  board/sifive/fu540/cache.c  | 20 ++++++++++++++++++++
> >  board/sifive/fu540/cache.h  | 13 +++++++++++++
> >  board/sifive/fu540/fu540.c  |  6 ++++--
> >  4 files changed, 38 insertions(+), 2 deletions(-)
> >  create mode 100644 board/sifive/fu540/cache.c
> >  create mode 100644 board/sifive/fu540/cache.h
> >
> > diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> > index b05e2f5807..3b867bbd89 100644
> > --- a/board/sifive/fu540/Makefile
> > +++ b/board/sifive/fu540/Makefile
> > @@ -3,6 +3,7 @@
> >  # Copyright (c) 2019 Western Digital Corporation or its affiliates.
> >
> >  obj-y  += fu540.o
> > +obj-y  += cache.o
> >
> >  ifdef CONFIG_SPL_BUILD
> >  obj-y += spl.o
> > diff --git a/board/sifive/fu540/cache.c b/board/sifive/fu540/cache.c
> > new file mode 100644
> > index 0000000000..a0bcd2ba48
> > --- /dev/null
> > +++ b/board/sifive/fu540/cache.c
>
> This should be put into arch/riscv/cpu/fu540/cache.c
>
> > @@ -0,0 +1,20 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2019 SiFive, Inc
> > + */
> > +#include <asm/io.h>
> > +
> > +/* Register offsets */
> > +#define CACHE_ENABLE           0x008
> > +
> > +/* Enable ways; allow cache to use these ways */
> > +void cache_enable_ways(u64 base_addr, u8 value)
> > +{
> > +       volatile u32 *enable = (volatile u32 *)(base_addr +
> > +                                         CACHE_ENABLE);
> > +       /* memory barrier */
> > +       mb();
> > +       (*enable) = value;
> > +       /* memory barrier */
> > +       mb();
> > +}
> > diff --git a/board/sifive/fu540/cache.h b/board/sifive/fu540/cache.h
> > new file mode 100644
> > index 0000000000..425124a23b
> > --- /dev/null
> > +++ b/board/sifive/fu540/cache.h
>
> arch/riscv/include/asm/arch-fu540/cache.h

Let's not entire FU540 directory under arch/riscv/cpu directory
just to have cache functions. The arch/riscv/cpu/generic is perfectly
suitable for FU540.

If we re-use arch/riscv/cpu/generic as-much as possible then
arch/riscv will be easy to maintain in future.

We can add arch/riscv/cpu/generic/cache.c which will do
things FU540 specific based on "#ifdef" or "DT compatible string".

>
> > @@ -0,0 +1,13 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (c) 2019 SiFive, Inc
> > + */
> > +
> > +#ifndef FU540_CACHE_H
> > +#define FU540_CACHE_H
> > +
> > +#define CACHE_CTRL_ADDR               _AC(0x2010000, UL)
> > +
> > +void cache_enable_ways(u64 base_addr, u8 value);
> > +
> > +#endif /* FU540_CACHE_H */
> > diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
> > index 89a65eb3fb..1d6c0c9bba 100644
> > --- a/board/sifive/fu540/fu540.c
> > +++ b/board/sifive/fu540/fu540.c
> > @@ -13,6 +13,8 @@
> >  #include <misc.h>
> >  #include <spl.h>
> >
> > +#include "cache.h"
> > +
> >  /*
> >   * This define is a value used for error/unknown serial.
> >   * If we really care about distinguishing errors and 0 is
> > @@ -111,8 +113,8 @@ int misc_init_r(void)
> >
> >  int board_init(void)
> >  {
> > -       /* For now nothing to do here. */
> > -
> > +       /* enable all cache ways */
> > +       cache_enable_ways(CACHE_CTRL_ADDR, 15);
> >         return 0;
> >  }
> >
>
> Regards,
> Bin

Regards,
Anup