Re: [PATCH 1/2] MIPS: Loongson-3: Enable COP2 usage in kernel

[Huacai Chen <chenhc@lemote.com>]

Hi, Maiej,

On Thu, May 14, 2020 at 6:42 AM Maciej W. Rozycki <macro@linux-mips.org> wrote:
>
> On Thu, 30 Apr 2020, Huacai Chen wrote:
>
> > > > diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
> > > > index ce40fbf..0f71540 100644
> > > > --- a/arch/mips/include/asm/mipsregs.h
> > > > +++ b/arch/mips/include/asm/mipsregs.h
> > > > @@ -386,6 +386,7 @@
> > > >  #define ST0_CU1                      0x20000000
> > > >  #define ST0_CU2                      0x40000000
> > > >  #define ST0_CU3                      0x80000000
> > > > +#define ST0_MM                       0x40000000      /* Loongson-3 naming */
> > >
> > > please use ST0_CU2, so everybody understands it's COO2
> > I see that there is already an alias  ST0_XX for ST0_CU3, and I think
> > use a ST0_MM for ST0_CU2 is more meaningful in some places (at least
> > in traps.c where ST0_XX is also used). If there are places only used
> > to describe the CU Mask (such as in stackframe.h), I will use ST0_CU2.
>
>  Well ST0_XX is not an alias, because the bit has a different meaning that
> has nothing to do with CP3.  It just happens to share the bit position in
> CP0.Status with ST0_CU3.  Yes, ST0_XX is misplaced and misnamed as it
> applies to R10k processors only, but it is our legacy from the old days of
> chaos and some three processor types supported.  This is similar to say
> ST0_ERL vs ST0_IEP, which also share the bit position in CP0.Status, but
> have different meanings each.
>
>  All this could have been cleaned up (e.g. s/ST0_XX/R10K_ST0_XX/) if
> someone had the incentive; I occasionally had and poked at these macros,
> but apparently missed this one and a couple of other ones.  Maybe on some
> rainy autumn evening...
>
>  However ST0_MM does enable CP2, even if a specific implementation, making
> it no different from ST0_CU2 really.
I have send a new version, could you please review that?Thank you.

>
>   Maciej
>
>
Huacai