Re: [PATCH V2] MIPS: Tidy up CP0.Config6 bits definition

[Huacai Chen <chenhc@lemote.com>]

OK, let me fix it.

Huacai

On Mon, Jun 1, 2020 at 10:13 AM Maciej W. Rozycki <macro@wdc.com> wrote:
>
> On Sat, 23 May 2020, Huacai Chen wrote:
>
> > CP0.Config6 is a Vendor-defined register whose bits definitions are
> > different from one to another. Recently, Xuerui's Loongson-3 patch and
> > Serge's P5600 patch make the definitions inconsistency and unclear.
> >
> > To make life easy, this patch tidy the definition up:
> > 1, Add a _MTI_ infix for proAptiv/P5600 feature bits;
> > 2, Add a _LOONGSON_ infix for Loongson-3 feature bits;
> > 3, Add bit6/bit7 definition for Loongson-3 which will be used later.
>
>  What a mess!  We use *prefixes* for vendor- or processor-specific names,
> e.g.:
>
> #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
> #define R4K_CONF_SW             (_ULCAST_(1) << 20)
> #define MTI_CONF7_PTC           (_ULCAST_(1) << 19)
>
> etc. and MIPS_ denotes a MIPS architectural (as in R1, R2, etc., i.e. not
> legacy) definition, e.g.:
>
> #define MIPS_CONF_VI            (_ULCAST_(1) <<  3)
>
>  So to be consistent these would have to be:
>
> > +/* Config6 feature bits for proAptiv/P5600 */
> > +
> >  /* Jump register cache prediction disable */
> > -#define MIPS_CONF6_JRCD              (_ULCAST_(1) << 0)
> > +#define MIPS_CONF6_MTI_JRCD          (_ULCAST_(1) << 0)
>
> #define MTI_CONF6_JRCD          (_ULCAST_(1) << 0)
>
> etc.
>
> > +/* Config6 feature bits for Loongson-3 */
> > +
> > +/* Loongson-3 internal timer bit */
> > +#define MIPS_CONF6_LOONGSON_INTIMER  (_ULCAST_(1) << 6)
>
> #define LOONGSON_CONF6_INTIMER  (_ULCAST_(1) << 6)
>
> etc.
>
>   Maciej