From mboxrd@z Thu Jan  1 00:00:00 1970
From: Moritz Fischer <moritz.fischer@ettus.com>
Date: Thu, 29 Jun 2017 10:38:12 -0700
Subject: [U-Boot] [PATCH] arm: zynq: Label whole PL part as fpga_full
	region
In-Reply-To: <def502ec0e99c259809172bdd9caea8043b3aff4.1498731247.git.michal.simek@xilinx.com>
References: <def502ec0e99c259809172bdd9caea8043b3aff4.1498731247.git.michal.simek@xilinx.com>
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To: u-boot@lists.denx.de

Hi Michal,

can you / did you send this to the kernel ML, too?

On Thu, Jun 29, 2017 at 3:14 AM, Michal Simek <michal.simek@xilinx.com> wrote:
> This will simplify dt overlay structure for the whole PL.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
> ---
>
>  arch/arm/dts/zynq-7000.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
> index 34fc6e5f8936..f993e19ef280 100644
> --- a/arch/arm/dts/zynq-7000.dtsi
> +++ b/arch/arm/dts/zynq-7000.dtsi
> @@ -38,6 +38,14 @@
>                 };
>         };
>
> +       fpga_full: fpga-full {
> +               compatible = "fpga-region";
> +               fpga-mgr = <&devcfg>;
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               ranges;
> +       };
> +
>         pmu at f8891000 {
>                 compatible = "arm,cortex-a9-pmu";
>                 interrupts = <0 5 4>, <0 6 4>;
> --
> 1.9.1
>
Thanks,

Moritz