From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:40542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SiluW-0001l5-J3 for qemu-devel@nongnu.org; Sun, 24 Jun 2012 08:27:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SiluU-0002P4-G1 for qemu-devel@nongnu.org; Sun, 24 Jun 2012 08:27:24 -0400 Received: from mail-ob0-f173.google.com ([209.85.214.173]:51419) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SiluU-0002Oy-8E for qemu-devel@nongnu.org; Sun, 24 Jun 2012 08:27:22 -0400 Received: by obbta14 with SMTP id ta14so5216835obb.4 for ; Sun, 24 Jun 2012 05:27:20 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1340195241-16620-1-git-send-email-peter.maydell@linaro.org> References: <1340195241-16620-1-git-send-email-peter.maydell@linaro.org> From: Blue Swirl Date: Sun, 24 Jun 2012 12:27:00 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PULL 00/33] target-arm queue List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, Anthony Liguori , Paul Brook On Wed, Jun 20, 2012 at 12:26 PM, Peter Maydell wrote: > This is a pullreq for outstanding target-arm patches. In fact it > only has my cp15 rework series in it. (No changes in that since the > v2 series I sent out some weeks back except for a tiny trivial fix > for a textual rebase conflict.) > > Please pull. Thanks, pulled. > > -- PMM > > > The following changes since commit 93bfef4c6e4b23caea9d51e1099d06433d8835= a4: > > =C2=A0Allow machines to configure the QEMU_VERSION that's exposed via har= dware (2012-06-19 13:36:56 -0500) > > are available in the git repository at: > =C2=A0git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-up= stream > > Peter Maydell (33): > =C2=A0 =C2=A0 =C2=A0target-arm: Fix 11MPCore cache type register value > =C2=A0 =C2=A0 =C2=A0target-arm: initial coprocessor register framework > =C2=A0 =C2=A0 =C2=A0hw/pxa2xx: Convert cp14 perf registers to new scheme > =C2=A0 =C2=A0 =C2=A0hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs > =C2=A0 =C2=A0 =C2=A0hw/pxa2xx_pic: Convert coprocessor registers to new s= cheme > =C2=A0 =C2=A0 =C2=A0target-arm: Remove old cpu_arm_set_cp_io infrastructu= re > =C2=A0 =C2=A0 =C2=A0target-arm: Add register_cp_regs_for_features() > =C2=A0 =C2=A0 =C2=A0target-arm: Convert debug registers to cp_reginfo > =C2=A0 =C2=A0 =C2=A0target-arm: Convert TEECR, TEEHBR to new scheme > =C2=A0 =C2=A0 =C2=A0target-arm: Convert WFI/barriers special cases to cp_= reginfo > =C2=A0 =C2=A0 =C2=A0target-arm: Convert TLS registers > =C2=A0 =C2=A0 =C2=A0target-arm: Convert performance monitor registers > =C2=A0 =C2=A0 =C2=A0target-arm: Convert generic timer cp15 regs > =C2=A0 =C2=A0 =C2=A0target-arm: Convert cp15 c3 register > =C2=A0 =C2=A0 =C2=A0target-arm: Convert MMU fault status cp15 registers > =C2=A0 =C2=A0 =C2=A0target-arm: Convert cp15 crn=3D2 registers > =C2=A0 =C2=A0 =C2=A0target-arm: Convert cp15 crn=3D13 registers > =C2=A0 =C2=A0 =C2=A0target-arm: Convert cp15 crn=3D10 registers > =C2=A0 =C2=A0 =C2=A0target-arm: Convert cp15 crn=3D15 registers > =C2=A0 =C2=A0 =C2=A0target-arm: Convert cp15 MMU TLB control > =C2=A0 =C2=A0 =C2=A0target-arm: Convert cp15 VA-PA translation registers > =C2=A0 =C2=A0 =C2=A0target-arm: convert cp15 crn=3D7 registers > =C2=A0 =C2=A0 =C2=A0target-arm: Convert cp15 crn=3D6 registers > =C2=A0 =C2=A0 =C2=A0target-arm: Convert cp15 crn=3D9 registers > =C2=A0 =C2=A0 =C2=A0target-arm: Convert cp15 crn=3D1 registers > =C2=A0 =C2=A0 =C2=A0target-arm: Convert cp15 crn=3D0 crm=3D{1,2} feature = registers > =C2=A0 =C2=A0 =C2=A0target-arm: Convert cp15 cache ID registers > =C2=A0 =C2=A0 =C2=A0target-arm: Convert MPIDR > =C2=A0 =C2=A0 =C2=A0target-arm: Convert final ID registers > =C2=A0 =C2=A0 =C2=A0target-arm: Remove c0_cachetype CPUARMState field > =C2=A0 =C2=A0 =C2=A0target-arm: Move block cache ops to new cp15 framewor= k > =C2=A0 =C2=A0 =C2=A0target-arm: Remove remaining old cp15 infrastructure > =C2=A0 =C2=A0 =C2=A0target-arm: Remove ARM_CPUID_* macros > > =C2=A0hw/pxa2xx.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0285 ++= +---- > =C2=A0hw/pxa2xx_pic.c =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 53 +- > =C2=A0linux-user/cpu-uname.c | =C2=A0 =C2=A05 +- > =C2=A0target-arm/cpu-qom.h =C2=A0 | =C2=A0 =C2=A05 + > =C2=A0target-arm/cpu.c =C2=A0 =C2=A0 =C2=A0 | =C2=A0230 +++++-- > =C2=A0target-arm/cpu.h =C2=A0 =C2=A0 =C2=A0 | =C2=A0248 +++++- > =C2=A0target-arm/helper.c =C2=A0 =C2=A0| 2070 +++++++++++++++++++++++++++= --------------------- > =C2=A0target-arm/helper.h =C2=A0 =C2=A0| =C2=A0 11 +- > =C2=A0target-arm/machine.c =C2=A0 | =C2=A0 =C2=A02 - > =C2=A0target-arm/op_helper.c | =C2=A0 42 +- > =C2=A0target-arm/translate.c | =C2=A0474 ++++-------- > =C2=A011 files changed, 1889 insertions(+), 1536 deletions(-)