From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:40467) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rr85V-0005aL-N9 for qemu-devel@nongnu.org; Sat, 28 Jan 2012 08:13:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rr85U-0002Cr-0C for qemu-devel@nongnu.org; Sat, 28 Jan 2012 08:13:01 -0500 Received: from mail-iy0-f173.google.com ([209.85.210.173]:54324) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rr85T-0002Cm-Rw for qemu-devel@nongnu.org; Sat, 28 Jan 2012 08:12:59 -0500 Received: by iahk25 with SMTP id k25so4082943iah.4 for ; Sat, 28 Jan 2012 05:12:59 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <1327505265-5976-1-git-send-email-peter.maydell@linaro.org> References: <1327505265-5976-1-git-send-email-peter.maydell@linaro.org> From: Blue Swirl Date: Sat, 28 Jan 2012 13:12:39 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PULL 0/5] target-arm queue List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, Aurelien Jarno On Wed, Jan 25, 2012 at 15:27, Peter Maydell wro= te: > Here's the latest target-arm pullreq. It includes Mark's fix for > config_base_register, which is in turn a dependency of the arm-devs > pullreq I'm about to send out, and which I'd like to get in before > Anthony's QOM patchset lands and invalidates it :-) > > Please pull. Thanks, pulled. > -- PMM > > > The following changes since commit 5b4448d27d7c6ff6e18a1edc8245cb1db783e3= 7c: > > =C2=A0Merge remote-tracking branch 'qemu-kvm/uq/master' into staging (201= 2-01-23 11:00:26 -0600) > > are available in the git repository at: > > =C2=A0git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-up= stream > > Mark Langsdorf (1): > =C2=A0 =C2=A0 =C2=A0arm: store the config_base_register during cpu_reset > > Peter Maydell (4): > =C2=A0 =C2=A0 =C2=A0target-arm: Fix implementation of TLB invalidate oper= ations > =C2=A0 =C2=A0 =C2=A0target-arm/helper.c: Don't assume softfloat int32 is = 32 bits only > =C2=A0 =C2=A0 =C2=A0Add dummy implementation of generic timer cp15 regist= ers > =C2=A0 =C2=A0 =C2=A0Add Cortex-A15 CPU definition > > =C2=A0target-arm/cpu.h =C2=A0 =C2=A0| =C2=A0 =C2=A02 + > =C2=A0target-arm/helper.c | =C2=A0 86 +++++++++++++++++++++++++++++++++++= +++++++--------- > =C2=A02 files changed, 73 insertions(+), 15 deletions(-)