From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:56180) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R8zZj-0002Bm-7q for qemu-devel@nongnu.org; Wed, 28 Sep 2011 15:13:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R8zZh-0001DP-T4 for qemu-devel@nongnu.org; Wed, 28 Sep 2011 15:13:47 -0400 Received: from mail-qy0-f180.google.com ([209.85.216.180]:62393) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R8zZh-0001DL-Qo for qemu-devel@nongnu.org; Wed, 28 Sep 2011 15:13:45 -0400 Received: by qyc1 with SMTP id 1so8998676qyc.4 for ; Wed, 28 Sep 2011 12:13:45 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1317230853-24970-1-git-send-email-peter.maydell@linaro.org> References: <1317230853-24970-1-git-send-email-peter.maydell@linaro.org> From: Blue Swirl Date: Wed, 28 Sep 2011 19:13:15 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 0/5] target-arm: Implement UDIV/SDIV and fused multiply-accumulate List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, patches@linaro.org On Wed, Sep 28, 2011 at 5:27 PM, Peter Maydell w= rote: > This patch series implements support in QEMU for some (user-mode) > instructions which are present on some recent processors > (eg Cortex-A15). > > The new instructions are UDIV/SDIV (previously only available as a Thumb > encoding for M-class cores, now an optional extension to ARMv7A), and > the fused-multiply-accumulate instructions VFMA, VFMS, VFNMA, VFNMS. > We don't (yet) support a specific processor for system mode with these > extensions, so they are enabled only for ARM_CPUID_ANY. > > The most interesting part of this is the fused multiply-accumulate > support which I have added to softfloat. Although this is only used > by ARM at the moment I've put in some flags which should be sufficient > for the variants provided by other architectures. (Specifically, > x86, Itanium and SPARC64 VI all need the "negate product" flag > since they have "-(a*b)+c" instructions. PPC needs the "negate > result" and "negate addend" flags.) > > The NaN handling hooks are not as clean as the 2-operand versions. > This is because there isn't really any consensus about what order > the operands in a fused-mac should be in; ARM uses c+(a*b), PPC > does something else, and so on. So even if there was more than > one 3-operand IEEE operation a generic "pick one of 3 NaNs" > function would be tricky; I opted to just be clear about the > fact this was fused-mac specific. I've provided the PPC implementation > of the NaN-selection function because the architecture manual was > helpfully clear about what it was. x86 and SPARC don't seem to > document the behaviour in this area :-( SPARC64 VII Extensions says this: "Also fnmadd and fnmsub behavior with rs1=3DNaN or rs2=3DNaN is different b= etween SPARC64 V and SPARC64 VII. SPARC64 VII outputs one of the NaN inputs as it is, while SPARC64 V outputs the one with the sign bit inverted." > I've thrown in the "reinstate target-specific NaN handling" patch > I posted earlier this week just to avoid possible patch conflicts. > > As usual, this has all been tested with a long run on my random > instruction generation testbed. > > > Peter Maydell (5): > =C2=A0softfloat: Reinstate accidentally disabled target-specific NaN > =C2=A0 =C2=A0handling > =C2=A0target-arm: v6 media multiply space: UNDEF on unassigned encodings > =C2=A0target-arm: Add ARM UDIV/SDIV support > =C2=A0softfloat: Implement fused multiply-add > =C2=A0target-arm: Implement VFPv4 fused multiply-accumulate insns > > =C2=A0fpu/softfloat-specialize.h | =C2=A0178 ++++++++++++++++++ > =C2=A0fpu/softfloat.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A043= 3 ++++++++++++++++++++++++++++++++++++++++++++ > =C2=A0fpu/softfloat.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 1= 4 ++ > =C2=A0target-arm/cpu.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 =C2=A0= 1 + > =C2=A0target-arm/helper.c =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 14 ++ > =C2=A0target-arm/helper.h =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 =C2=A03 + > =C2=A0target-arm/translate.c =C2=A0 =C2=A0 | =C2=A0115 +++++++++++- > =C2=A07 files changed, 754 insertions(+), 4 deletions(-) > > >