From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59861) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7uPT-0001Vh-EK for qemu-devel@nongnu.org; Wed, 14 Mar 2012 16:03:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7uPP-0008JN-6x for qemu-devel@nongnu.org; Wed, 14 Mar 2012 16:02:59 -0400 Received: from mail-iy0-f173.google.com ([209.85.210.173]:52547) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7uPP-0008J3-09 for qemu-devel@nongnu.org; Wed, 14 Mar 2012 16:02:55 -0400 Received: by iafj26 with SMTP id j26so3065746iaf.4 for ; Wed, 14 Mar 2012 13:02:53 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1331689198-11076-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331689198-11076-1-git-send-email-afaerber@suse.de> From: Blue Swirl Date: Wed, 14 Mar 2012 20:02:30 +0000 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?Q?Andreas_F=C3=A4rber?= Cc: Guan Xue-tao , qemu-devel@nongnu.org, Anthony Liguori On Wed, Mar 14, 2012 at 01:39, Andreas F=C3=A4rber wrote= : > Hello, > > Based on qom-cpu v4 and object_class_get_list() v2, this series converts > the UniCore32 CPU to QOM. Code-wise, target-unicore32 is pretty close to > target-arm and faces a similar issue of CPU-dependent init code, so let's > tackle it next. > > Patch 1 adds a UniCore32 CPU guest core (TCG) section to MAINTAINERS, > so that the target-unicore32 author gets notified of patches against his = code. > > Patch 2, based on feedback from Guan Xuetao, changes the license of most > target-unicore32 files from GPLv2 to GPLv2+. Anthony had contributed a > qemu_malloc() -> g_malloc() substitution that he can't relicense at this = time, > so leave that as GPLv2 and declare my following patches explicitly as GPL= v2+. Perhaps g_malloc() patch could be partially reverted and a new GPLv2+ patch applied which uses g_new()? > Patch 2 embeds CPUUniCore32State into UniCore32CPU. My new cpu-qom.h head= er > can be GPLv2+, but into cpu.c we're moving helper.c code so make it GPLv2= for now. > > Patches 4-7 move code out of the uc32_cpu_init() function and into classe= s. > > Regards, > Andreas > > Cc: Guan Xue-tao > Cc: Anthony Liguori > > Changes from former repo.or.cz qom-cpu[-wip] branch: > * Drop duplicate .instance_init. > > Andreas F=C3=A4rber (7): > =C2=A0MAINTAINERS: Add entry for UniCore32 > =C2=A0target-unicore32: Relicense to GPLv2+ > =C2=A0target-unicore32: QOM'ify CPU > =C2=A0target-unicore32: Store cp0 c0_cachetype in UniCore32CPUClass > =C2=A0target-unicore32: Store cp0 c1_sys in UniCore32CPUClass > =C2=A0target-unicore32: Store feature flags in UniCore32CPUClass > =C2=A0target-unicore32: Store ucf64 fpscr in UniCore32CPUClass > > =C2=A0MAINTAINERS =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0| =C2=A0 =C2=A05 ++ > =C2=A0Makefile.target =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| = =C2=A0 =C2=A01 + > =C2=A0target-unicore32/cpu-qom.h =C2=A0 | =C2=A0 81 +++++++++++++++++++++= +++++++++ > =C2=A0target-unicore32/cpu.c =C2=A0 =C2=A0 =C2=A0 | =C2=A0112 +++++++++++= +++++++++++++++++++++++++++++++ > =C2=A0target-unicore32/cpu.h =C2=A0 =C2=A0 =C2=A0 | =C2=A0 10 +--- > =C2=A0target-unicore32/helper.c =C2=A0 =C2=A0| =C2=A0 62 ++--------------= ------- > =C2=A0target-unicore32/helper.h =C2=A0 =C2=A0| =C2=A0 =C2=A05 +- > =C2=A0target-unicore32/op_helper.c | =C2=A0 =C2=A05 +- > =C2=A0target-unicore32/translate.c | =C2=A0 =C2=A05 +- > =C2=A09 files changed, 213 insertions(+), 73 deletions(-) > =C2=A0create mode 100644 target-unicore32/cpu-qom.h > =C2=A0create mode 100644 target-unicore32/cpu.c > > -- > 1.7.7 > >