From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Chiu Subject: Re: [PATCH] pinctrl: intel: save HOSTSW_OWN register over suspend/resume Date: Fri, 29 Mar 2019 16:38:20 +0800 Message-ID: References: <20171117064904.GZ17200@lahna.fi.intel.com> <20171121105205.GP22431@lahna.fi.intel.com> <20171121120422.GR22431@lahna.fi.intel.com> <20190327172940.GR3622@lahna.fi.intel.com> <20190328091729.GV9224@smile.fi.intel.com> <20190328123444.GX3622@lahna.fi.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: <20190328123444.GX3622@lahna.fi.intel.com> Sender: linux-kernel-owner@vger.kernel.org To: Mika Westerberg Cc: Daniel Drake , Andy Shevchenko , Heikki Krogerus , Linus Walleij , "open list:PIN CONTROL SUBSYSTEM" , Linux Kernel , Linux Upstreaming Team List-Id: linux-gpio@vger.kernel.org On Thu, Mar 28, 2019 at 8:34 PM Mika Westerberg wrote: > > On Thu, Mar 28, 2019 at 08:19:59PM +0800, Chris Chiu wrote: > > On Thu, Mar 28, 2019 at 5:38 PM Daniel Drake wrote: > > > > > > On Thu, Mar 28, 2019 at 5:17 PM Andy Shevchenko > > > wrote: > > > > Hmm... Can you confirm that laptop you declared as a fixed case and the > > > > mentioned here is the same one? > > > > > > They are definitely not the same exact unit - originally we had a > > > pre-production sample, and now we briefly diagnosed a real production > > > unit that was sold to a customer. There could be subtle motherboard > > > variations as you mention. > > > > > > > If it's the case, I recommend to ping Asus again and make them check and fix. > > > > > > We'll keep an eye open for any opportunities to go deeper here. > > > However further investigation on both our side and theirs is blocked > > > by not having any of the affected hardware (since the models are now > > > so old), so I'm not very optimistic that we'll be able to make > > > progress there. > > > > > > > Meanwhile, Mika's proposal sounds feasible and not so intrusive. We may > > > > implement this later on. > > > > > > Chris will work on implementing this for your consideration. > > > > > > Thanks for the quick feedback! > > > Daniel > > > > What if I modify the patch as follows? It doesn't save HOSTSW_OWN register. > > It just toggles the bit specifically for the IRQ GPIO pin after resume when DMI > > matches. > > I don't really like having quirks like this if we can avoid it and in > this case I think we can. Just always save HOSTSW_OWN and then restore > it if there is a GPIO requested and the value differs (and log a warning > or something like that). You mean save the content of hostsw_own register on padgroup based ex. communities[i].hostown[gpp] = readl(base + gpp * 4); And then check the hostown bit for the GPIO requested pin in intel_pinctrl_resume(), differs the hostsw_own bit on pin base (like padcfg), then restore the hostsw_own value of the padgroug which the GPIO pin is belonging to? I think what you mean should be a much more straightforward solution for this. Could you implement this in your way and we can try to help verification. Thanks. Chris