From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2352C47082 for ; Wed, 26 May 2021 20:19:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BC4EC613BF for ; Wed, 26 May 2021 20:19:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233416AbhEZUUc (ORCPT ); Wed, 26 May 2021 16:20:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233376AbhEZUUc (ORCPT ); Wed, 26 May 2021 16:20:32 -0400 Received: from mail-yb1-xb30.google.com (mail-yb1-xb30.google.com [IPv6:2607:f8b0:4864:20::b30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDA91C061574 for ; Wed, 26 May 2021 13:18:59 -0700 (PDT) Received: by mail-yb1-xb30.google.com with SMTP id f9so3865317ybo.6 for ; Wed, 26 May 2021 13:18:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=O0Ka4vBpdAyBWG8p8PcO/rjMwhjvUsXlTA1ts+xUeXQ=; b=lhiT/wAQpaU17DcX8sLxSf/H5gZKylSp3iz+OTJw4vaXVWrk/85EubveBZ1o/mm+Mr nDIR2Iw3BhSER8FZSPs3TkAsSpgEqlB+cVc6RqDBXxy3njg4zKZFYqMpWs2hp31QJ/KN h7VhDOBKS88RgJwl63pJ8iZX/SefPscfvaCd71FaL3cew/moQefAKPO1ArmR/eozDiOG htR8oTVk3bMHutK2ec3QkPkzipkgDmK6PvyMQH3M/ey1JsmKJA988dqj83iPcdjfTzGR e3qvB74G8K89jYNbts3iGBR13uo+gwm8ex46n63lijPkTE0aQFeh8hEUBrjuz8MfWoLr Kohw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=O0Ka4vBpdAyBWG8p8PcO/rjMwhjvUsXlTA1ts+xUeXQ=; b=KJ0K9YGYrjtRwW7y2bV5Ov4pCxaKBsfMsaQURJRmYuxCL2KDHV1P5F6vBxLy15azl7 J53LDkhF7ioauAh89I0mEsAh5U1t/AU86YRDu8z6ETSVRepf13j6EjxxbxtYEkB5mpC8 Ccfuv9WrY7ME4O7FoZNYWK9ASzNzzQAHzkpw91CC7dbODc+qlRyMrgs1WSswfFjKAnLe Ok2szMW/lqv1cIkUouNl1ywFE5BxzncaPNmevwWhk37LZSpyJQNypO/TKAYbVIDPmIbB U0IXCZYCaSz/MhrDyWXHlTg2c/r1Ll7EHZiFM9YKe5qBU0n5hu2yoji30X/1m0e2MXR+ 3p1Q== X-Gm-Message-State: AOAM530Lxr4J9kLgQu2xvCxND45Ow32nD5yrJFxgc2V7BqciZ/HwJBVe QldEWzxGxcma594Rnycy6RUdRrUoTK3e1055gCUxzwNBIwo= X-Google-Smtp-Source: ABdhPJxIy7DPGux6JC6GejgNMpeDZZc1iQbKluGiAvpRAxutBjFV8k2r7A1KKToWGiwXMexs4JZU34/D7kpN87m4ld4= X-Received: by 2002:a25:4f05:: with SMTP id d5mr51533969ybb.473.1622060339198; Wed, 26 May 2021 13:18:59 -0700 (PDT) MIME-Version: 1.0 References: <20210520120055.jl7vkqanv7wzeipq@pali> <20210520140529.rczoz3npjoadzfqc@pali> <4e972ecb-43df-639f-052d-8d1518bae9c0@broadcom.com> <87pmxgwh7o.wl-maz@kernel.org> <13a7e409-646d-40a7-17a0-4e4be011efb2@broadcom.com> <874keqvsf2.wl-maz@kernel.org> <964cc65e-5c44-8d29-9c08-013a64a5c6fd@broadcom.com> In-Reply-To: <964cc65e-5c44-8d29-9c08-013a64a5c6fd@broadcom.com> From: Sandor Bodo-Merle Date: Wed, 26 May 2021 22:18:47 +0200 Message-ID: Subject: Re: pcie-iproc-msi.c: Bug in Multi-MSI support? To: Ray Jui Cc: Marc Zyngier , =?UTF-8?Q?Pali_Roh=C3=A1r?= , linux-pci@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Wed, May 26, 2021 at 7:34 PM Ray Jui wrote: > > > Here's the thing. All Broadcom ARMv8 based SoCs have migrated to use > either gicv2m or gicv3-its for MSI/MSIX support. The platforms that > still use iProc event queue based MSI are only legacy ARMv7 based > platforms. Out of them: > > NSP - dual core > Cygnus - single core > HR2 - single core > > So based on this, it seems to me that it still makes sense to allow > multi-msi to be supported on single core platforms, and Sandor's company > seems to need such support in their particular use case. Sandor, can you > confirm? Right - we are using it in production on legacy ARMv7 SOCs. > > > Thanks. This makes sense. And it looks like this can be addressed > separately from the above issue. I'll have to allocate time to work on > this. In addition, I'd also need someone else with the NSP dual-core > platform to test it for me since we don't have these legacy platforms in > our office anymore. > I will be able to test patches on the XGS Katana2 SOC - which is dual core.