From: Stephane Eranian <eranian@google.com>
To: Jacob Shin <jacob.shin@amd.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
perfmon2-devel@lists.sourceforge.net
Subject: Re: [PATCH V6 0/6] perf, amd: Enable AMD family 15h northbridge counters
Date: Fri, 8 Feb 2013 11:55:23 +0100 [thread overview]
Message-ID: <CABPqkBTUM9KGN0pua2fP3Q+hwjrZvxgaESgfArtpOkAsGW-=9g@mail.gmail.com> (raw)
In-Reply-To: <20130206173125.GA11055@jshin-Toonie>
On Wed, Feb 6, 2013 at 6:31 PM, Jacob Shin <jacob.shin@amd.com> wrote:
> On Wed, Feb 06, 2013 at 11:26:23AM -0600, Jacob Shin wrote:
>> The following patchset enables 4 additional performance counters in
>> AMD family 15h processors that count northbridge events -- such as
>> number of DRAM accesses.
>>
>
> Here is the libpfm4 counterpart,
>
Patch applied to libpfm4 with fixes to make it pass the validation test suite.
Thanks.
>
> From acbc2e6f66dc131658a0fa1283d830327a44919f Mon Sep 17 00:00:00 2001
> From: Jacob Shin <jacob.shin@amd.com>
> Date: Thu, 31 Jan 2013 14:34:06 -0600
> Subject: [PATCH V2] Add AMD Family 15h northbridge performance events
>
> libpfm4 side support for the following Linux kernel patchset:
> http://lkml.org/lkml/2013/1/10/450
>
> Reference -- BIOS and Kernel Developer Guide (BKDG) for AMD Family 15h
> Models 00h-0Fh Processors:
> http://support.amd.com/us/Processor_TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf
> ---
> lib/events/amd64_events_fam15h.h | 1128 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 1128 insertions(+)
>
> diff --git a/lib/events/amd64_events_fam15h.h b/lib/events/amd64_events_fam15h.h
> index 7f654e8..8700ab2 100644
> --- a/lib/events/amd64_events_fam15h.h
> +++ b/lib/events/amd64_events_fam15h.h
> @@ -752,6 +752,910 @@ static const amd64_umask_t amd64_fam15h_l2_prefetcher_trigger_events[]={
> },
> };
>
> +static const amd64_umask_t amd64_fam15h_dram_accesses[]={
> + { .uname = "DCT0_PAGE_HIT",
> + .udesc = "DCT0 Page hit",
> + .ucode = 0x1,
> + },
> + { .uname = "DCT0_PAGE_MISS",
> + .udesc = "DCT0 Page Miss",
> + .ucode = 0x2,
> + },
> + { .uname = "DCT0_PAGE_CONFLICT",
> + .udesc = "DCT0 Page Conflict",
> + .ucode = 0x4,
> + },
> + { .uname = "DCT1_PAGE_HIT",
> + .udesc = "DCT1 Page hit",
> + .ucode = 0x8,
> + },
> + { .uname = "DCT1_PAGE_MISS",
> + .udesc = "DCT1 Page Miss",
> + .ucode = 0x10,
> + },
> + { .uname = "DCT1_PAGE_CONFLICT",
> + .udesc = "DCT1 Page Conflict",
> + .ucode = 0x20,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0x3f,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_dram_controller_page_table_overflows[]={
> + { .uname = "DCT0_PAGE_TABLE_OVERFLOW",
> + .udesc = "DCT0 Page Table Overflow",
> + .ucode = 0x1,
> + },
> + { .uname = "DCT1_PAGE_TABLE_OVERFLOW",
> + .udesc = "DCT1 Page Table Overflow",
> + .ucode = 0x2,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0x3,
> + .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_memory_controller_dram_command_slots_missed[]={
> + { .uname = "DCT0_COMMAND_SLOTS_MISSED",
> + .udesc = "DCT0 Command Slots Missed (in MemClks)",
> + .ucode = 0x1,
> + },
> + { .uname = "DCT1_COMMAND_SLOTS_MISSED",
> + .udesc = "DCT1 Command Slots Missed (in MemClks)",
> + .ucode = 0x2,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0x3,
> + .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_memory_controller_turnarounds[]={
> + { .uname = "DCT0_DIMM_TURNAROUND",
> + .udesc = "DCT0 DIMM (chip select) turnaround",
> + .ucode = 0x1,
> + },
> + { .uname = "DCT0_READ_WRITE_TURNAROUND",
> + .udesc = "DCT0 Read to write turnaround",
> + .ucode = 0x2,
> + },
> + { .uname = "DCT0_WRITE_READ_TURNAROUND",
> + .udesc = "DCT0 Write to read turnaround",
> + .ucode = 0x4,
> + },
> + { .uname = "DCT1_DIMM_TURNAROUND",
> + .udesc = "DCT1 DIMM (chip select) turnaround",
> + .ucode = 0x8,
> + },
> + { .uname = "DCT1_READ_WRITE_TURNAROUND",
> + .udesc = "DCT1 Read to write turnaround",
> + .ucode = 0x10,
> + },
> + { .uname = "DCT1_WRITE_READ_TURNAROUND",
> + .udesc = "DCT1 Write to read turnaround",
> + .ucode = 0x20,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0x3f,
> + .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_memory_controller_bypass_counter_saturation[]={
> + { .uname = "MEMORY_CONTROLLER_HIGH_PRIORITY_BYPASS",
> + .udesc = "Memory controller high priority bypass",
> + .ucode = 0x1,
> + },
> + { .uname = "MEMORY_CONTROLLER_MEDIUM_PRIORITY_BYPASS",
> + .udesc = "Memory controller medium priority bypass",
> + .ucode = 0x2,
> + },
> + { .uname = "DCT0_DCQ_BYPASS",
> + .udesc = "DCT0 DCQ bypass",
> + .ucode = 0x4,
> + },
> + { .uname = "DCT1_DCQ_BYPASS",
> + .udesc = "DCT1 DCQ bypass",
> + .ucode = 0x8,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0xf,
> + .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_thermal_status[]={
> + { .uname = "NUM_HTC_TRIP_POINT_CROSSED",
> + .udesc = "Number of times the HTC trip point is crossed",
> + .ucode = 0x4,
> + },
> + { .uname = "NUM_CLOCKS_HTC_PSTATE_INACTIVE",
> + .udesc = "Number of clocks HTC P-state is inactive",
> + .ucode = 0x20,
> + },
> + { .uname = "NUM_CLOCKS_HTC_PSTATE_ACTIVE",
> + .udesc = "Number of clocks HTC P-state is active",
> + .ucode = 0x40,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0x64,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_cpu_io_requests_to_memory_io[]={
> + { .uname = "REMOTE_IO_TO_LOCAL_IO",
> + .udesc = "Remote IO to Local IO",
> + .ucode = 0x61,
> + },
> + { .uname = "REMOTE_CPU_TO_LOCAL_IO",
> + .udesc = "Remote CPU to Local IO",
> + .ucode = 0x64,
> + },
> + { .uname = "LOCAL_IO_TO_REMOTE_IO",
> + .udesc = "Local IO to Remote IO",
> + .ucode = 0x91,
> + },
> + { .uname = "LOCAL_IO_TO_REMOTE_MEM",
> + .udesc = "Local IO to Remote Mem",
> + .ucode = 0x92,
> + },
> + { .uname = "LOCAL_CPU_TO_REMOTE_IO",
> + .udesc = "Local CPU to Remote IO",
> + .ucode = 0x94,
> + },
> + { .uname = "LOCAL_CPU_TO_REMOTE_MEM",
> + .udesc = "Local CPU to Remote Mem",
> + .ucode = 0x98,
> + },
> + { .uname = "LOCAL_IO_TO_LOCAL_IO",
> + .udesc = "Local IO to Local IO",
> + .ucode = 0xa1,
> + },
> + { .uname = "LOCAL_IO_TO_LOCAL_MEM",
> + .udesc = "Local IO to Local Mem",
> + .ucode = 0xa2,
> + },
> + { .uname = "LOCAL_CPU_TO_LOCAL_IO",
> + .udesc = "Local CPU to Local IO",
> + .ucode = 0xa4,
> + },
> + { .uname = "LOCAL_CPU_TO_LOCAL_MEM",
> + .udesc = "Local CPU to Local Mem",
> + .ucode = 0xa8,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_cache_block_commands[]={
> + { .uname = "VICTIM_BLOCK",
> + .udesc = "Victim Block (Writeback)",
> + .ucode = 0x1,
> + },
> + { .uname = "READ_BLOCK",
> + .udesc = "Read Block (Dcache load miss refill)",
> + .ucode = 0x4,
> + },
> + { .uname = "READ_BLOCK_SHARED",
> + .udesc = "Read Block Shared (Icache refill)",
> + .ucode = 0x8,
> + },
> + { .uname = "READ_BLOCK_MODIFIED",
> + .udesc = "Read Block Modified (Dcache store miss refill)",
> + .ucode = 0x10,
> + },
> + { .uname = "CHANGE_TO_DIRTY",
> + .udesc = "Change-to-Dirty (first store to clean block already in cache)",
> + .ucode = 0x20,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0x3d,
> + .uflags = AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_sized_commands[]={
> + { .uname = "NON-POSTED_SZWR_BYTE",
> + .udesc = "Non-Posted SzWr Byte (1-32 bytes). Typical Usage: Legacy or mapped IO, typically 1-4 bytes.",
> + .ucode = 0x1,
> + },
> + { .uname = "NON-POSTED_SZWR_DW",
> + .udesc = "Non-Posted SzWr DW (1-16 dwords). Typical Usage: Legacy or mapped IO, typically 1",
> + .ucode = 0x2,
> + },
> + { .uname = "POSTED_SZWR_BYTE",
> + .udesc = "Posted SzWr Byte (1-32 bytes). Typical Usage: Subcache-line DMA writes, size varies; also",
> + .ucode = 0x4,
> + },
> + { .uname = "POSTED_SZWR_DW",
> + .udesc = "Posted SzWr DW (1-16 dwords). Typical Usage: Block-oriented DMA writes, often cache-line",
> + .ucode = 0x8,
> + },
> + { .uname = "SZRD_BYTE",
> + .udesc = "SzRd Byte (4 bytes). Typical Usage: Legacy or mapped IO.",
> + .ucode = 0x10,
> + },
> + { .uname = "SZRD_DW",
> + .udesc = "SzRd DW (1-16 dwords). Typical Usage: Block-oriented DMA reads, typically cache-line size.",
> + .ucode = 0x20,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0x3f,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_probe_responses_and_upstream_requests[]={
> + { .uname = "PROBE_MISS",
> + .udesc = "Probe miss",
> + .ucode = 0x1,
> + },
> + { .uname = "PROBE_HIT_CLEAN",
> + .udesc = "Probe hit clean",
> + .ucode = 0x2,
> + },
> + { .uname = "PROBE_HIT_DIRTY_WITHOUT_MEMORY_CANCEL",
> + .udesc = "Probe hit dirty without memory cancel (probed by Sized Write or Change2Dirty)",
> + .ucode = 0x4,
> + },
> + { .uname = "PROBE_HIT_DIRTY_WITH_MEMORY_CANCEL",
> + .udesc = "Probe hit dirty with memory cancel (probed by DMA read or cache refill request)",
> + .ucode = 0x8,
> + },
> + { .uname = "UPSTREAM_DISPLAY_REFRESH_ISOC_READS",
> + .udesc = "Upstream display refresh/ISOC reads",
> + .ucode = 0x10,
> + },
> + { .uname = "UPSTREAM_NON-DISPLAY_REFRESH_READS",
> + .udesc = "Upstream non-display refresh reads",
> + .ucode = 0x20,
> + },
> + { .uname = "UPSTREAM_ISOC_WRITES",
> + .udesc = "Upstream ISOC writes",
> + .ucode = 0x40,
> + },
> + { .uname = "UPSTREAM_NON-ISOC_WRITES",
> + .udesc = "Upstream non-ISOC writes",
> + .ucode = 0x80,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0xff,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_gart_events[]={
> + { .uname = "GART_APERTURE_HIT_ON_ACCESS_FROM_CPU",
> + .udesc = "GART aperture hit on access from CPU",
> + .ucode = 0x1,
> + },
> + { .uname = "GART_APERTURE_HIT_ON_ACCESS_FROM_IO",
> + .udesc = "GART aperture hit on access from IO",
> + .ucode = 0x2,
> + },
> + { .uname = "GART_MISS",
> + .udesc = "GART miss",
> + .ucode = 0x4,
> + },
> + { .uname = "GART_REQUEST_HIT_TABLE_WALK_IN_PROGRESS",
> + .udesc = "GART Request hit table walk in progress",
> + .ucode = 0x8,
> + },
> + { .uname = "GART_MULTIPLE_TABLE_WALK_IN_PROGRESS",
> + .udesc = "GART multiple table walk in progress",
> + .ucode = 0x80,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0x8f,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_link_transmit_bandwidth[]={
> + { .uname = "COMMAND_DW_SENT",
> + .udesc = "Command DW sent",
> + .ucode = 0x1,
> + },
> + { .uname = "DATA_DW_SENT",
> + .udesc = "Data DW sent",
> + .ucode = 0x2,
> + },
> + { .uname = "BUFFER_RELEASE_DW_SENT",
> + .udesc = "Buffer release DW sent",
> + .ucode = 0x4,
> + },
> + { .uname = "NOP_DW_SENT",
> + .udesc = "NOP DW sent (idle)",
> + .ucode = 0x8,
> + },
> + { .uname = "ADDRESS_DW_SENT",
> + .udesc = "Address (including extensions) DW sent",
> + .ucode = 0x10,
> + },
> + { .uname = "PER_PACKET_CRC_SENT",
> + .udesc = "Per packet CRC sent",
> + .ucode = 0x20,
> + },
> + { .uname = "SUBLINK_COMMAND_DW_SENT",
> + .udesc = "Sublink Command DW sent",
> + .ucode = 0x81,
> + },
> + { .uname = "SUBLINK_DATA_DW_SENT",
> + .udesc = "Sublink Data DW sent",
> + .ucode = 0x82,
> + },
> + { .uname = "SUBLINK_BUFFER_RELEASE_DW_SENT",
> + .udesc = "Sublink Buffer release DW sent",
> + .ucode = 0x84,
> + },
> + { .uname = "SUBLINK_NOP_DW_SENT",
> + .udesc = "Sublink NOP DW sent (idle)",
> + .ucode = 0x88,
> + },
> + { .uname = "SUBLINK_ADDRESS_DW_SENT",
> + .udesc = "Sublink Address (including extensions) DW sent",
> + .ucode = 0x90,
> + },
> + { .uname = "SUBLINK_PER_PACKET_CRC_SENT",
> + .udesc = "Sublink Per packet CRC sent",
> + .ucode = 0xa0,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0x3f,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_cpu_to_dram_requests_to_target_node[]={
> + { .uname = "LOCAL_TO_NODE_0",
> + .udesc = "From Local node to Node 0",
> + .ucode = 0x1,
> + },
> + { .uname = "LOCAL_TO_NODE_1",
> + .udesc = "From Local node to Node 1",
> + .ucode = 0x2,
> + },
> + { .uname = "LOCAL_TO_NODE_2",
> + .udesc = "From Local node to Node 2",
> + .ucode = 0x4,
> + },
> + { .uname = "LOCAL_TO_NODE_3",
> + .udesc = "From Local node to Node 3",
> + .ucode = 0x8,
> + },
> + { .uname = "LOCAL_TO_NODE_4",
> + .udesc = "From Local node to Node 4",
> + .ucode = 0x10,
> + },
> + { .uname = "LOCAL_TO_NODE_5",
> + .udesc = "From Local node to Node 5",
> + .ucode = 0x20,
> + },
> + { .uname = "LOCAL_TO_NODE_6",
> + .udesc = "From Local node to Node 6",
> + .ucode = 0x40,
> + },
> + { .uname = "LOCAL_TO_NODE_7",
> + .udesc = "From Local node to Node 7",
> + .ucode = 0x80,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0xff,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_io_to_dram_requests_to_target_node[]={
> + { .uname = "LOCAL_TO_NODE_0",
> + .udesc = "From Local node to Node 0",
> + .ucode = 0x1,
> + },
> + { .uname = "LOCAL_TO_NODE_1",
> + .udesc = "From Local node to Node 1",
> + .ucode = 0x2,
> + },
> + { .uname = "LOCAL_TO_NODE_2",
> + .udesc = "From Local node to Node 2",
> + .ucode = 0x4,
> + },
> + { .uname = "LOCAL_TO_NODE_3",
> + .udesc = "From Local node to Node 3",
> + .ucode = 0x8,
> + },
> + { .uname = "LOCAL_TO_NODE_4",
> + .udesc = "From Local node to Node 4",
> + .ucode = 0x10,
> + },
> + { .uname = "LOCAL_TO_NODE_5",
> + .udesc = "From Local node to Node 5",
> + .ucode = 0x20,
> + },
> + { .uname = "LOCAL_TO_NODE_6",
> + .udesc = "From Local node to Node 6",
> + .ucode = 0x40,
> + },
> + { .uname = "LOCAL_TO_NODE_7",
> + .udesc = "From Local node to Node 7",
> + .ucode = 0x80,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0xff,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_cpu_read_command_requests_to_target_node_0_3[]={
> + { .uname = "READ_BLOCK_LOCAL_TO_NODE_0",
> + .udesc = "Read block From Local node to Node 0",
> + .ucode = 0x11,
> + },
> + { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_0",
> + .udesc = "Read block shared From Local node to Node 0",
> + .ucode = 0x12,
> + },
> + { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_0",
> + .udesc = "Read block modified From Local node to Node 0",
> + .ucode = 0x14,
> + },
> + { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_0",
> + .udesc = "Change-to-Dirty From Local node to Node 0",
> + .ucode = 0x18,
> + },
> + { .uname = "READ_BLOCK_LOCAL_TO_NODE_1",
> + .udesc = "Read block From Local node to Node 1",
> + .ucode = 0x21,
> + },
> + { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_1",
> + .udesc = "Read block shared From Local node to Node 1",
> + .ucode = 0x22,
> + },
> + { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_1",
> + .udesc = "Read block modified From Local node to Node 1",
> + .ucode = 0x24,
> + },
> + { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_1",
> + .udesc = "Change-to-Dirty From Local node to Node 1",
> + .ucode = 0x28,
> + },
> + { .uname = "READ_BLOCK_LOCAL_TO_NODE_2",
> + .udesc = "Read block From Local node to Node 2",
> + .ucode = 0x41,
> + },
> + { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_2",
> + .udesc = "Read block shared From Local node to Node 2",
> + .ucode = 0x42,
> + },
> + { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_2",
> + .udesc = "Read block modified From Local node to Node 2",
> + .ucode = 0x44,
> + },
> + { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_2",
> + .udesc = "Change-to-Dirty From Local node to Node 2",
> + .ucode = 0x48,
> + },
> + { .uname = "READ_BLOCK_LOCAL_TO_NODE_3",
> + .udesc = "Read block From Local node to Node 3",
> + .ucode = 0x81,
> + },
> + { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_3",
> + .udesc = "Read block shared From Local node to Node 3",
> + .ucode = 0x82,
> + },
> + { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_3",
> + .udesc = "Read block modified From Local node to Node 3",
> + .ucode = 0x84,
> + },
> + { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_3",
> + .udesc = "Change-to-Dirty From Local node to Node 3",
> + .ucode = 0x88,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0xff,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_cpu_read_command_requests_to_target_node_4_7[]={
> + { .uname = "READ_BLOCK_LOCAL_TO_NODE_4",
> + .udesc = "Read block From Local node to Node 4",
> + .ucode = 0x11,
> + },
> + { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_4",
> + .udesc = "Read block shared From Local node to Node 4",
> + .ucode = 0x12,
> + },
> + { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_4",
> + .udesc = "Read block modified From Local node to Node 4",
> + .ucode = 0x14,
> + },
> + { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_4",
> + .udesc = "Change-to-Dirty From Local node to Node 4",
> + .ucode = 0x18,
> + },
> + { .uname = "READ_BLOCK_LOCAL_TO_NODE_5",
> + .udesc = "Read block From Local node to Node 5",
> + .ucode = 0x21,
> + },
> + { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_5",
> + .udesc = "Read block shared From Local node to Node 5",
> + .ucode = 0x22,
> + },
> + { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_5",
> + .udesc = "Read block modified From Local node to Node 5",
> + .ucode = 0x24,
> + },
> + { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_5",
> + .udesc = "Change-to-Dirty From Local node to Node 5",
> + .ucode = 0x28,
> + },
> + { .uname = "READ_BLOCK_LOCAL_TO_NODE_6",
> + .udesc = "Read block From Local node to Node 6",
> + .ucode = 0x41,
> + },
> + { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_6",
> + .udesc = "Read block shared From Local node to Node 6",
> + .ucode = 0x42,
> + },
> + { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_6",
> + .udesc = "Read block modified From Local node to Node 6",
> + .ucode = 0x44,
> + },
> + { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_6",
> + .udesc = "Change-to-Dirty From Local node to Node 6",
> + .ucode = 0x48,
> + },
> + { .uname = "READ_BLOCK_LOCAL_TO_NODE_7",
> + .udesc = "Read block From Local node to Node 7",
> + .ucode = 0x81,
> + },
> + { .uname = "READ_BLOCK_SHARED_LOCAL_TO_NODE_7",
> + .udesc = "Read block shared From Local node to Node 7",
> + .ucode = 0x82,
> + },
> + { .uname = "READ_BLOCK_MODIFIED_LOCAL_TO_NODE_7",
> + .udesc = "Read block modified From Local node to Node 7",
> + .ucode = 0x84,
> + },
> + { .uname = "CHANGE_TO_DIRTY_LOCAL_TO_NODE_7",
> + .udesc = "Change-to-Dirty From Local node to Node 7",
> + .ucode = 0x88,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0xff,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_cpu_command_requests_to_target_node[]={
> + { .uname = "READ_SIZED_LOCAL_TO_NODE_0",
> + .udesc = "Read Sized From Local node to Node 0",
> + .ucode = 0x11,
> + },
> + { .uname = "WRITE_SIZED_LOCAL_TO_NODE_0",
> + .udesc = "Write Sized From Local node to Node 0",
> + .ucode = 0x12,
> + },
> + { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_0",
> + .udesc = "Victim Block From Local node to Node 0",
> + .ucode = 0x14,
> + },
> + { .uname = "READ_SIZED_LOCAL_TO_NODE_1",
> + .udesc = "Read Sized From Local node to Node 1",
> + .ucode = 0x21,
> + },
> + { .uname = "WRITE_SIZED_LOCAL_TO_NODE_1",
> + .udesc = "Write Sized From Local node to Node 1",
> + .ucode = 0x22,
> + },
> + { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_1",
> + .udesc = "Victim Block From Local node to Node 1",
> + .ucode = 0x24,
> + },
> + { .uname = "READ_SIZED_LOCAL_TO_NODE_2",
> + .udesc = "Read Sized From Local node to Node 2",
> + .ucode = 0x41,
> + },
> + { .uname = "WRITE_SIZED_LOCAL_TO_NODE_2",
> + .udesc = "Write Sized From Local node to Node 2",
> + .ucode = 0x42,
> + },
> + { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_2",
> + .udesc = "Victim Block From Local node to Node 2",
> + .ucode = 0x44,
> + },
> + { .uname = "READ_SIZED_LOCAL_TO_NODE_3",
> + .udesc = "Read Sized From Local node to Node 3",
> + .ucode = 0x81,
> + },
> + { .uname = "WRITE_SIZED_LOCAL_TO_NODE_3",
> + .udesc = "Write Sized From Local node to Node 3",
> + .ucode = 0x82,
> + },
> + { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_3",
> + .udesc = "Victim Block From Local node to Node 3",
> + .ucode = 0x84,
> + },
> + { .uname = "READ_SIZED_LOCAL_TO_NODE_4",
> + .udesc = "Read Sized From Local node to Node 4",
> + .ucode = 0x19,
> + },
> + { .uname = "WRITE_SIZED_LOCAL_TO_NODE_4",
> + .udesc = "Write Sized From Local node to Node 4",
> + .ucode = 0x1a,
> + },
> + { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_4",
> + .udesc = "Victim Block From Local node to Node 4",
> + .ucode = 0x1c,
> + },
> + { .uname = "READ_SIZED_LOCAL_TO_NODE_5",
> + .udesc = "Read Sized From Local node to Node 5",
> + .ucode = 0x29,
> + },
> + { .uname = "WRITE_SIZED_LOCAL_TO_NODE_5",
> + .udesc = "Write Sized From Local node to Node 5",
> + .ucode = 0x2a,
> + },
> + { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_5",
> + .udesc = "Victim Block From Local node to Node 5",
> + .ucode = 0x2c,
> + },
> + { .uname = "READ_SIZED_LOCAL_TO_NODE_6",
> + .udesc = "Read Sized From Local node to Node 6",
> + .ucode = 0x49,
> + },
> + { .uname = "WRITE_SIZED_LOCAL_TO_NODE_6",
> + .udesc = "Write Sized From Local node to Node 6",
> + .ucode = 0x4a,
> + },
> + { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_6",
> + .udesc = "Victim Block From Local node to Node 6",
> + .ucode = 0x4c,
> + },
> + { .uname = "READ_SIZED_LOCAL_TO_NODE_7",
> + .udesc = "Read Sized From Local node to Node 7",
> + .ucode = 0x89,
> + },
> + { .uname = "WRITE_SIZED_LOCAL_TO_NODE_7",
> + .udesc = "Write Sized From Local node to Node 7",
> + .ucode = 0x8a,
> + },
> + { .uname = "VICTIM_BLOCK_LOCAL_TO_NODE_7",
> + .udesc = "Victim Block From Local node to Node 7",
> + .ucode = 0x8c,
> + },
> + { .uname = "ALL_LOCAL_TO_NODE_0_3",
> + .udesc = "All From Local node to Node 0-3",
> + .ucode = 0xf7,
> + .uflags= AMD64_FL_NCOMBO,
> + },
> + { .uname = "ALL_LOCAL_TO_NODE_4_7",
> + .udesc = "All From Local node to Node 4-7",
> + .ucode = 0xff,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_request_cache_status_0[]={
> + { .uname = "PROBE_HIT_S",
> + .udesc = "Probe Hit S",
> + .ucode = 0x1,
> + },
> + { .uname = "PROBE_HIT_E",
> + .udesc = "Probe Hit E",
> + .ucode = 0x2,
> + },
> + { .uname = "PROBE_HIT_MUW_OR_O",
> + .udesc = "Probe Hit MuW or O",
> + .ucode = 0x4,
> + },
> + { .uname = "PROBE_HIT_M",
> + .udesc = "Probe Hit M",
> + .ucode = 0x8,
> + },
> + { .uname = "PROBE_MISS",
> + .udesc = "Probe Miss",
> + .ucode = 0x10,
> + },
> + { .uname = "DIRECTED_PROBE",
> + .udesc = "Directed Probe",
> + .ucode = 0x20,
> + },
> + { .uname = "TRACK_CACHE_STAT_FOR_RDBLK",
> + .udesc = "Track Cache Stat for RdBlk",
> + .ucode = 0x40,
> + },
> + { .uname = "TRACK_CACHE_STAT_FOR_RDBLKS",
> + .udesc = "Track Cache Stat for RdBlkS",
> + .ucode = 0x80,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0xff,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_request_cache_status_1[]={
> + { .uname = "PROBE_HIT_S",
> + .udesc = "Probe Hit S",
> + .ucode = 0x1,
> + },
> + { .uname = "PROBE_HIT_E",
> + .udesc = "Probe Hit E",
> + .ucode = 0x2,
> + },
> + { .uname = "PROBE_HIT_MUW_OR_O",
> + .udesc = "Probe Hit MuW or O",
> + .ucode = 0x4,
> + },
> + { .uname = "PROBE_HIT_M",
> + .udesc = "Probe Hit M",
> + .ucode = 0x8,
> + },
> + { .uname = "PROBE_MISS",
> + .udesc = "Probe Miss",
> + .ucode = 0x10,
> + },
> + { .uname = "DIRECTED_PROBE",
> + .udesc = "Directed Probe",
> + .ucode = 0x20,
> + },
> + { .uname = "TRACK_CACHE_STAT_FOR_CHGTODIRTY",
> + .udesc = "Track Cache Stat for ChgToDirty",
> + .ucode = 0x40,
> + },
> + { .uname = "TRACK_CACHE_STAT_FOR_RDBLKM",
> + .udesc = "Track Cache Stat for RdBlkM",
> + .ucode = 0x80,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0xff,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_memory_controller_requests[]={
> + { .uname = "WRITE_REQUESTS_TO_DCT",
> + .udesc = "Write requests sent to the DCT",
> + .ucode = 0x1,
> + },
> + { .uname = "READ_REQUESTS_TO_DCT",
> + .udesc = "Read requests (including prefetch requests) sent to the DCT",
> + .ucode = 0x2,
> + },
> + { .uname = "PREFETCH_REQUESTS_TO_DCT",
> + .udesc = "Prefetch requests sent to the DCT",
> + .ucode = 0x4,
> + },
> + { .uname = "32_BYTES_SIZED_WRITES",
> + .udesc = "32 Bytes Sized Writes",
> + .ucode = 0x8,
> + },
> + { .uname = "64_BYTES_SIZED_WRITES",
> + .udesc = "64 Bytes Sized Writes",
> + .ucode = 0x10,
> + },
> + { .uname = "32_BYTES_SIZED_READS",
> + .udesc = "32 Bytes Sized Reads",
> + .ucode = 0x20,
> + },
> + { .uname = "64_BYTE_SIZED_READS",
> + .udesc = "64 Byte Sized Reads",
> + .ucode = 0x40,
> + },
> + { .uname = "READ_REQUESTS_TO_DCT_WHILE_WRITES_PENDING",
> + .udesc = "Read requests sent to the DCT while writes requests are pending in the DCT",
> + .ucode = 0x80,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0xff,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_read_request_to_l3_cache[]={
> + { .uname = "READ_BLOCK_EXCLUSIVE",
> + .udesc = "Read Block Exclusive (Data cache read)",
> + .ucode = 0xf1,
> + },
> + { .uname = "READ_BLOCK_SHARED",
> + .udesc = "Read Block Shared (Instruction cache read)",
> + .ucode = 0xf2,
> + },
> + { .uname = "READ_BLOCK_MODIFY",
> + .udesc = "Read Block Modify",
> + .ucode = 0xf4,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0xf7,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_l3_fills_caused_by_l2_evictions[]={
> + { .uname = "SHARED",
> + .udesc = "Shared",
> + .ucode = 0xf1,
> + },
> + { .uname = "EXCLUSIVE",
> + .udesc = "Exclusive",
> + .ucode = 0xf2,
> + },
> + { .uname = "OWNED",
> + .udesc = "Owned",
> + .ucode = 0xf4,
> + },
> + { .uname = "MODIFIED",
> + .udesc = "Modified",
> + .ucode = 0xf8,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0xff,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_l3_evictions[]={
> + { .uname = "SHARED",
> + .udesc = "Shared",
> + .ucode = 0x1,
> + },
> + { .uname = "EXCLUSIVE",
> + .udesc = "Exclusive",
> + .ucode = 0x2,
> + },
> + { .uname = "OWNED",
> + .udesc = "Owned",
> + .ucode = 0x4,
> + },
> + { .uname = "MODIFIED",
> + .udesc = "Modified",
> + .ucode = 0x8,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0xf,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> +static const amd64_umask_t amd64_fam15h_l3_latency[]={
> + { .uname = "L3_REQUEST_CYCLE",
> + .udesc = "L3 Request cycle count.",
> + .ucode = 0x1,
> + },
> + { .uname = "L3_REQUEST",
> + .udesc = "L3 request count.",
> + .ucode = 0x2,
> + },
> + { .uname = "ALL",
> + .udesc = "All sub-events selected",
> + .ucode = 0x3,
> + .uflags= AMD64_FL_NCOMBO | AMD64_FL_DFL,
> + },
> +};
> +
> static const amd64_entry_t amd64_fam15h_pe[]={
> { .name = "DISPATCHED_FPU_OPS",
> .desc = "FPU Pipe Assignment",
> @@ -1256,4 +2160,228 @@ static const amd64_entry_t amd64_fam15h_pe[]={
> .modmsk = AMD64_FAM15H_ATTRS,
> .code = 0x1d8,
> },
> +{ .name = "DRAM_ACCESSES",
> + .desc = "DRAM Accesses",
> + .code = 0xe0,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_dram_accesses),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_dram_accesses,
> +},
> +{ .name = "DRAM_CONTROLLER_PAGE_TABLE_OVERFLOWS",
> + .desc = "DRAM Controller Page Table Overflows",
> + .code = 0xe1,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_dram_controller_page_table_overflows),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_dram_controller_page_table_overflows,
> +},
> +{ .name = "MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED",
> + .desc = "Memory Controller DRAM Command Slots Missed",
> + .code = 0xe2,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_memory_controller_dram_command_slots_missed),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_memory_controller_dram_command_slots_missed,
> +},
> +{ .name = "MEMORY_CONTROLLER_TURNAROUNDS",
> + .desc = "Memory Controller Turnarounds",
> + .code = 0xe3,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_memory_controller_turnarounds),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_memory_controller_turnarounds,
> +},
> +{ .name = "MEMORY_CONTROLLER_BYPASS_COUNTER_SATURATION",
> + .desc = "Memory Controller Bypass Counter Saturation",
> + .code = 0xe4,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_memory_controller_bypass_counter_saturation),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_memory_controller_bypass_counter_saturation,
> +},
> +{ .name = "THERMAL_STATUS",
> + .desc = "Thermal Status",
> + .code = 0xe8,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_thermal_status),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_thermal_status,
> +},
> +{ .name = "CPU_IO_REQUESTS_TO_MEMORY_IO",
> + .desc = "CPU/IO Requests to Memory/IO",
> + .code = 0xe9,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_cpu_io_requests_to_memory_io),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_cpu_io_requests_to_memory_io,
> +},
> +{ .name = "CACHE_BLOCK_COMMANDS",
> + .desc = "Cache Block Commands",
> + .code = 0xea,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_cache_block_commands),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_cache_block_commands,
> +},
> +{ .name = "SIZED_COMMANDS",
> + .desc = "Sized Commands",
> + .code = 0xeb,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_sized_commands),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_sized_commands,
> +},
> +{ .name = "PROBE_RESPONSES_AND_UPSTREAM_REQUESTS",
> + .desc = "Probe Responses and Upstream Requests",
> + .code = 0xec,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_probe_responses_and_upstream_requests),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_probe_responses_and_upstream_requests,
> +},
> +{ .name = "GART_EVENTS",
> + .desc = "GART Events",
> + .code = 0xee,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_gart_events),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_gart_events,
> +},
> +{ .name = "LINK_TRANSMIT_BANDWIDTH_LINK_0",
> + .desc = "Link Transmit Bandwidth Link 0",
> + .code = 0xf6,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_link_transmit_bandwidth),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_link_transmit_bandwidth,
> +},
> +{ .name = "LINK_TRANSMIT_BANDWIDTH_LINK_1",
> + .desc = "Link Transmit Bandwidth Link 1",
> + .code = 0xf7,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_link_transmit_bandwidth),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_link_transmit_bandwidth,
> +},
> +{ .name = "LINK_TRANSMIT_BANDWIDTH_LINK_2",
> + .desc = "Link Transmit Bandwidth Link 2",
> + .code = 0xf8,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_link_transmit_bandwidth),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_link_transmit_bandwidth,
> +},
> +{ .name = "LINK_TRANSMIT_BANDWIDTH_LINK_3",
> + .desc = "Link Transmit Bandwidth Link 3",
> + .code = 0x1f9,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_link_transmit_bandwidth),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_link_transmit_bandwidth,
> +},
> +{ .name = "CPU_TO_DRAM_REQUESTS_TO_TARGET_NODE",
> + .desc = "CPU to DRAM Requests to Target Node",
> + .code = 0x1e0,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_cpu_to_dram_requests_to_target_node),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_cpu_to_dram_requests_to_target_node,
> +},
> +{ .name = "IO_TO_DRAM_REQUESTS_TO_TARGET_NODE",
> + .desc = "IO to DRAM Requests to Target Node",
> + .code = 0x1e1,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_io_to_dram_requests_to_target_node),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_io_to_dram_requests_to_target_node,
> +},
> +{ .name = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_0_3",
> + .desc = "CPU Read Command Latency to Target Node 0-3",
> + .code = 0x1e2,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_cpu_read_command_requests_to_target_node_0_3),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_cpu_read_command_requests_to_target_node_0_3,
> +},
> +{ .name = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_0_3",
> + .desc = "CPU Read Command Requests to Target Node 0-3",
> + .code = 0x1e3,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_cpu_read_command_requests_to_target_node_0_3),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_cpu_read_command_requests_to_target_node_0_3,
> +},
> +{ .name = "CPU_READ_COMMAND_LATENCY_TO_TARGET_NODE_4_7",
> + .desc = "CPU Read Command Latency to Target Node 4-7",
> + .code = 0x1e4,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_cpu_read_command_requests_to_target_node_4_7),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_cpu_read_command_requests_to_target_node_4_7,
> +},
> +{ .name = "CPU_READ_COMMAND_REQUESTS_TO_TARGET_NODE_4_7",
> + .desc = "CPU Read Command Requests to Target Node 4-7",
> + .code = 0x1e5,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_cpu_read_command_requests_to_target_node_4_7),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_cpu_read_command_requests_to_target_node_4_7,
> +},
> +{ .name = "CPU_COMMAND_LATENCY_TO_TARGET_NODE",
> + .desc = "CPU Command Latency to Target Node",
> + .code = 0x1e6,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_cpu_command_requests_to_target_node),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_cpu_command_requests_to_target_node,
> +},
> +{ .name = "CPU_REQUESTS_TO_TARGET_NODE",
> + .desc = "CPU Requests to Target Node",
> + .code = 0x1e7,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_cpu_command_requests_to_target_node),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_cpu_command_requests_to_target_node,
> +},
> +{ .name = "REQUEST_CACHE_STATUS_0",
> + .desc = "Request Cache Status 0",
> + .code = 0x1ea,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_request_cache_status_0),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_request_cache_status_0,
> +},
> +{ .name = "REQUEST_CACHE_STATUS_1",
> + .desc = "Request Cache Status 1",
> + .code = 0x1eb,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_request_cache_status_1),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_request_cache_status_1,
> +},
> +{ .name = "MEMORY_CONTROLLER_REQUESTS",
> + .desc = "Memory Controller Requests",
> + .code = 0x1f0,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_memory_controller_requests),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_memory_controller_requests,
> +},
> +{ .name = "READ_REQUEST_TO_L3_CACHE",
> + .desc = "Read Request to L3 Cache",
> + .code = 0x4e0,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_read_request_to_l3_cache),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_read_request_to_l3_cache,
> +},
> +{ .name = "L3_CACHE_MISSES",
> + .desc = "L3 Cache Misses",
> + .code = 0x4e1,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_read_request_to_l3_cache),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_read_request_to_l3_cache,
> +},
> +{ .name = "L3_FILLS_CAUSED_BY_L2_EVICTIONS",
> + .desc = "L3 Fills caused by L2 Evictions",
> + .code = 0x4e2,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_l3_fills_caused_by_l2_evictions),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_l3_fills_caused_by_l2_evictions,
> +},
> +{ .name = "L3_EVICTIONS",
> + .desc = "L3 Evictions",
> + .code = 0x4e3,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_l3_evictions),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_l3_evictions,
> +},
> +{ .name = "NON_CANCELED_L3_READ_REQUESTS",
> + .desc = "Non-canceled L3 Read Requests",
> + .code = 0x4ed,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_read_request_to_l3_cache),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_read_request_to_l3_cache,
> +},
> +{ .name = "L3_LATENCY",
> + .desc = "L3 Latency",
> + .code = 0x4ef,
> + .numasks = LIBPFM_ARRAY_SIZE(amd64_fam15h_l3_latency),
> + .ngrp = 1,
> + .umasks = amd64_fam15h_l3_latency,
> +},
> };
> --
> 1.7.9.5
>
>
prev parent reply other threads:[~2013-02-08 10:55 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-06 17:26 [PATCH V6 0/6] perf, amd: Enable AMD family 15h northbridge counters Jacob Shin
2013-02-06 17:26 ` [PATCH 1/6] perf, amd: Rework northbridge event constraints handler Jacob Shin
2013-02-06 20:28 ` [tip:perf/core] perf/x86/amd: " tip-bot for Robert Richter
2013-02-06 17:26 ` [PATCH 2/6] perf, amd: Generalize northbridge constraints code for family 15h Jacob Shin
2013-02-06 20:29 ` [tip:perf/core] perf/x86/amd: " tip-bot for Robert Richter
2013-02-06 17:26 ` [PATCH 3/6] perf, amd: Use proper naming scheme for AMD bit field definitions Jacob Shin
2013-02-06 20:30 ` [tip:perf/core] perf/x86/amd: " tip-bot for Jacob Shin
2013-02-06 17:26 ` [PATCH 4/6] perf, x86: Move MSR address offset calculation to architecture specific files Jacob Shin
2013-02-06 20:31 ` [tip:perf/core] perf/x86: " tip-bot for Jacob Shin
2013-02-06 17:26 ` [PATCH 5/6] perf, x86: Allow for architecture specific RDPMC indexes Jacob Shin
2013-02-06 20:32 ` [tip:perf/core] perf/x86: " tip-bot for Jacob Shin
2013-02-06 17:26 ` [PATCH 6/6] perf, amd: Enable northbridge performance counters on AMD family 15h Jacob Shin
2013-02-07 17:57 ` Jacob Shin
2013-02-07 17:58 ` Stephane Eranian
2013-02-07 19:09 ` Ingo Molnar
2013-02-08 11:16 ` Stephane Eranian
2013-02-11 16:26 ` Jacob Shin
2013-02-15 20:51 ` Jacob Shin
2013-02-18 8:30 ` [tip:perf/core] perf/x86/amd: " tip-bot for Jacob Shin
2013-02-06 17:31 ` [PATCH V6 0/6] perf, amd: Enable AMD family 15h northbridge counters Jacob Shin
2013-02-08 10:55 ` Stephane Eranian [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CABPqkBTUM9KGN0pua2fP3Q+hwjrZvxgaESgfArtpOkAsGW-=9g@mail.gmail.com' \
--to=eranian@google.com \
--cc=jacob.shin@amd.com \
--cc=linux-kernel@vger.kernel.org \
--cc=perfmon2-devel@lists.sourceforge.net \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.