From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rodrigo Vivi Subject: Re: [PATCH 38/89] drm/i915/skl: Implement drm_plane vfuncs Date: Wed, 17 Sep 2014 15:08:33 -0700 Message-ID: References: <1409830075-11139-1-git-send-email-damien.lespiau@intel.com> <1409830075-11139-39-git-send-email-damien.lespiau@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0258583747==" Return-path: Received: from mail-wg0-f42.google.com (mail-wg0-f42.google.com [74.125.82.42]) by gabe.freedesktop.org (Postfix) with ESMTP id 1D6CD6E022 for ; Wed, 17 Sep 2014 15:08:34 -0700 (PDT) Received: by mail-wg0-f42.google.com with SMTP id x12so2056565wgg.25 for ; Wed, 17 Sep 2014 15:08:34 -0700 (PDT) In-Reply-To: <1409830075-11139-39-git-send-email-damien.lespiau@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Damien Lespiau Cc: intel-gfx List-Id: intel-gfx@lists.freedesktop.org --===============0258583747== Content-Type: multipart/alternative; boundary=f46d043c7f04e43cd805034a1b5d --f46d043c7f04e43cd805034a1b5d Content-Type: text/plain; charset=UTF-8 On Thu, Sep 4, 2014 at 4:27 AM, Damien Lespiau wrote: > SKL Uses the same hardware for all planes now, so called "universal" > planes. Ie both the primary planes and sprite planes share the same > logic. This patch implements the drm_plane vfuncs for "sprites" ie > planes that aren't the primary plane. > > v2: Couple of fixes: > - Actually enabled the planes and fix the plane number > > Signed-off-by: Damien Lespiau > --- > drivers/gpu/drm/i915/i915_reg.h | 31 +++++- > drivers/gpu/drm/i915/intel_sprite.c | 206 > +++++++++++++++++++++++++++++++++++- > 2 files changed, 235 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index c293dab..0159f2d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4513,7 +4513,9 @@ enum punit_power_well { > #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24) > #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24) > #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) > -#define PLANE_CTL_KEY_ENABLE (1 << 22) > +#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) > +#define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21) > +#define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21) > Oh ignore my comments on patch 12/89 regarding these bits! ;) > #define PLANE_CTL_ORDER_BGRX (0 << 20) > #define PLANE_CTL_ORDER_RGBX (1 << 20) > #define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16) > @@ -4548,6 +4550,12 @@ enum punit_power_well { > #define _PLANE_OFFSET_1_A 0x701a4 > #define _PLANE_OFFSET_2_A 0x702a4 > #define _PLANE_OFFSET_3_A 0x703a4 > +#define _PLANE_KEYVAL_1_A 0x70194 > +#define _PLANE_KEYVAL_2_A 0x70294 > +#define _PLANE_KEYMSK_1_A 0x70198 > +#define _PLANE_KEYMSK_2_A 0x70298 > +#define _PLANE_KEYMAX_1_A 0x701a0 > +#define _PLANE_KEYMAX_2_A 0x702a0 > > #define _PLANE_CTL_1_B 0x71180 > #define _PLANE_CTL_2_B 0x71280 > @@ -4604,6 +4612,27 @@ enum punit_power_well { > #define PLANE_OFFSET(pipe, plane) \ > _PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) > > +#define _PLANE_KEYVAL_1_B 0x71194 > +#define _PLANE_KEYVAL_2_B 0x71294 > +#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, > _PLANE_KEYVAL_1_B) > +#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, > _PLANE_KEYVAL_2_B) > +#define PLANE_KEYVAL(pipe, plane) \ > + _PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) > + > +#define _PLANE_KEYMSK_1_B 0x71198 > +#define _PLANE_KEYMSK_2_B 0x71298 > +#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, > _PLANE_KEYMSK_1_B) > +#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, > _PLANE_KEYMSK_2_B) > +#define PLANE_KEYMSK(pipe, plane) \ > + _PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) > + > +#define _PLANE_KEYMAX_1_B 0x711a0 > +#define _PLANE_KEYMAX_2_B 0x712a0 > +#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, > _PLANE_KEYMAX_1_B) > +#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, > _PLANE_KEYMAX_2_B) > +#define PLANE_KEYMAX(pipe, plane) \ > + _PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) > + > /* VBIOS regs */ > #define VGACNTRL 0x71400 > # define VGA_DISP_DISABLE (1 << 31) > diff --git a/drivers/gpu/drm/i915/intel_sprite.c > b/drivers/gpu/drm/i915/intel_sprite.c > index 07a74ef..57e7190 100644 > --- a/drivers/gpu/drm/i915/intel_sprite.c > +++ b/drivers/gpu/drm/i915/intel_sprite.c > @@ -139,6 +139,184 @@ static void intel_update_primary_plane(struct > intel_crtc *crtc) > } > > static void > +skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, > + struct drm_framebuffer *fb, > + struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, > + unsigned int crtc_w, unsigned int crtc_h, > + uint32_t x, uint32_t y, > + uint32_t src_w, uint32_t src_h) > +{ > + struct drm_device *dev = drm_plane->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_plane *intel_plane = to_intel_plane(drm_plane); > + const int pipe = intel_plane->pipe; > + const int plane = intel_plane->plane + 1; A comment above to remind skl doesn't have the primary would be good. > + u32 plane_ctl, stride; > + int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); > + > + plane_ctl = I915_READ(PLANE_CTL(pipe, plane)); > + > + /* Mask out pixel format bits in case we change it */ > + plane_ctl &= ~PLANE_CTL_FORMAT_MASK; > + plane_ctl &= ~PLANE_CTL_ORDER_RGBX; > + plane_ctl &= ~PLANE_CTL_YUV422_ORDER_MASK; > + plane_ctl &= ~PLANE_CTL_TILED_MASK; > + plane_ctl &= ~PLANE_CTL_ALPHA_MASK; > + > + /* Trickle feed has to be enabled */ > + plane_ctl &= ~PLANE_CTL_TRICKLE_FEED_DISABLE; > + > + switch (fb->pixel_format) { > + case DRM_FORMAT_RGB565: > + plane_ctl |= PLANE_CTL_FORMAT_RGB_565; > + break; > + case DRM_FORMAT_XBGR8888: > + plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | > PLANE_CTL_ORDER_RGBX; > + break; > + case DRM_FORMAT_XRGB8888: > + plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; > + break; > + /* > + * XXX: For ARBG/ABGR formats we default to expecting scanout > buffers > + * to be already pre-multiplied. We need to add a knob (or a > different > + * DRM_FORMAT) for user-space to configure that. > + */ > + case DRM_FORMAT_ABGR8888: > + plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | > + PLANE_CTL_ORDER_RGBX | > + PLANE_CTL_ALPHA_SW_PREMULTIPLY; > + break; > + case DRM_FORMAT_ARGB8888: > + plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | > + PLANE_CTL_ALPHA_SW_PREMULTIPLY; > + break; > + case DRM_FORMAT_YUYV: > + plane_ctl |= PLANE_CTL_FORMAT_YUV422 | > PLANE_CTL_YUV422_YUYV; > + break; > + case DRM_FORMAT_YVYU: > + plane_ctl |= PLANE_CTL_FORMAT_YUV422 | > PLANE_CTL_YUV422_YVYU; > + break; > + case DRM_FORMAT_UYVY: > + plane_ctl |= PLANE_CTL_FORMAT_YUV422 | > PLANE_CTL_YUV422_UYVY; > + break; > + case DRM_FORMAT_VYUY: > + plane_ctl |= PLANE_CTL_FORMAT_YUV422 | > PLANE_CTL_YUV422_VYUY; > + break; > + default: > + BUG(); > + } > + > + switch (obj->tiling_mode) { > + case I915_TILING_NONE: > + stride = fb->pitches[0] >> 6; > + break; > + case I915_TILING_X: > + plane_ctl |= PLANE_CTL_TILED_X; > + stride = fb->pitches[0] >> 9; > + break; > + default: > + BUG(); > + } > + > + plane_ctl |= PLANE_CTL_ENABLE; > + plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE; > + > + intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h, > + pixel_size, true, > + src_w != crtc_w || src_h != crtc_h); > + > + /* Sizes are 0 based */ > + src_w--; > + src_h--; > + crtc_w--; > + crtc_h--; > + > + I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x); > + I915_WRITE(PLANE_STRIDE(pipe, plane), stride); > + I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); > + I915_WRITE(PLANE_SIZE(pipe, plane), (crtc_h << 16) | crtc_w); > + I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); > + I915_WRITE(PLANE_SURF(pipe, plane), i915_gem_obj_ggtt_offset(obj)); > + POSTING_READ(PLANE_SURF(pipe, plane)); > +} > + > +static void > +skl_disable_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc) > +{ > + struct drm_device *dev = drm_plane->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_plane *intel_plane = to_intel_plane(drm_plane); > + const int pipe = intel_plane->pipe; > + const int plane = intel_plane->plane + 1; > + > + I915_WRITE(PLANE_CTL(pipe, plane), > + I915_READ(PLANE_CTL(pipe, plane)) & ~PLANE_CTL_ENABLE); > + > + /* Activate double buffered register update */ > + I915_WRITE(PLANE_CTL(pipe, plane), 0); > + POSTING_READ(PLANE_CTL(pipe, plane)); > + > + intel_update_sprite_watermarks(drm_plane, crtc, 0, 0, 0, false, > false); > +} > + > +static int > +skl_update_colorkey(struct drm_plane *drm_plane, > + struct drm_intel_sprite_colorkey *key) > +{ > + struct drm_device *dev = drm_plane->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_plane *intel_plane = to_intel_plane(drm_plane); > + const int pipe = intel_plane->pipe; > + const int plane = intel_plane->plane; > + u32 plane_ctl; > + > + I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); > + I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); > + I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); > + > + plane_ctl = I915_READ(PLANE_CTL(pipe, plane)); > + plane_ctl &= ~PLANE_CTL_KEY_ENABLE_MASK; > + if (key->flags & I915_SET_COLORKEY_DESTINATION) > + plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; > + else if (key->flags & I915_SET_COLORKEY_SOURCE) > + plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; > + I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); > + > + POSTING_READ(PLANE_CTL(pipe, plane)); > + > + return 0; > +} > + > +static void > +skl_get_colorkey(struct drm_plane *drm_plane, > + struct drm_intel_sprite_colorkey *key) > +{ > + struct drm_device *dev = drm_plane->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_plane *intel_plane = to_intel_plane(drm_plane); > + const int pipe = intel_plane->pipe; > + const int plane = intel_plane->plane; > + u32 plane_ctl; > + > + key->min_value = I915_READ(PLANE_KEYVAL(pipe, plane)); > + key->max_value = I915_READ(PLANE_KEYMAX(pipe, plane)); > + key->channel_mask = I915_READ(PLANE_KEYMSK(pipe, plane)); > + > + plane_ctl = I915_READ(PLANE_CTL(pipe, plane)); > + > + switch (plane_ctl & PLANE_CTL_KEY_ENABLE_MASK) { > + case PLANE_CTL_KEY_ENABLE_DESTINATION: > + key->flags = I915_SET_COLORKEY_DESTINATION; > + break; > + case PLANE_CTL_KEY_ENABLE_SOURCE: > + key->flags = I915_SET_COLORKEY_SOURCE; > + break; > + default: > + key->flags = I915_SET_COLORKEY_NONE; > + } > +} > + > +static void > vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, > struct drm_framebuffer *fb, > struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, > @@ -1305,6 +1483,18 @@ static uint32_t vlv_plane_formats[] = { > DRM_FORMAT_VYUY, > }; > > +static uint32_t skl_plane_formats[] = { > + DRM_FORMAT_RGB565, > + DRM_FORMAT_ABGR8888, > + DRM_FORMAT_ARGB8888, > + DRM_FORMAT_XBGR8888, > + DRM_FORMAT_XRGB8888, > + DRM_FORMAT_YUYV, > + DRM_FORMAT_YVYU, > + DRM_FORMAT_UYVY, > + DRM_FORMAT_VYUY, > +}; > + > int > intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) > { > @@ -1368,7 +1558,21 @@ intel_plane_init(struct drm_device *dev, enum pipe > pipe, int plane) > num_plane_formats = ARRAY_SIZE(snb_plane_formats); > } > break; > - > + case 9: > + /* > + * FIXME: Skylake planes can be scaled (with some > restrictions), > + * but this is for another time. > + */ > + intel_plane->can_scale = false; > + intel_plane->max_downscale = 1; > + intel_plane->update_plane = skl_update_plane; > + intel_plane->disable_plane = skl_disable_plane; > + intel_plane->update_colorkey = skl_update_colorkey; > + intel_plane->get_colorkey = skl_get_colorkey; > + > + plane_formats = skl_plane_formats; > + num_plane_formats = ARRAY_SIZE(skl_plane_formats); > + break; > default: > kfree(intel_plane); > return -ENODEV; > -- > 1.8.3.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > Reviewed-by: Rodrigo Vivi -- Rodrigo Vivi Blog: http://blog.vivi.eng.br --f46d043c7f04e43cd805034a1b5d Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable


On Thu, Sep 4, 2014 at 4:27 AM, Damien Lespiau <damien.lespiau@= intel.com> wrote:
SKL Uses= the same hardware for all planes now, so called "universal"
planes. Ie both the primary planes and sprite planes share the same
logic. This patch implements the drm_plane vfuncs for "sprites" i= e
planes that aren't the primary plane.

v2: Couple of fixes:
=C2=A0 - Actually enabled the planes and fix the plane number

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
=C2=A0drivers/gpu/drm/i915/i915_reg.h=C2=A0 =C2=A0 =C2=A0|=C2=A0 31 +++++-<= br> =C2=A0drivers/gpu/drm/i915/intel_sprite.c | 206 +++++++++++++++++++++++++++= ++++++++-
=C2=A02 files changed, 235 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_re= g.h
index c293dab..0159f2d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4513,7 +4513,9 @@ enum punit_power_well {
=C2=A0#define=C2=A0 =C2=A0PLANE_CTL_FORMAT_INDEXED=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0( 12 << 24)
=C2=A0#define=C2=A0 =C2=A0PLANE_CTL_FORMAT_RGB_565=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0( 14 << 24)
=C2=A0#define=C2=A0 =C2=A0PLANE_CTL_PIPE_CSC_ENABLE=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 (1 << 23)
-#define=C2=A0 =C2=A0PLANE_CTL_KEY_ENABLE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 22)
+#define=C2=A0 =C2=A0PLANE_CTL_KEY_ENABLE_MASK=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 (0x3 << 21)
+#define=C2=A0 =C2=A0PLANE_CTL_KEY_ENABLE_SOURCE=C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 (=C2=A0 1 << 21)
+#define=C2=A0 =C2=A0PLANE_CTL_KEY_ENABLE_DESTINATION=C2=A0 =C2=A0 =C2=A0(= =C2=A0 2 << 21)

Oh ignore my comm= ents on patch 12/89 regarding these bits! ;)
=C2=A0
=C2=A0#define=C2=A0 =C2=A0PLANE_CTL_ORDER_BGRX=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(0 << 20)
=C2=A0#define=C2=A0 =C2=A0PLANE_CTL_ORDER_RGBX=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1 << 20)
=C2=A0#define=C2=A0 =C2=A0PLANE_CTL_YUV422_ORDER_MASK=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 (0x3 << 16)
@@ -4548,6 +4550,12 @@ enum punit_power_well {
=C2=A0#define _PLANE_OFFSET_1_A=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x701a4
=C2=A0#define _PLANE_OFFSET_2_A=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x702a4
=C2=A0#define _PLANE_OFFSET_3_A=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x703a4
+#define _PLANE_KEYVAL_1_A=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x70194
+#define _PLANE_KEYVAL_2_A=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x70294
+#define _PLANE_KEYMSK_1_A=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x70198
+#define _PLANE_KEYMSK_2_A=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x70298
+#define _PLANE_KEYMAX_1_A=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x701a0
+#define _PLANE_KEYMAX_2_A=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x702a0

=C2=A0#define _PLANE_CTL_1_B=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x71180
=C2=A0#define _PLANE_CTL_2_B=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x71280
@@ -4604,6 +4612,27 @@ enum punit_power_well {
=C2=A0#define PLANE_OFFSET(pipe, plane)=C2=A0 =C2=A0 =C2=A0 \
=C2=A0 =C2=A0 =C2=A0 =C2=A0 _PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFF= SET_2(pipe))

+#define _PLANE_KEYVAL_1_B=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x71194
+#define _PLANE_KEYVAL_2_B=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x71294
+#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL= _1_B)
+#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL= _2_B)
+#define PLANE_KEYVAL(pipe, plane)=C2=A0 =C2=A0 =C2=A0 \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEY= VAL_2(pipe))
+
+#define _PLANE_KEYMSK_1_B=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x71198
+#define _PLANE_KEYMSK_2_B=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x71298
+#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK= _1_B)
+#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK= _2_B)
+#define PLANE_KEYMSK(pipe, plane)=C2=A0 =C2=A0 =C2=A0 \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEY= MSK_2(pipe))
+
+#define _PLANE_KEYMAX_1_B=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x711a0
+#define _PLANE_KEYMAX_2_B=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x712a0
+#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX= _1_B)
+#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX= _2_B)
+#define PLANE_KEYMAX(pipe, plane)=C2=A0 =C2=A0 =C2=A0 \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEY= MAX_2(pipe))
+
=C2=A0/* VBIOS regs */
=C2=A0#define VGACNTRL=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A00x71400
=C2=A0# define VGA_DISP_DISABLE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 31)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/int= el_sprite.c
index 07a74ef..57e7190 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -139,6 +139,184 @@ static void intel_update_primary_plane(struct intel_c= rtc *crtc)
=C2=A0}

=C2=A0static void
+skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 struct drm_framebu= ffer *fb,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 struct drm_i915_ge= m_object *obj, int crtc_x, int crtc_y,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 unsigned int crtc_= w, unsigned int crtc_h,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint32_t x, uint32= _t y,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 uint32_t src_w, ui= nt32_t src_h)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct drm_device *dev =3D drm_plane->dev; +=C2=A0 =C2=A0 =C2=A0 =C2=A0struct drm_i915_private *dev_priv =3D dev->d= ev_private;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct intel_plane *intel_plane =3D to_intel_pl= ane(drm_plane);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0const int pipe =3D intel_plane->pipe;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0const int plane =3D intel_plane->plane + 1;<= /blockquote>

A comment above to remind skl doesn't h= ave the primary would be good.=C2=A0
=C2=A0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u32 plane_ctl, stride;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0int pixel_size =3D drm_format_plane_cpp(fb->= pixel_format, 0);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl =3D I915_READ(PLANE_CTL(pipe, plane))= ;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Mask out pixel format bits in case we change= it */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl &=3D ~PLANE_CTL_FORMAT_MASK;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl &=3D ~PLANE_CTL_ORDER_RGBX;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl &=3D ~PLANE_CTL_YUV422_ORDER_MASK= ;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl &=3D ~PLANE_CTL_TILED_MASK;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl &=3D ~PLANE_CTL_ALPHA_MASK;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Trickle feed has to be enabled */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl &=3D ~PLANE_CTL_TRICKLE_FEED_DISA= BLE;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (fb->pixel_format) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case DRM_FORMAT_RGB565:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl |=3D PLAN= E_CTL_FORMAT_RGB_565;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case DRM_FORMAT_XBGR8888:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl |=3D PLAN= E_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case DRM_FORMAT_XRGB8888:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl |=3D PLAN= E_CTL_FORMAT_XRGB_8888;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0/*
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 * XXX: For ARBG/ABGR formats we default to exp= ecting scanout buffers
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 * to be already pre-multiplied. We need to add= a knob (or a different
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 * DRM_FORMAT) for user-space to configure that= .
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case DRM_FORMAT_ABGR8888:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl |=3D PLAN= E_CTL_FORMAT_XRGB_8888 |
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 PLANE_CTL_ORDER_RGBX |
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case DRM_FORMAT_ARGB8888:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl |=3D PLAN= E_CTL_FORMAT_XRGB_8888 |
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case DRM_FORMAT_YUYV:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl |=3D PLAN= E_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case DRM_FORMAT_YVYU:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl |=3D PLAN= E_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case DRM_FORMAT_UYVY:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl |=3D PLAN= E_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case DRM_FORMAT_VYUY:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl |=3D PLAN= E_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0BUG();
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (obj->tiling_mode) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case I915_TILING_NONE:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0stride =3D fb->p= itches[0] >> 6;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case I915_TILING_X:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl |=3D PLAN= E_CTL_TILED_X;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0stride =3D fb->p= itches[0] >> 9;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0BUG();
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl |=3D PLANE_CTL_ENABLE;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl |=3D PLANE_CTL_PIPE_CSC_ENABLE;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0intel_update_sprite_watermarks(drm_plane, crtc,= src_w, src_h,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 pixel_size, tru= e,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 src_w !=3D crtc= _w || src_h !=3D crtc_h);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Sizes are 0 based */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0src_w--;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0src_h--;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0crtc_w--;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0crtc_h--;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0I915_WRITE(PLANE_OFFSET(pipe, plane), (y <&l= t; 16) | x);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0I915_WRITE(PLANE_STRIDE(pipe, plane), stride);<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0I915_WRITE(PLANE_POS(pipe, plane), (crtc_y <= < 16) | crtc_x);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0I915_WRITE(PLANE_SIZE(pipe, plane), (crtc_h <= ;< 16) | crtc_w);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0I915_WRITE(PLANE_SURF(pipe, plane), i915_gem_ob= j_ggtt_offset(obj));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0POSTING_READ(PLANE_SURF(pipe, plane));
+}
+
+static void
+skl_disable_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct drm_device *dev =3D drm_plane->dev; +=C2=A0 =C2=A0 =C2=A0 =C2=A0struct drm_i915_private *dev_priv =3D dev->d= ev_private;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct intel_plane *intel_plane =3D to_intel_pl= ane(drm_plane);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0const int pipe =3D intel_plane->pipe;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0const int plane =3D intel_plane->plane + 1;<= br> +
+=C2=A0 =C2=A0 =C2=A0 =C2=A0I915_WRITE(PLANE_CTL(pipe, plane),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 I915_READ(P= LANE_CTL(pipe, plane)) & ~PLANE_CTL_ENABLE);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Activate double buffered register update */<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0I915_WRITE(PLANE_CTL(pipe, plane), 0);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0POSTING_READ(PLANE_CTL(pipe, plane));
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0intel_update_sprite_watermarks(drm_plane, crtc,= 0, 0, 0, false, false);
+}
+
+static int
+skl_update_colorkey(struct drm_plane *drm_plane,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struc= t drm_intel_sprite_colorkey *key)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct drm_device *dev =3D drm_plane->dev; +=C2=A0 =C2=A0 =C2=A0 =C2=A0struct drm_i915_private *dev_priv =3D dev->d= ev_private;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct intel_plane *intel_plane =3D to_intel_pl= ane(drm_plane);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0const int pipe =3D intel_plane->pipe;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0const int plane =3D intel_plane->plane;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u32 plane_ctl;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0I915_WRITE(PLANE_KEYVAL(pipe, plane), key->m= in_value);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0I915_WRITE(PLANE_KEYMAX(pipe, plane), key->m= ax_value);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0I915_WRITE(PLANE_KEYMSK(pipe, plane), key->c= hannel_mask);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl =3D I915_READ(PLANE_CTL(pipe, plane))= ;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl &=3D ~PLANE_CTL_KEY_ENABLE_MASK;<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0if (key->flags & I915_SET_COLORKEY_DESTI= NATION)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl |=3D PLAN= E_CTL_KEY_ENABLE_DESTINATION;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0else if (key->flags & I915_SET_COLORKEY_= SOURCE)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl |=3D PLAN= E_CTL_KEY_ENABLE_SOURCE;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);<= br> +
+=C2=A0 =C2=A0 =C2=A0 =C2=A0POSTING_READ(PLANE_CTL(pipe, plane));
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;
+}
+
+static void
+skl_get_colorkey(struct drm_plane *drm_plane,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 struct drm_intel_s= prite_colorkey *key)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct drm_device *dev =3D drm_plane->dev; +=C2=A0 =C2=A0 =C2=A0 =C2=A0struct drm_i915_private *dev_priv =3D dev->d= ev_private;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0struct intel_plane *intel_plane =3D to_intel_pl= ane(drm_plane);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0const int pipe =3D intel_plane->pipe;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0const int plane =3D intel_plane->plane;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0u32 plane_ctl;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0key->min_value =3D I915_READ(PLANE_KEYVAL(pi= pe, plane));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0key->max_value =3D I915_READ(PLANE_KEYMAX(pi= pe, plane));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0key->channel_mask =3D I915_READ(PLANE_KEYMSK= (pipe, plane));
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0plane_ctl =3D I915_READ(PLANE_CTL(pipe, plane))= ;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0switch (plane_ctl & PLANE_CTL_KEY_ENABLE_MA= SK) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case PLANE_CTL_KEY_ENABLE_DESTINATION:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0key->flags =3D I= 915_SET_COLORKEY_DESTINATION;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case PLANE_CTL_KEY_ENABLE_SOURCE:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0key->flags =3D I= 915_SET_COLORKEY_SOURCE;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0default:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0key->flags =3D I= 915_SET_COLORKEY_NONE;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0}
+}
+
+static void
=C2=A0vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct drm_fr= amebuffer *fb,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct drm_i9= 15_gem_object *obj, int crtc_x, int crtc_y,
@@ -1305,6 +1483,18 @@ static uint32_t vlv_plane_formats[] =3D {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 DRM_FORMAT_VYUY,
=C2=A0};

+static uint32_t skl_plane_formats[] =3D {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0DRM_FORMAT_RGB565,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0DRM_FORMAT_ABGR8888,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0DRM_FORMAT_ARGB8888,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0DRM_FORMAT_XBGR8888,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0DRM_FORMAT_XRGB8888,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0DRM_FORMAT_YUYV,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0DRM_FORMAT_YVYU,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0DRM_FORMAT_UYVY,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0DRM_FORMAT_VYUY,
+};
+
=C2=A0int
=C2=A0intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) =C2=A0{
@@ -1368,7 +1558,21 @@ intel_plane_init(struct drm_device *dev, enum pipe p= ipe, int plane)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 num_plane_formats =3D ARRAY_SIZE(snb_plane_formats);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 break;
-
+=C2=A0 =C2=A0 =C2=A0 =C2=A0case 9:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/*
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 * FIXME: Skylake p= lanes can be scaled (with some restrictions),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 * but this is for = another time.
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0intel_plane->can= _scale =3D false;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0intel_plane->max= _downscale =3D 1;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0intel_plane->upd= ate_plane =3D skl_update_plane;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0intel_plane->dis= able_plane =3D skl_disable_plane;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0intel_plane->upd= ate_colorkey =3D skl_update_colorkey;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0intel_plane->get= _colorkey =3D skl_get_colorkey;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0plane_formats =3D s= kl_plane_formats;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0num_plane_formats = =3D ARRAY_SIZE(skl_plane_formats);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 default:
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 kfree(intel_plane);=
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return -ENODEV;
--
1.8.3.1

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Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br<= /div>
=C2=A0
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