From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rodrigo Vivi Subject: Re: [PATCH] drm/i915: Update PSR on resume. Date: Mon, 11 Aug 2014 09:57:12 -0700 Message-ID: References: <20140610152457.GY5821@phenom.ffwll.local> <1407518374-7886-1-git-send-email-rodrigo.vivi@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0930650781==" Return-path: Received: from mail-wi0-f172.google.com (mail-wi0-f172.google.com [209.85.212.172]) by gabe.freedesktop.org (Postfix) with ESMTP id CA75A6E28A for ; Mon, 11 Aug 2014 09:57:13 -0700 (PDT) Received: by mail-wi0-f172.google.com with SMTP id n3so4581667wiv.11 for ; Mon, 11 Aug 2014 09:57:12 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter Cc: intel-gfx , Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org --===============0930650781== Content-Type: multipart/alternative; boundary=047d7ba97fda47e6c105005d7289 --047d7ba97fda47e6c105005d7289 Content-Type: text/plain; charset=UTF-8 Well, this fix the issue Linus faced. Actually the issue I was aware of and trying to fix with this patch for a long time was reported by chromeos guys saying the psr wasn't propperly working after suspend/resume. They got the screen back but never got psr back again. The original patch fix suspend/resume issues with psr and I decided to keep the same and subject for reference of what the problem this fixes and what was the patch history, but changed the place for the full setup to crtc_enable per your recommendation. Thanks, Rodrigo. On Sat, Aug 9, 2014 at 12:40 AM, Daniel Vetter wrote: > On Fri, Aug 8, 2014 at 7:19 PM, Rodrigo Vivi > wrote: > > From: Rodrigo Vivi > > > > Some registers set during setup might not be persistent after > suspend/resume. > > This was causing bugs for some people that was unable to get PSR entry > state > > after resume cycle. > > > > v2: Adding some comments and better commit message explaining why this > is needed. > > v3: Getting back old setup_done variable and move from resume to > crtc_enable > > as Daniel requested. > > > > Cc: Daniel Vetter > > Signed-off-by: Rodrigo Vivi > > I'm confused ... whats the use of this? Afaict that's exactly what the > code currently does. > -Daniel > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch > -- Rodrigo Vivi Blog: http://blog.vivi.eng.br --047d7ba97fda47e6c105005d7289 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Well, this fix the issue Linus faced.

A= ctually the issue I was aware of and trying to fix with this patch for a lo= ng time was reported by chromeos guys saying the psr wasn't propperly w= orking after suspend/resume. They got the screen back but never got psr bac= k again.

The original patch fix suspend/resume issues with psr a= nd I decided to keep the same and subject for reference of what the problem= this fixes and what was the patch history, but changed the place for the f= ull setup to crtc_enable per your recommendation.

Thanks,
Rodrigo.



On Sat, A= ug 9, 2014 at 12:40 AM, Daniel Vetter <daniel.vetter@ffwll.ch>= wrote:
On Fri, Aug 8, 2014 at 7:19 = PM, Rodrigo Vivi <rodrigo.vivi= @intel.com> wrote:
> From: Rodrigo Vivi <rodri= go.vivi@gmail.com>
>
> Some registers set during setup might not be persistent after suspend/= resume.
> This was causing bugs for some people that was unable to get PSR entry= state
> after resume cycle.
>
> v2: Adding some comments and better commit message explaining why this= is needed.
> v3: Getting back old setup_done variable and move from resume to crtc_= enable
> =C2=A0 =C2=A0 as Daniel requested.
>
> Cc: Daniel Vetter <daniel= .vetter@ffwll.ch>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

I'm confused ... whats the use of this? Afaict that's exactly= what the
code currently does.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48=C2=A0- http://blog.ffwll.ch



--
=
Rodrigo Vivi
=C2=A0
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