From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rodrigo Vivi Subject: Re: [PATCH 1/4] drm/i915: Increase PSR Idle Frame to 2. Date: Thu, 4 Sep 2014 11:18:12 -0700 Message-ID: References: <1409798999-1809-1-git-send-email-rodrigo.vivi@intel.com> <20140904075516.GB4193@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1497292044==" Return-path: Received: from mail-wg0-f49.google.com (mail-wg0-f49.google.com [74.125.82.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 38AEE6E1F1 for ; Thu, 4 Sep 2014 11:18:13 -0700 (PDT) Received: by mail-wg0-f49.google.com with SMTP id y10so10504297wgg.8 for ; Thu, 04 Sep 2014 11:18:12 -0700 (PDT) In-Reply-To: <20140904075516.GB4193@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= Cc: intel-gfx , Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org --===============1497292044== Content-Type: multipart/alternative; boundary=e89a8f8391bf1b6dd3050241601e --e89a8f8391bf1b6dd3050241601e Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Thu, Sep 4, 2014 at 12:55 AM, Ville Syrj=C3=A4l=C3=A4 < ville.syrjala@linux.intel.com> wrote: > On Wed, Sep 03, 2014 at 10:49:56PM -0400, Rodrigo Vivi wrote: > > With Software tracking we are going to PSR sooner than we should and > staying > > with blank screens in many cases. > > > > Using 2 identical frames to detect idleness is safier. > > This idle frame detection still depends of FBC right? > not sure. and fbc is disabled anyway here on my tests. > I believe if we want to go for full sw tracking on HSW/BDW we need to > use the debug register to force PSR entry/exit. > I tried this many times in different ways but never had success > > > > > Discovered and validated with refactored igt/kms_sink_psr_crc. > > > > Signed-off-by: Rodrigo Vivi > > --- > > drivers/gpu/drm/i915/intel_dp.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > b/drivers/gpu/drm/i915/intel_dp.c > > index f79473b..a796831 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -1813,7 +1813,7 @@ static void intel_edp_psr_enable_source(struct > intel_dp *intel_dp) > > struct drm_device *dev =3D dig_port->base.base.dev; > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > uint32_t max_sleep_time =3D 0x1f; > > - uint32_t idle_frames =3D 1; > > + uint32_t idle_frames =3D 2; > > uint32_t val =3D 0x0; > > const uint32_t link_entry_time =3D > EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; > > bool only_standby =3D false; > > -- > > 1.9.3 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrj=C3=A4l=C3=A4 > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > --=20 Rodrigo Vivi Blog: http://blog.vivi.eng.br --e89a8f8391bf1b6dd3050241601e Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable



On Thu, Sep 4, 2014 at 12:55 AM, Ville Syrj=C3=A4l=C3=A4 <ville.syrjala@linux.intel.com> wrote:
On Wed, Sep 03, 2014 at 10:49:56PM -0400, = Rodrigo Vivi wrote:
> With Software tracking we are going to PSR sooner than we should and s= taying
> with blank screens in many cases.
>
> Using 2 identical frames to detect idleness is safier.

This idle frame detection still depends of FBC right?
=C2=A0
not sure. and fbc is disabled anyway here on my tests.
=C2=A0
I believe if we want to go for full sw tracking on HSW/BDW we need to
use the debug register to force PSR entry/exit.


<= div>I tried thi= s many times in different ways but never had success=C2=A0
=C2=A0

>
> Discovered and validated with refactored igt/kms_sink_psr_crc.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>=C2=A0 drivers/gpu/drm/i915/intel_dp.c | 2 +-
>=C2=A0 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/in= tel_dp.c
> index f79473b..a796831 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1813,7 +1813,7 @@ static void intel_edp_psr_enable_source(struct i= ntel_dp *intel_dp)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0struct drm_device *dev =3D dig_port->base= .base.dev;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0struct drm_i915_private *dev_priv =3D dev-&g= t;dev_private;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t max_sleep_time =3D 0x1f;
> -=C2=A0 =C2=A0 =C2=A0uint32_t idle_frames =3D 1;
> +=C2=A0 =C2=A0 =C2=A0uint32_t idle_frames =3D 2;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t val =3D 0x0;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0const uint32_t link_entry_time =3D EDP_PSR_M= IN_LINK_ENTRY_TIME_8_LINES;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0bool only_standby =3D false;
> --
> 1.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.fre= edesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx=

--
Ville Syrj=C3=A4l=C3=A4
Intel OTC
___________________________= ____________________
Intel-gfx mailing list
Intel-gfx@lists.freedesk= top.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx



--
=
Rodrigo Vivi
=C2=A0
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