On Thu, Sep 04, 2014 at 11:29:16AM +0200, Daniel Vetter wrote:
> On Thu, Sep 04, 2014 at 10:55:16AM +0300, Ville Syrjälä wrote:
> > On Wed, Sep 03, 2014 at 10:49:56PM -0400, Rodrigo Vivi wrote:
> > > With Software tracking we are going to PSR sooner than we should and staying
> > > with blank screens in many cases.
> > >
> > > Using 2 identical frames to detect idleness is safier.
> >
> > This idle frame detection still depends of FBC right?
> >
> > I believe if we want to go for full sw tracking on HSW/BDW we need to
> > use the debug register to force PSR entry/exit.
>
> Currently the sw tracking relies upon 1 additional full upload happening
> after the flush, which hopefully should magically happen if we have just 1
> idle frame.
>
> If we'd completely switch to sw tracking we'd need to set up a vblank
> worker to disable psr after the next vblank, which would comlicate the
> code I think.

vlv/chv have no hw tracking so if the current sw tracking can't deal
with that then it would seem to need more work.

> -Daniel
>
> >
> > >
> > > Discovered and validated with refactored igt/kms_sink_psr_crc.
> > >
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index f79473b..a796831 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -1813,7 +1813,7 @@ static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
> > >   struct drm_device *dev = dig_port->base.base.dev;
> > >   struct drm_i915_private *dev_priv = dev->dev_private;
> > >   uint32_t max_sleep_time = 0x1f;
> > > - uint32_t idle_frames = 1;
> > > + uint32_t idle_frames = 2;
> > >   uint32_t val = 0x0;
> > >   const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> > >   bool only_standby = false;
> > > --
> > > 1.9.3
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrjälä
> > Intel OTC
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

--
Ville Syrjälä
Intel OTC
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