From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rodrigo Vivi Subject: Re: [PATCH 1/4] drm/i915: Increase PSR Idle Frame to 2. Date: Thu, 4 Sep 2014 11:22:23 -0700 Message-ID: References: <1409798999-1809-1-git-send-email-rodrigo.vivi@intel.com> <20140904075516.GB4193@intel.com> <20140904092916.GF15520@phenom.ffwll.local> <20140904100427.GD4193@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0384781303==" Return-path: Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 8BA486E671 for ; Thu, 4 Sep 2014 11:22:26 -0700 (PDT) Received: by mail-we0-f177.google.com with SMTP id u56so10477642wes.8 for ; Thu, 04 Sep 2014 11:22:23 -0700 (PDT) In-Reply-To: <20140904100427.GD4193@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= Cc: intel-gfx , Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org --===============0384781303== Content-Type: multipart/alternative; boundary=047d7b6225ac1c8db40502416fac --047d7b6225ac1c8db40502416fac Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Thu, Sep 4, 2014 at 3:04 AM, Ville Syrj=C3=A4l=C3=A4 wrote: > On Thu, Sep 04, 2014 at 11:29:16AM +0200, Daniel Vetter wrote: > > On Thu, Sep 04, 2014 at 10:55:16AM +0300, Ville Syrj=C3=A4l=C3=A4 wrote= : > > > On Wed, Sep 03, 2014 at 10:49:56PM -0400, Rodrigo Vivi wrote: > > > > With Software tracking we are going to PSR sooner than we should an= d > staying > > > > with blank screens in many cases. > > > > > > > > Using 2 identical frames to detect idleness is safier. > > > > > > This idle frame detection still depends of FBC right? > > > > > > I believe if we want to go for full sw tracking on HSW/BDW we need to > > > use the debug register to force PSR entry/exit. > > > > Currently the sw tracking relies upon 1 additional full upload happenin= g > > after the flush, which hopefully should magically happen if we have jus= t > 1 > > idle frame. > > > > If we'd completely switch to sw tracking we'd need to set up a vblank > > worker to disable psr after the next vblank, which would comlicate the > > code I think. > > vlv/chv have no hw tracking so if the current sw tracking can't deal > with that then it would seem to need more work. > the sw tracking on vlv works well. The only issue is that the force depends on a dpms_on call and I was facing strange hangs when going blank. But overal it is possible. > > > -Daniel > > > > > > > > > > > > > Discovered and validated with refactored igt/kms_sink_psr_crc. > > > > > > > > Signed-off-by: Rodrigo Vivi > > > > --- > > > > drivers/gpu/drm/i915/intel_dp.c | 2 +- > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > b/drivers/gpu/drm/i915/intel_dp.c > > > > index f79473b..a796831 100644 > > > > --- a/drivers/gpu/drm/i915/intel_dp.c > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > > > @@ -1813,7 +1813,7 @@ static void intel_edp_psr_enable_source(struc= t > intel_dp *intel_dp) > > > > struct drm_device *dev =3D dig_port->base.base.dev; > > > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > > > uint32_t max_sleep_time =3D 0x1f; > > > > - uint32_t idle_frames =3D 1; > > > > + uint32_t idle_frames =3D 2; > > > > uint32_t val =3D 0x0; > > > > const uint32_t link_entry_time =3D > EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; > > > > bool only_standby =3D false; > > > > -- > > > > 1.9.3 > > > > > > > > _______________________________________________ > > > > Intel-gfx mailing list > > > > Intel-gfx@lists.freedesktop.org > > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > -- > > > Ville Syrj=C3=A4l=C3=A4 > > > Intel OTC > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Daniel Vetter > > Software Engineer, Intel Corporation > > +41 (0) 79 365 57 48 - http://blog.ffwll.ch > > -- > Ville Syrj=C3=A4l=C3=A4 > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > --=20 Rodrigo Vivi Blog: http://blog.vivi.eng.br --047d7b6225ac1c8db40502416fac Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable



On Thu, Sep 4, 2014 at 3:04 AM, Ville Syrj=C3=A4l=C3=A4 <ville.syrjala@linux.intel.com> wrote:
On Thu, Sep 04, 2014 at 11:2= 9:16AM +0200, Daniel Vetter wrote:
> On Thu, Sep 04, 2014 at 10:55:16AM +0300, Ville Syrj=C3=A4l=C3=A4 wrot= e:
> > On Wed, Sep 03, 2014 at 10:49:56PM -0400, Rodrigo Vivi wrote:
> > > With Software tracking we are going to PSR sooner than we sh= ould and staying
> > > with blank screens in many cases.
> > >
> > > Using 2 identical frames to detect idleness is safier.
> >
> > This idle frame detection still depends of FBC right?
> >
> > I believe if we want to go for full sw tracking on HSW/BDW we nee= d to
> > use the debug register to force PSR entry/exit.
>
> Currently the sw tracking relies upon 1 additional full upload happeni= ng
> after the flush, which hopefully should magically happen if we have ju= st 1
> idle frame.
>
> If we'd completely switch to sw tracking we'd need to set up a= vblank
> worker to disable psr after the next vblank, which would comlicate the=
> code I think.

vlv/chv have no hw tracking so if the current sw tracking can't d= eal
with that then it would seem to need more work.

the sw tracking on vlv works well.
The only issue is tha= t the force depends on a dpms_on call and I was facing strange hangs when g= oing blank.
But overal it is possible.
=C2=A0

> -Daniel
>
> >
> > >
> > > Discovered and validated with refactored igt/kms_sink_psr_cr= c.
> > >
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >=C2=A0 drivers/gpu/drm/i915/intel_dp.c | 2 +-
> > >=C2=A0 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/d= rm/i915/intel_dp.c
> > > index f79473b..a796831 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -1813,7 +1813,7 @@ static void intel_edp_psr_enable_sourc= e(struct intel_dp *intel_dp)
> > >=C2=A0 =C2=A0struct drm_device *dev =3D dig_port->base.bas= e.dev;
> > >=C2=A0 =C2=A0struct drm_i915_private *dev_priv =3D dev->de= v_private;
> > >=C2=A0 =C2=A0uint32_t max_sleep_time =3D 0x1f;
> > > - uint32_t idle_frames =3D 1;
> > > + uint32_t idle_frames =3D 2;
> > >=C2=A0 =C2=A0uint32_t val =3D 0x0;
> > >=C2=A0 =C2=A0const uint32_t link_entry_time =3D EDP_PSR_MIN_L= INK_ENTRY_TIME_8_LINES;
> > >=C2=A0 =C2=A0bool only_standby =3D false;
> > > --
> > > 1.9.3
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx= @lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/int= el-gfx
> >
> > --
> > Ville Syrj=C3=A4l=C3=A4
> > Intel OTC
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@list= s.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gf= x
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

--
Ville Syrj=C3=A4l=C3=A4
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesk= top.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx



--
=
Rodrigo Vivi
=C2=A0
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