From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rodrigo Vivi Subject: Re: [PATCH 1/4] drm/i915: Increase PSR Idle Frame to 2. Date: Thu, 4 Sep 2014 11:26:34 -0700 Message-ID: References: <1409798999-1809-1-git-send-email-rodrigo.vivi@intel.com> <20140904075516.GB4193@intel.com> <20140904092916.GF15520@phenom.ffwll.local> <20140904100427.GD4193@intel.com> <20140904101819.GE4193@intel.com> <20140904110406.GH15520@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0318396130==" Return-path: Received: from mail-wi0-f179.google.com (mail-wi0-f179.google.com [209.85.212.179]) by gabe.freedesktop.org (Postfix) with ESMTP id 4373A6E674 for ; Thu, 4 Sep 2014 11:26:35 -0700 (PDT) Received: by mail-wi0-f179.google.com with SMTP id q5so1670176wiv.12 for ; Thu, 04 Sep 2014 11:26:34 -0700 (PDT) In-Reply-To: <20140904110406.GH15520@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter Cc: intel-gfx , Rodrigo Vivi List-Id: intel-gfx@lists.freedesktop.org --===============0318396130== Content-Type: multipart/alternative; boundary=047d7bb04dd20b7c420502417e7e --047d7bb04dd20b7c420502417e7e Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Thu, Sep 4, 2014 at 4:04 AM, Daniel Vetter wrote: > On Thu, Sep 04, 2014 at 01:18:19PM +0300, Ville Syrj=C3=A4l=C3=A4 wrote: > > On Thu, Sep 04, 2014 at 01:04:27PM +0300, Ville Syrj=C3=A4l=C3=A4 wrote= : > > > On Thu, Sep 04, 2014 at 11:29:16AM +0200, Daniel Vetter wrote: > > > > On Thu, Sep 04, 2014 at 10:55:16AM +0300, Ville Syrj=C3=A4l=C3=A4 w= rote: > > > > > On Wed, Sep 03, 2014 at 10:49:56PM -0400, Rodrigo Vivi wrote: > > > > > > With Software tracking we are going to PSR sooner than we shoul= d > and staying > > > > > > with blank screens in many cases. > > > > > > > > > > > > Using 2 identical frames to detect idleness is safier. > > > > > > > > > > This idle frame detection still depends of FBC right? > > > > > > > > > > I believe if we want to go for full sw tracking on HSW/BDW we nee= d > to > > > > > use the debug register to force PSR entry/exit. > > > > > > > > Currently the sw tracking relies upon 1 additional full upload > happening > > > > after the flush, which hopefully should magically happen if we have > just 1 > > > > idle frame. > > > > > > > > If we'd completely switch to sw tracking we'd need to set up a vbla= nk > > > > worker to disable psr after the next vblank, which would comlicate > the > > > > code I think. > > > > > > vlv/chv have no hw tracking so if the current sw tracking can't deal > > > with that then it would seem to need more work. > > > > Hmm. Actually they seem to have a hw timer mode where we can program th= e > > number of idle frames. I think idle here means "since the last plane > > register frobbing" as there's no real modification tracking ala. FBC. > > So maybe it can work roughly the same way as HSW in that regard. > > Essentially the primitive the current code needs (modulo bugs, which seem > to still be) is to "upload one more full frame, then enter psr". If a lot > of platforms can't do that themselves I guess we could wrap some helpers > for them. > > But if there's some real sw tracking bug still, and Rodrigo's patch looks > like this is still the case, we need to fix that ofc. > Yeah, I agree. But I'm afraid I didn't fully get your idea. What do you have in mind? > -Daniel > > > > > > > > > > -Daniel > > > > > > > > > > > > > > > > > > > > > Discovered and validated with refactored igt/kms_sink_psr_crc. > > > > > > > > > > > > Signed-off-by: Rodrigo Vivi > > > > > > --- > > > > > > drivers/gpu/drm/i915/intel_dp.c | 2 +- > > > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > b/drivers/gpu/drm/i915/intel_dp.c > > > > > > index f79473b..a796831 100644 > > > > > > --- a/drivers/gpu/drm/i915/intel_dp.c > > > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > > > > > @@ -1813,7 +1813,7 @@ static void > intel_edp_psr_enable_source(struct intel_dp *intel_dp) > > > > > > struct drm_device *dev =3D dig_port->base.base.dev; > > > > > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > > > > > uint32_t max_sleep_time =3D 0x1f; > > > > > > - uint32_t idle_frames =3D 1; > > > > > > + uint32_t idle_frames =3D 2; > > > > > > uint32_t val =3D 0x0; > > > > > > const uint32_t link_entry_time =3D > EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; > > > > > > bool only_standby =3D false; > > > > > > -- > > > > > > 1.9.3 > > > > > > > > > > > > _______________________________________________ > > > > > > Intel-gfx mailing list > > > > > > Intel-gfx@lists.freedesktop.org > > > > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > > > > > -- > > > > > Ville Syrj=C3=A4l=C3=A4 > > > > > Intel OTC > > > > > _______________________________________________ > > > > > Intel-gfx mailing list > > > > > Intel-gfx@lists.freedesktop.org > > > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > > > -- > > > > Daniel Vetter > > > > Software Engineer, Intel Corporation > > > > +41 (0) 79 365 57 48 - http://blog.ffwll.ch > > > > > > -- > > > Ville Syrj=C3=A4l=C3=A4 > > > Intel OTC > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Ville Syrj=C3=A4l=C3=A4 > > Intel OTC > > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > --=20 Rodrigo Vivi Blog: http://blog.vivi.eng.br --047d7bb04dd20b7c420502417e7e Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable



On Thu, Sep 4, 2014 at 4:04 AM, Daniel Vetter <= ;daniel@ffwll.ch&g= t; wrote:
On Thu, Sep 04, 2014 at 01:1= 8:19PM +0300, Ville Syrj=C3=A4l=C3=A4 wrote:
> On Thu, Sep 04, 2014 at 01:04:27PM +0300, Ville Syrj=C3=A4l=C3=A4 wrot= e:
> > On Thu, Sep 04, 2014 at 11:29:16AM +0200, Daniel Vetter wrote: > > > On Thu, Sep 04, 2014 at 10:55:16AM +0300, Ville Syrj=C3=A4l= =C3=A4 wrote:
> > > > On Wed, Sep 03, 2014 at 10:49:56PM -0400, Rodrigo Vivi = wrote:
> > > > > With Software tracking we are going to PSR sooner = than we should and staying
> > > > > with blank screens in many cases.
> > > > >
> > > > > Using 2 identical frames to detect idleness is saf= ier.
> > > >
> > > > This idle frame detection still depends of FBC right? > > > >
> > > > I believe if we want to go for full sw tracking on HSW/= BDW we need to
> > > > use the debug register to force PSR entry/exit.
> > >
> > > Currently the sw tracking relies upon 1 additional full uplo= ad happening
> > > after the flush, which hopefully should magically happen if = we have just 1
> > > idle frame.
> > >
> > > If we'd completely switch to sw tracking we'd need t= o set up a vblank
> > > worker to disable psr after the next vblank, which would com= licate the
> > > code I think.
> >
> > vlv/chv have no hw tracking so if the current sw tracking can'= ;t deal
> > with that then it would seem to need more work.
>
> Hmm. Actually they seem to have a hw timer mode where we can program t= he
> number of idle frames. I think idle here means "since the last pl= ane
> register frobbing" as there's no real modification tracking a= la. FBC.
> So maybe it can work roughly the same way as HSW in that regard.

Essentially the primitive the current code needs (modulo bugs, which = seem
to still be) is to "upload one more full frame, then enter psr". = If a lot
of platforms can't do that themselves I guess we could wrap some helper= s
for them.

But if there's some real sw tracking bug still, and Rodrigo's patch= looks
like this is still the case, we need to fix that ofc.
=
Yeah, I agree. But I'm afraid I didn't fully get you= r idea. What do you have in mind?

=C2=A0
-Daniel

>
> >
> > > -Daniel
> > >
> > > >
> > > > >
> > > > > Discovered and validated with refactored igt/kms_s= ink_psr_crc.
> > > > >
> > > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > > > ---
> > > > >=C2=A0 drivers/gpu/drm/i915/intel_dp.c | 2 +-
> > > > >=C2=A0 1 file changed, 1 insertion(+), 1 deletion(-= )
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/dri= vers/gpu/drm/i915/intel_dp.c
> > > > > index f79473b..a796831 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > > @@ -1813,7 +1813,7 @@ static void intel_edp_psr_en= able_source(struct intel_dp *intel_dp)
> > > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0struct drm_device *dev = =3D dig_port->base.base.dev;
> > > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0struct drm_i915_private = *dev_priv =3D dev->dev_private;
> > > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t max_sleep_time = =3D 0x1f;
> > > > > -=C2=A0 =C2=A0 =C2=A0uint32_t idle_frames =3D 1; > > > > > +=C2=A0 =C2=A0 =C2=A0uint32_t idle_frames =3D 2; > > > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t val =3D 0x0; > > > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0const uint32_t link_entr= y_time =3D EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> > > > >=C2=A0 =C2=A0 =C2=A0 =C2=A0bool only_standby =3D fa= lse;
> > > > > --
> > > > > 1.9.3
> > > > >
> > > > > _______________________________________________ > > > > > Intel-gfx mailing list
> > > > > Intel-gfx@lists.freedesktop.org
> > > > > http://lists.freedesktop.org/mailman/li= stinfo/intel-gfx
> > > >
> > > > --
> > > > Ville Syrj=C3=A4l=C3=A4
> > > > Intel OTC
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Inte= l-gfx@lists.freedesktop.org
> > > > http://lists.freedesktop.org/mailman/listinf= o/intel-gfx
> > >
> > > --
> > > Daniel Vetter
> > > Software Engineer, Intel Corporation
> > > +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> >
> > --
> > Ville Syrj=C3=A4l=C3=A4
> > Intel OTC
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@list= s.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gf= x
>
> --
> Ville Syrj=C3=A4l=C3=A4
> Intel OTC

--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48=C2=A0- http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesk= top.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx



--
=
Rodrigo Vivi
=C2=A0
--047d7bb04dd20b7c420502417e7e-- --===============0318396130== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0318396130==--