From mboxrd@z Thu Jan  1 00:00:00 1970
From: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Subject: Re: [PATCH 15/37] drm/i915: add S PLL control
Date: Mon, 26 Mar 2012 14:41:27 -0300
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* indentation
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> This PLL control can drive DDI ports at desired frequencies for
> DisplayPort and FDI connections.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
> =A0drivers/gpu/drm/i915/i915_reg.h | =A0 =A08 ++++++++
> =A01 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_=
reg.h
> index 9ff9856..e38dafc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3963,4 +3963,12 @@
> =A0#define =A0PIXCLK_GATE_UNGATE =A0 =A0 =A0 =A0 =A0 =A01<<0
> =A0#define =A0PIXCLK_GATE_GATE =A0 =A0 =A0 =A0 =A0 =A0 =A00<<0
>
> +/* SPLL */
> +#define SPLL_CTL =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 0x46020
> +#define =A0SPLL_PLL_ENABLE =A0 =A0 =A0 =A0 =A0 =A0 =A0 (1<<31)
> +#define =A0SPLL_PLL_SCC =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0(1<<28)
> +#define =A0SPLL_PLL_NON_SCC =A0 =A0 =A0 =A0 =A0 =A0 =A0(2<<28)
> +#define =A0SPLL_PLL_FREQ_810MHz =A0(0<<26)
> +#define =A0SPLL_PLL_FREQ_1350MHz (1<<26)
> +
> =A0#endif /* _I915_REG_H_ */
> --
> 1.7.9.2
>
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-- =

Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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