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To: Jason Wang Content-Type: multipart/alternative; boundary="000000000000972b3205a52690a4" Received-SPF: none client-ip=2a00:1450:4864:20::344; envelope-from=andrew@daynix.com; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dmitry.fleytman@gmail.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000972b3205a52690a4 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Yo, I've used OpenSDM_8257x-18.pdf specification. This document was recommended by Intel guys(Also, they referenced to that note). I've made a fast fix and it works. Before that I had a fix for Linux e1000e driver. Overall, the issue was in pending interrupts that can't be cleared by reading ICR in Linux(Windows driver clears by writing to ICR). You can download spec for example from: http://iweb.dl.sourceforge.net/project/e1000/8257x%20Developer%20Manual/Rev= ision%201.8/OpenSDM_8257x-18.pdf On Fri, May 8, 2020 at 5:21 AM Jason Wang wrote: > > On 2020/5/7 =E4=B8=8A=E5=8D=885:26, andrew@daynix.com wrote: > > From: Andrew Melnychenko > > > > Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=3D1707441 > > Added ICR clearing if there is IMS bit - according to the note by > > section 13.3.27 of the 8257X developers manual. > > > > Signed-off-by: Andrew Melnychenko > > --- > > hw/net/e1000e_core.c | 9 +++++++++ > > hw/net/trace-events | 1 + > > 2 files changed, 10 insertions(+) > > > > diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c > > index d5676871fa..302e99ff46 100644 > > --- a/hw/net/e1000e_core.c > > +++ b/hw/net/e1000e_core.c > > @@ -2624,6 +2624,15 @@ e1000e_mac_icr_read(E1000ECore *core, int index) > > e1000e_clear_ims_bits(core, core->mac[IAM]); > > } > > > > + /* > > + * PCIe* GbE Controllers Open Source Software Developer's Manual > > + * 13.3.27 Interrupt Cause Read Register > > + */ > > > Hi Andrew: > > Which version of the manual did you use? I try to use the one mentioned > in e1000e.c which is > > http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-data= sheet.pdf > . > > But I couldn't find chapter 13.3.27. > > Thanks > > > > + if (core->mac[ICR] & core->mac[IMS]) { > > + trace_e1000e_irq_icr_clear_icr_bit_ims(core->mac[ICR], > core->mac[IMS]); > > + core->mac[ICR] =3D 0; > > + } > > + > > trace_e1000e_irq_icr_read_exit(core->mac[ICR]); > > e1000e_update_interrupt_state(core); > > return ret; > > diff --git a/hw/net/trace-events b/hw/net/trace-events > > index e18f883cfd..46e40fcfa9 100644 > > --- a/hw/net/trace-events > > +++ b/hw/net/trace-events > > @@ -237,6 +237,7 @@ e1000e_irq_icr_read_entry(uint32_t icr) "Starting > ICR read. Current ICR: 0x%x" > > e1000e_irq_icr_read_exit(uint32_t icr) "Ending ICR read. Current ICR: > 0x%x" > > e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero > IMS" > > e1000e_irq_icr_clear_iame(void) "Clearing ICR on read due to IAME" > > +e1000e_irq_icr_clear_icr_bit_ims(uint32_t icr, uint32_t ims) "Clearing > ICR on read due corresponding IMS bit: 0x%x & 0x%x" > > e1000e_irq_iam_clear_eiame(uint32_t iam, uint32_t cause) "Clearing IM= S > due to EIAME, IAM: 0x%X, cause: 0x%X" > > e1000e_irq_icr_clear_eiac(uint32_t icr, uint32_t eiac) "Clearing ICR > bits due to EIAC, ICR: 0x%X, EIAC: 0x%X" > > e1000e_irq_ims_clear_set_imc(uint32_t val) "Clearing IMS bits due to > IMC write 0x%x" > > --000000000000972b3205a52690a4 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Yo, I've used OpenSDM_8257x-18.pdf specification.=
This document was recommended by Intel guys(Also, they referenc= ed to that note).
I've made a fast fix and it works. Before t= hat I had a fix for Linux e1000e driver.
Overall, the issue was i= n pending interrupts that can't be cleared by reading ICR in Linux(Wind= ows driver clears by writing to ICR).

Y= ou can download spec for example from:

On Fri, May 8= , 2020 at 5:21 AM Jason Wang <jas= owang@redhat.com> wrote:

On 2020/5/7 =E4=B8=8A=E5=8D=885:26, andrew@daynix.com wrote:
> From: Andrew Melnychenko <andrew@daynix.com>
>
> Buglink: https://bugzilla.redhat.com/show_= bug.cgi?id=3D1707441
> Added ICR clearing if there is IMS bit - according to the note by
> section 13.3.27 of the 8257X developers manual.
>
> Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
> ---
>=C2=A0 =C2=A0hw/net/e1000e_core.c | 9 +++++++++
>=C2=A0 =C2=A0hw/net/trace-events=C2=A0 | 1 +
>=C2=A0 =C2=A02 files changed, 10 insertions(+)
>
> diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c
> index d5676871fa..302e99ff46 100644
> --- a/hw/net/e1000e_core.c
> +++ b/hw/net/e1000e_core.c
> @@ -2624,6 +2624,15 @@ e1000e_mac_icr_read(E1000ECore *core, int index= )
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0e1000e_clear_ims_bits(core, co= re->mac[IAM]);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0}
>=C2=A0 =C2=A0
> +=C2=A0 =C2=A0 /*
> +=C2=A0 =C2=A0 =C2=A0* PCIe* GbE Controllers Open Source Software Deve= loper's Manual
> +=C2=A0 =C2=A0 =C2=A0* 13.3.27 Interrupt Cause Read Register
> +=C2=A0 =C2=A0 =C2=A0*/


Hi Andrew:

Which version of the manual did you use? I try to use the one mentioned in e1000e.c which is
http://www.intel.c= om/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf.

But I couldn't find chapter 13.3.27.

Thanks


> +=C2=A0 =C2=A0 if (core->mac[ICR] & core->mac[IMS]) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 trace_e1000e_irq_icr_clear_icr_bit_ims(co= re->mac[ICR], core->mac[IMS]);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 core->mac[ICR] =3D 0;
> +=C2=A0 =C2=A0 }
> +
>=C2=A0 =C2=A0 =C2=A0 =C2=A0trace_e1000e_irq_icr_read_exit(core->mac[= ICR]);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0e1000e_update_interrupt_state(core);
>=C2=A0 =C2=A0 =C2=A0 =C2=A0return ret;
> diff --git a/hw/net/trace-events b/hw/net/trace-events
> index e18f883cfd..46e40fcfa9 100644
> --- a/hw/net/trace-events
> +++ b/hw/net/trace-events
> @@ -237,6 +237,7 @@ e1000e_irq_icr_read_entry(uint32_t icr) "Star= ting ICR read. Current ICR: 0x%x"
>=C2=A0 =C2=A0e1000e_irq_icr_read_exit(uint32_t icr) "Ending ICR re= ad. Current ICR: 0x%x"
>=C2=A0 =C2=A0e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on = read due to zero IMS"
>=C2=A0 =C2=A0e1000e_irq_icr_clear_iame(void) "Clearing ICR on read= due to IAME"
> +e1000e_irq_icr_clear_icr_bit_ims(uint32_t icr, uint32_t ims) "Cl= earing ICR on read due corresponding IMS bit: 0x%x & 0x%x"
>=C2=A0 =C2=A0e1000e_irq_iam_clear_eiame(uint32_t iam, uint32_t cause) &= quot;Clearing IMS due to EIAME, IAM: 0x%X, cause: 0x%X"
>=C2=A0 =C2=A0e1000e_irq_icr_clear_eiac(uint32_t icr, uint32_t eiac) &qu= ot;Clearing ICR bits due to EIAC, ICR: 0x%X, EIAC: 0x%X"
>=C2=A0 =C2=A0e1000e_irq_ims_clear_set_imc(uint32_t val) "Clearing = IMS bits due to IMC write 0x%x"

--000000000000972b3205a52690a4--