Re: [PATCH RFC v2 riscv/for-next 5/5] riscv: align arch_static_branch function

[Andy Chiu <andy.chiu@sifive.com>]

Hi Guo,

Sorry for sending it again, I forgot to send in plain-text on the last mail.

On Wed, Sep 14, 2022 at 3:06 PM Guo Ren <guoren@kernel.org> wrote:
>
> Is this patch related to this series?
>

This is related to dynamic code patching but not the mechanism of
"function tracer" itself. You are right, I should submit another patch
for that.

> On Tue, Sep 13, 2022 at 5:44 PM Andy Chiu <andy.chiu@sifive.com> wrote:
> >
> > runtime code patching must be done at a naturally aligned address, or we
> > may execute on a partial instruction.
> If it's true, we can't use static branches at all. Have you
> encountered a problem?
>
> If you are right, arm64 ... csky all need the patch.
>
In fact we have run into problems that traced back to static jump
functions during the test. We switched tracer randomly for every 1~5
seconds on a dual-core QEMU setup and found the kernel stucking at a
static branch where it jumps to itself. The reason is that the static
branch was 2-byte but not 4-byte aligned. Then, the kernel would patch
the instruction, either J or NOP, with 2 half-word stores, if the
machine does not have efficient unaligned accesses. Thus, there exists
moments where a half of the NOP mixes with the other half of the J
when transitioning the branch. In our particular case, on a
little-endian machine, the upper half of the NOP was mixed with the
lower part of the J when enabling the branch, resulting in a jump that
jumped to itself. On the other way, it would result in a HINT
instruction when disabling the branch, but it might not be observable.

ARM64 does not have this problem since all instructions must be 4-byte aligned.

Regards,
Andy

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