> MTL has a fixed rawclk of 38400Mhz. Register does not need to be
> +             * MTL always uses a 38.4 MHz rawclk.  The bspec tells us
Mismatch between commit message and comment. Probably
38400Mhz -> 38400kHz
-caz

On Mon, Aug 1, 2022 at 8:29 PM Matt Roper <matthew.d.roper@intel.com> wrote:

> On Wed, Jul 27, 2022 at 06:34:09PM -0700, Radhakrishna Sripada wrote:
> > From: Clint Taylor <clinton.a.taylor@intel.com>
> >
> > MTL has a fixed rawclk of 38400Mhz. Register does not need to be
> > reprogrammed.
> >
> > Bspec: 49304
> >
> > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 86a22c3766e5..390a198b0011 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -3036,6 +3036,13 @@ u32 intel_read_rawclk(struct drm_i915_private
> *dev_priv)
> >
> >       if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> >               freq = dg1_rawclk(dev_priv);
> > +     else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
> > +             /*
> > +             * MTL always uses a 38.4 MHz rawclk.  The bspec tells us
>
> Indentation isn't quite right here.
>
> Patch is also missing your s-o-b.
>
> With those fixed,
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> > +             * "RAWCLK_FREQ defaults to the values for 38.4 and does
> > +             * not need to be programmed."
> > +             */
> > +             freq = 38400;
> >       else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
> >               freq = cnp_rawclk(dev_priv);
> >       else if (HAS_PCH_SPLIT(dev_priv))
> > --
> > 2.25.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
>


-- 
-caz, caz at caztech dot com, 503-six one zero - five six nine nine(m)