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Tue, 12 Apr 2022 03:06:08 -0700 From: Guillaume Ranquet User-Agent: meli 0.7.2 References: <20220327223927.20848-1-granquet@baylibre.com> <20220327223927.20848-4-granquet@baylibre.com> In-Reply-To: MIME-Version: 1.0 Date: Tue, 12 Apr 2022 03:06:08 -0700 Message-ID: Subject: Re: [PATCH v9 03/22] dt-bindings: mediatek,dp_phy: Add Display Port PHY binding To: Rob Herring Cc: airlied@linux.ie, angelogioacchino.delregno@collabora.com, chunfeng.yun@mediatek.com, chunkuang.hu@kernel.org, ck.hu@mediatek.com, daniel@ffwll.ch, deller@gmx.de, jitao.shi@mediatek.com, kishon@ti.com, krzk+dt@kernel.org, maarten.lankhorst@linux.intel.com, matthias.bgg@gmail.com, mripard@kernel.org, p.zabel@pengutronix.de, tzimmermann@suse.de, vkoul@kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, markyacoub@google.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220412_030611_165960_E1EB526E X-CRM114-Status: GOOD ( 11.49 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Wed, 30 Mar 2022 00:58, Rob Herring wrote: >On Mon, Mar 28, 2022 at 12:39:08AM +0200, Guillaume Ranquet wrote: >> This phy controller is embedded in the Display Port Controller on mt8195 SoCs. > >Sorry, but I think you need to go back to what you had in v8. While yes, >the phy and controller IP often do change independently, this h/w looks >pretty interwined. Understood, I'll revert back to v8. > >You could make the controller a phy provider to itself if you wanted. Not sure I follow, could you point me to an example? Thx, Guillaume. > >> >> Signed-off-by: Guillaume Ranquet >> --- >> .../bindings/phy/mediatek,dp-phy.yaml | 43 +++++++++++++++++++ >> 1 file changed, 43 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >> >> diff --git a/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >> new file mode 100644 >> index 000000000000..1f5ffca4e140 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >> @@ -0,0 +1,43 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +# Copyright (c) 2022 MediaTek >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/mediatek,dp-phy.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: MediaTek Display Port PHY >> + >> +maintainers: >> + - CK Hu >> + - Jitao shi >> + >> +description: | >> + Device tree bindings for the Mediatek (embedded) Display Port PHY >> + present on some Mediatek SoCs. >> + >> +properties: >> + compatible: >> + enum: >> + - mediatek,mt8195-dp-phy >> + >> + mediatek,dp-syscon: >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: Phandle to the Display Port node. >> + >> + "#phy-cells": >> + const: 0 >> + >> +required: >> + - compatible >> + - mediatek,dp-syscon >> + - "#phy-cells" >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + dp_phy: dp-phy { >> + compatible = "mediatek,mt8195-dp-phy"; >> + mediatek,dp-syscon = <&dp_tx>; >> + #phy-cells = <0>; >> + }; >> -- >> 2.34.1 >> >> _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BFCF1C433F5 for ; Tue, 12 Apr 2022 10:06:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D703F10E068; Tue, 12 Apr 2022 10:06:10 +0000 (UTC) Received: from mail-oa1-x2b.google.com (mail-oa1-x2b.google.com [IPv6:2001:4860:4864:20::2b]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5892D10E068 for ; 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charset="UTF-8" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-fbdev@vger.kernel.org, devicetree@vger.kernel.org, airlied@linux.ie, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, deller@gmx.de, kishon@ti.com, chunkuang.hu@kernel.org, jitao.shi@mediatek.com, tzimmermann@suse.de, chunfeng.yun@mediatek.com, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, linux-arm-kernel@lists.infradead.org, angelogioacchino.delregno@collabora.com, linux-kernel@vger.kernel.org, vkoul@kernel.org, krzk+dt@kernel.org, markyacoub@google.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, 30 Mar 2022 00:58, Rob Herring wrote: >On Mon, Mar 28, 2022 at 12:39:08AM +0200, Guillaume Ranquet wrote: >> This phy controller is embedded in the Display Port Controller on mt8195 SoCs. > >Sorry, but I think you need to go back to what you had in v8. While yes, >the phy and controller IP often do change independently, this h/w looks >pretty interwined. Understood, I'll revert back to v8. > >You could make the controller a phy provider to itself if you wanted. Not sure I follow, could you point me to an example? Thx, Guillaume. > >> >> Signed-off-by: Guillaume Ranquet >> --- >> .../bindings/phy/mediatek,dp-phy.yaml | 43 +++++++++++++++++++ >> 1 file changed, 43 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >> >> diff --git a/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >> new file mode 100644 >> index 000000000000..1f5ffca4e140 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >> @@ -0,0 +1,43 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +# Copyright (c) 2022 MediaTek >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/mediatek,dp-phy.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: MediaTek Display Port PHY >> + >> +maintainers: >> + - CK Hu >> + - Jitao shi >> + >> +description: | >> + Device tree bindings for the Mediatek (embedded) Display Port PHY >> + present on some Mediatek SoCs. >> + >> +properties: >> + compatible: >> + enum: >> + - mediatek,mt8195-dp-phy >> + >> + mediatek,dp-syscon: >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: Phandle to the Display Port node. >> + >> + "#phy-cells": >> + const: 0 >> + >> +required: >> + - compatible >> + - mediatek,dp-syscon >> + - "#phy-cells" >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + dp_phy: dp-phy { >> + compatible = "mediatek,mt8195-dp-phy"; >> + mediatek,dp-syscon = <&dp_tx>; >> + #phy-cells = <0>; >> + }; >> -- >> 2.34.1 >> >> From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C65D5C433EF for ; Tue, 12 Apr 2022 10:06:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date: MIME-Version:In-Reply-To:References:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=qMx/hzo78QcvEpPSYOO3BvkVN7wbqiEQhU/s8tsmU7Y=; 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Tue, 12 Apr 2022 03:06:09 -0700 (PDT) Received: from 753933720722 named unknown by gmailapi.google.com with HTTPREST; Tue, 12 Apr 2022 03:06:08 -0700 From: Guillaume Ranquet User-Agent: meli 0.7.2 References: <20220327223927.20848-1-granquet@baylibre.com> <20220327223927.20848-4-granquet@baylibre.com> In-Reply-To: MIME-Version: 1.0 Date: Tue, 12 Apr 2022 03:06:08 -0700 Message-ID: Subject: Re: [PATCH v9 03/22] dt-bindings: mediatek,dp_phy: Add Display Port PHY binding To: Rob Herring Cc: airlied@linux.ie, angelogioacchino.delregno@collabora.com, chunfeng.yun@mediatek.com, chunkuang.hu@kernel.org, ck.hu@mediatek.com, daniel@ffwll.ch, deller@gmx.de, jitao.shi@mediatek.com, kishon@ti.com, krzk+dt@kernel.org, maarten.lankhorst@linux.intel.com, matthias.bgg@gmail.com, mripard@kernel.org, p.zabel@pengutronix.de, tzimmermann@suse.de, vkoul@kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, markyacoub@google.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220412_030611_571091_A86A6BDD X-CRM114-Status: GOOD ( 11.28 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Wed, 30 Mar 2022 00:58, Rob Herring wrote: >On Mon, Mar 28, 2022 at 12:39:08AM +0200, Guillaume Ranquet wrote: >> This phy controller is embedded in the Display Port Controller on mt8195 SoCs. > >Sorry, but I think you need to go back to what you had in v8. While yes, >the phy and controller IP often do change independently, this h/w looks >pretty interwined. Understood, I'll revert back to v8. > >You could make the controller a phy provider to itself if you wanted. Not sure I follow, could you point me to an example? Thx, Guillaume. > >> >> Signed-off-by: Guillaume Ranquet >> --- >> .../bindings/phy/mediatek,dp-phy.yaml | 43 +++++++++++++++++++ >> 1 file changed, 43 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >> >> diff --git a/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >> new file mode 100644 >> index 000000000000..1f5ffca4e140 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >> @@ -0,0 +1,43 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +# Copyright (c) 2022 MediaTek >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/mediatek,dp-phy.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: MediaTek Display Port PHY >> + >> +maintainers: >> + - CK Hu >> + - Jitao shi >> + >> +description: | >> + Device tree bindings for the Mediatek (embedded) Display Port PHY >> + present on some Mediatek SoCs. >> + >> +properties: >> + compatible: >> + enum: >> + - mediatek,mt8195-dp-phy >> + >> + mediatek,dp-syscon: >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: Phandle to the Display Port node. >> + >> + "#phy-cells": >> + const: 0 >> + >> +required: >> + - compatible >> + - mediatek,dp-syscon >> + - "#phy-cells" >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + dp_phy: dp-phy { >> + compatible = "mediatek,mt8195-dp-phy"; >> + mediatek,dp-syscon = <&dp_tx>; >> + #phy-cells = <0>; >> + }; >> -- >> 2.34.1 >> >> -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0910C433EF for ; Tue, 12 Apr 2022 10:08:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date: MIME-Version:In-Reply-To:References:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; 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Tue, 12 Apr 2022 03:06:09 -0700 (PDT) Received: from 753933720722 named unknown by gmailapi.google.com with HTTPREST; Tue, 12 Apr 2022 03:06:08 -0700 From: Guillaume Ranquet User-Agent: meli 0.7.2 References: <20220327223927.20848-1-granquet@baylibre.com> <20220327223927.20848-4-granquet@baylibre.com> In-Reply-To: MIME-Version: 1.0 Date: Tue, 12 Apr 2022 03:06:08 -0700 Message-ID: Subject: Re: [PATCH v9 03/22] dt-bindings: mediatek,dp_phy: Add Display Port PHY binding To: Rob Herring Cc: airlied@linux.ie, angelogioacchino.delregno@collabora.com, chunfeng.yun@mediatek.com, chunkuang.hu@kernel.org, ck.hu@mediatek.com, daniel@ffwll.ch, deller@gmx.de, jitao.shi@mediatek.com, kishon@ti.com, krzk+dt@kernel.org, maarten.lankhorst@linux.intel.com, matthias.bgg@gmail.com, mripard@kernel.org, p.zabel@pengutronix.de, tzimmermann@suse.de, vkoul@kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-fbdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, markyacoub@google.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220412_030611_190742_AEAA24FA X-CRM114-Status: GOOD ( 12.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 30 Mar 2022 00:58, Rob Herring wrote: >On Mon, Mar 28, 2022 at 12:39:08AM +0200, Guillaume Ranquet wrote: >> This phy controller is embedded in the Display Port Controller on mt8195 SoCs. > >Sorry, but I think you need to go back to what you had in v8. While yes, >the phy and controller IP often do change independently, this h/w looks >pretty interwined. Understood, I'll revert back to v8. > >You could make the controller a phy provider to itself if you wanted. Not sure I follow, could you point me to an example? Thx, Guillaume. > >> >> Signed-off-by: Guillaume Ranquet >> --- >> .../bindings/phy/mediatek,dp-phy.yaml | 43 +++++++++++++++++++ >> 1 file changed, 43 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >> >> diff --git a/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >> new file mode 100644 >> index 000000000000..1f5ffca4e140 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >> @@ -0,0 +1,43 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +# Copyright (c) 2022 MediaTek >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/mediatek,dp-phy.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: MediaTek Display Port PHY >> + >> +maintainers: >> + - CK Hu >> + - Jitao shi >> + >> +description: | >> + Device tree bindings for the Mediatek (embedded) Display Port PHY >> + present on some Mediatek SoCs. >> + >> +properties: >> + compatible: >> + enum: >> + - mediatek,mt8195-dp-phy >> + >> + mediatek,dp-syscon: >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: Phandle to the Display Port node. >> + >> + "#phy-cells": >> + const: 0 >> + >> +required: >> + - compatible >> + - mediatek,dp-syscon >> + - "#phy-cells" >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + dp_phy: dp-phy { >> + compatible = "mediatek,mt8195-dp-phy"; >> + mediatek,dp-syscon = <&dp_tx>; >> + #phy-cells = <0>; >> + }; >> -- >> 2.34.1 >> >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 701DAC433F5 for ; Tue, 12 Apr 2022 11:24:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234261AbiDLL0t (ORCPT ); Tue, 12 Apr 2022 07:26:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347599AbiDLLZd (ORCPT ); Tue, 12 Apr 2022 07:25:33 -0400 Received: from mail-oa1-x32.google.com (mail-oa1-x32.google.com [IPv6:2001:4860:4864:20::32]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41C97A0BFA for ; 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charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 30 Mar 2022 00:58, Rob Herring wrote: >On Mon, Mar 28, 2022 at 12:39:08AM +0200, Guillaume Ranquet wrote: >> This phy controller is embedded in the Display Port Controller on mt8195 SoCs. > >Sorry, but I think you need to go back to what you had in v8. While yes, >the phy and controller IP often do change independently, this h/w looks >pretty interwined. Understood, I'll revert back to v8. > >You could make the controller a phy provider to itself if you wanted. Not sure I follow, could you point me to an example? Thx, Guillaume. > >> >> Signed-off-by: Guillaume Ranquet >> --- >> .../bindings/phy/mediatek,dp-phy.yaml | 43 +++++++++++++++++++ >> 1 file changed, 43 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >> >> diff --git a/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >> new file mode 100644 >> index 000000000000..1f5ffca4e140 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml >> @@ -0,0 +1,43 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +# Copyright (c) 2022 MediaTek >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/mediatek,dp-phy.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: MediaTek Display Port PHY >> + >> +maintainers: >> + - CK Hu >> + - Jitao shi >> + >> +description: | >> + Device tree bindings for the Mediatek (embedded) Display Port PHY >> + present on some Mediatek SoCs. >> + >> +properties: >> + compatible: >> + enum: >> + - mediatek,mt8195-dp-phy >> + >> + mediatek,dp-syscon: >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: Phandle to the Display Port node. >> + >> + "#phy-cells": >> + const: 0 >> + >> +required: >> + - compatible >> + - mediatek,dp-syscon >> + - "#phy-cells" >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + dp_phy: dp-phy { >> + compatible = "mediatek,mt8195-dp-phy"; >> + mediatek,dp-syscon = <&dp_tx>; >> + #phy-cells = <0>; >> + }; >> -- >> 2.34.1 >> >>