From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 905E6C6FA83 for ; Tue, 27 Sep 2022 13:54:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231808AbiI0Nyp (ORCPT ); Tue, 27 Sep 2022 09:54:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230334AbiI0Nyk (ORCPT ); Tue, 27 Sep 2022 09:54:40 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 672DE1057A for ; Tue, 27 Sep 2022 06:54:34 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id z20so2263197plb.10 for ; Tue, 27 Sep 2022 06:54:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:mime-version:in-reply-to:references :user-agent:from:from:to:cc:subject:date; bh=5qwETXszsJHRG+KNZAfDuGy2+IIkJBoKDnABLfH60tQ=; b=f6CmSv0OlzXmED5tWFMSEinGTJEbhs3apO2o1WVlHEn+fFfXX/l+1/NWVY0KujLper X/2WcJl9nH8Xw5kR9mL+LHRjOMu43tSGWSUwpvW9zKPDPXKjDOCRlWV7xlNA4fU9O3uO EMLs8HS8JsxOPDDfvIp20W1TauC+8dKOsL0XnOUFHRZiSa+Zbjqid1dyRpVlomKM4otZ zh6z3rpfTqgJ1FKaCaI+uRceIOXR7ELINnOEvNzy5OSpCn6dwVULSLU4AeDcDUINb9b0 wiTFGntz5cRLbyKXTdNoLvrKQdmT7WT5bwZGjE1l5eZ42VfsffuzvLg2MDN0nikd2ZHZ OhNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:mime-version:in-reply-to:references :user-agent:from:x-gm-message-state:from:to:cc:subject:date; bh=5qwETXszsJHRG+KNZAfDuGy2+IIkJBoKDnABLfH60tQ=; b=Y9GvkICwygXNTB3X0Hf+l3xn/IzDqYdJRJJEeqUS2KStOWeLRs7jbZmAHk3jVOuLfi DL9xcXoFAWvkEuLpvStyvRdeSZobk76LAHwKUmS5wHV2NVFVzqftVOERjuQTfURyaHCp F0IgSasxSzfOk6/2hpIiKG/Ji/Ghtx1Sx536+1WU1+8wcCCDv8y7boET045MQ7hXLudd ra83952bCcy1L0ZGnetF8/wG/CTL2WSltKB0NwZOLKkewi+yp+GjUf58niUMJJ0FuBEc b9+SXMY9XNQu+XU+x/NoFHdsb/I1kxUxg2obFPFrwu+/XX+auQvF+9kpQq7PzhzOg7gt evAg== X-Gm-Message-State: ACrzQf3BXaM5TCEKjQWiVSDBVEo6sbzO5x9QBoA6aFW9U9o+F73EuTNo 7JzghcO4VBTRJHzYZWkbRjUPIv9Oc/UBSJwh1mK9Ey44XFA= X-Google-Smtp-Source: AMsMyM4+x7J4OZ7W3bVeH4hHPFvWPmyfihQv01BR+E1ukDBABSgNNIPaY8dNmMrk3y51NserN90WcMrsVcQRB6ZIwYk= X-Received: by 2002:a17:90b:3807:b0:205:d746:93a0 with SMTP id mq7-20020a17090b380700b00205d74693a0mr3837620pjb.188.1664286873871; Tue, 27 Sep 2022 06:54:33 -0700 (PDT) Received: from 753933720722 named unknown by gmailapi.google.com with HTTPREST; Tue, 27 Sep 2022 06:54:33 -0700 From: Guillaume Ranquet User-Agent: meli 0.7.2 References: <20220919-v1-0-4844816c9808@baylibre.com> <20220919-v1-4-4844816c9808@baylibre.com> <260bb17f-efc8-1287-3e03-f9b8e79a6e31@linaro.org> In-Reply-To: <260bb17f-efc8-1287-3e03-f9b8e79a6e31@linaro.org> MIME-Version: 1.0 Date: Tue, 27 Sep 2022 06:54:33 -0700 Message-ID: Subject: Re: [PATCH v1 04/17] dt-bindings: display: mediatek: add MT8195 hdmi bindings To: Krzysztof Kozlowski , Matthias Brugger , Vinod Koul , Stephen Boyd , David Airlie , Rob Herring , Philipp Zabel , Krzysztof Kozlowski , Daniel Vetter , Chunfeng Yun , CK Hu , Jitao shi , Chun-Kuang Hu , Michael Turquette , Kishon Vijay Abraham I Cc: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org, Pablo Sun , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Mattijs Korpershoek , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 22 Sep 2022 09:18, Krzysztof Kozlowski wrote: >On 19/09/2022 18:56, Guillaume Ranquet wrote: >> Add mt8195 SoC bindings for hdmi and hdmi-ddc >> >> Make port1 optional for mt8195 as it only supports HDMI tx for now. >> Requires a ddc-i2c-bus phandle. >> Requires a power-domains phandle. >> >> Signed-off-by: Guillaume Ranquet >> >> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml >> index bdaf0b51e68c..abb231a0694b 100644 >> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml >> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml >> @@ -21,6 +21,10 @@ properties: >> - mediatek,mt7623-hdmi >> - mediatek,mt8167-hdmi >> - mediatek,mt8173-hdmi >> + - mediatek,mt8195-hdmi >> + >> + clocks: true >> + clock-names: true > >???? >Why is this moved? > >> >> reg: >> maxItems: 1 >> @@ -28,20 +32,6 @@ properties: >> interrupts: >> maxItems: 1 >> >> - clocks: >> - items: >> - - description: Pixel Clock >> - - description: HDMI PLL >> - - description: Bit Clock >> - - description: S/PDIF Clock >> - >> - clock-names: >> - items: >> - - const: pixel >> - - const: pll >> - - const: bclk >> - - const: spdif > >Clock definition with constraints should stay here. You just customize >it per variant. > Clocks are different between the two hardwares, so I've tried moving everything inside the if/else block. Is there a better way to express this? >> - >> phys: >> maxItems: 1 >> >> @@ -58,6 +48,16 @@ properties: >> description: | >> phandle link and register offset to the system configuration registers. >> >> + ddc-i2c-bus: >> + $ref: '/schemas/types.yaml#/definitions/phandle' > >Drop quotes > >> + description: Phandle to the ddc-i2c device > >Isn't this property of panel? > It's a property used in panels and connectors. But since this IP doesn't use a connector per say, I've added the property here. Which doesn't sound reasonnable when I'm explaining it like this... I'll see what I can do to fit a connector and have things look a bit more standard. >> + >> + power-domains: >> + description: >> + A phandle and PM domain specifier as defined by bindings >> + of the power controller specified by phandle. See >> + Documentation/devicetree/bindings/power/power-domain.yaml for details. > >No need for this text. This is standard property. You miss maxItems. > > >> + >> ports: >> $ref: /schemas/graph.yaml#/properties/ports >> >> @@ -76,7 +76,6 @@ properties: >> >> required: >> - port@0 >> - - port@1 >> >> required: >> - compatible >> @@ -86,9 +85,55 @@ required: >> - clock-names >> - phys >> - phy-names >> - - mediatek,syscon-hdmi >> - ports >> >> +allOf: >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: mediatek,mt8195-hdmi >> + then: >> + properties: >> + clocks: >> + items: >> + - description: APB >> + - description: HDCP >> + - description: HDCP 24M >> + - description: Split HDMI >> + clock-names: >> + items: >> + - const: hdmi_apb_sel >> + - const: hdcp_sel >> + - const: hdcp24_sel >> + - const: split_hdmi > >Clocks are entirely different. I am not sure there is benefit in keeping >these devices in one bindings. > I agree with that, but it was requested by CK that the driver and bindings be as common as possible. >> + >> + required: >> + - power-domains >> + - ddc-i2c-bus > >Blank line, > >> + else: >> + properties: >> + clocks: >> + items: >> + - description: Pixel Clock >> + - description: HDMI PLL >> + - description: Bit Clock >> + - description: S/PDIF Clock >> + >> + clock-names: >> + items: >> + - const: pixel >> + - const: pll >> + - const: bclk >> + - const: spdif >> + >> + ports: >> + required: >> + - port@1 >> + >> + required: >> + - mediatek,syscon-hdmi >> + >> additionalProperties: false >> >> examples: >> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml >> new file mode 100644 >> index 000000000000..3c80bcebe6d3 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml >> @@ -0,0 +1,45 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Mediatek HDMI DDC Device Tree Bindings for mt8195 > >Drop Device Tree Bindings > >> + >> +maintainers: >> + - CK Hu >> + - Jitao shi >> + >> +description: | >> + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. > >Why is this different than existing ddc bindings? > This ddc is actually part of the MT8195 hdmi IP. So it is a bit simpler than the mediatek,hdmi-ddc.yaml As it has only one clock, no reg, no interrupts. >> + >> +properties: >> + compatible: >> + enum: >> + - mediatek,mt8195-hdmi-ddc >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: ddc-i2c >> + >> +required: >> + - compatible >> + - clocks >> + - clock-names >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + hdmiddc0: ddc_i2c { > >No underscores in node names. Generic node names. > > >Best regards, >Krzysztof > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88584C6FA83 for ; Tue, 27 Sep 2022 13:54:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BA24E10E943; Tue, 27 Sep 2022 13:54:36 +0000 (UTC) Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5B32210E943 for ; Tue, 27 Sep 2022 13:54:34 +0000 (UTC) Received: by mail-pj1-x1032.google.com with SMTP id x1-20020a17090ab00100b001fda21bbc90so15629880pjq.3 for ; Tue, 27 Sep 2022 06:54:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:mime-version:in-reply-to:references :user-agent:from:from:to:cc:subject:date; bh=5qwETXszsJHRG+KNZAfDuGy2+IIkJBoKDnABLfH60tQ=; b=f6CmSv0OlzXmED5tWFMSEinGTJEbhs3apO2o1WVlHEn+fFfXX/l+1/NWVY0KujLper X/2WcJl9nH8Xw5kR9mL+LHRjOMu43tSGWSUwpvW9zKPDPXKjDOCRlWV7xlNA4fU9O3uO EMLs8HS8JsxOPDDfvIp20W1TauC+8dKOsL0XnOUFHRZiSa+Zbjqid1dyRpVlomKM4otZ zh6z3rpfTqgJ1FKaCaI+uRceIOXR7ELINnOEvNzy5OSpCn6dwVULSLU4AeDcDUINb9b0 wiTFGntz5cRLbyKXTdNoLvrKQdmT7WT5bwZGjE1l5eZ42VfsffuzvLg2MDN0nikd2ZHZ OhNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:mime-version:in-reply-to:references :user-agent:from:x-gm-message-state:from:to:cc:subject:date; bh=5qwETXszsJHRG+KNZAfDuGy2+IIkJBoKDnABLfH60tQ=; b=eKjUuGbThzjQscl0I6TuBDtDuD/FVStdwMWuN/bXuJrRY7WyWPKoE8Jt93UqW+54oE Fhum5JMdAHgcA9l454wju+Ynv0fHxp3DWSVyLxp2Ri1AZlwEn8ARiyv2tUq3UeBE/5I4 uGQ+OXNOt3MR/69huHhCMtiHmParWBP+ATnx7sl5C55zNKrG/LNibmiCHVsQdooeHOfR +P2YzATrUapiFC9O6JrvY83YcrS+DxoMEMY1fKnVFOwoUv060JQBUk//i7FQAjY/Y9Ru XCvOmKu0dIxpNYEm1c2XfOq8Mg0ex7JwaMBQEbYswjaKiTsZi++Pa6hVieD27sUDPZ/S zVhw== X-Gm-Message-State: ACrzQf3L2w7zOLBoekE9gqgQCW7kSbVBRl0n83XPtJS8OHDglY0p+39g WflmRMa+Pba9XQVr1naJ61KubyJAZUNnH67NoI9xGg== X-Google-Smtp-Source: AMsMyM4+x7J4OZ7W3bVeH4hHPFvWPmyfihQv01BR+E1ukDBABSgNNIPaY8dNmMrk3y51NserN90WcMrsVcQRB6ZIwYk= X-Received: by 2002:a17:90b:3807:b0:205:d746:93a0 with SMTP id mq7-20020a17090b380700b00205d74693a0mr3837620pjb.188.1664286873871; Tue, 27 Sep 2022 06:54:33 -0700 (PDT) Received: from 753933720722 named unknown by gmailapi.google.com with HTTPREST; Tue, 27 Sep 2022 06:54:33 -0700 From: Guillaume Ranquet User-Agent: meli 0.7.2 References: <20220919-v1-0-4844816c9808@baylibre.com> <20220919-v1-4-4844816c9808@baylibre.com> <260bb17f-efc8-1287-3e03-f9b8e79a6e31@linaro.org> In-Reply-To: <260bb17f-efc8-1287-3e03-f9b8e79a6e31@linaro.org> MIME-Version: 1.0 Date: Tue, 27 Sep 2022 06:54:33 -0700 Message-ID: Subject: Re: [PATCH v1 04/17] dt-bindings: display: mediatek: add MT8195 hdmi bindings To: Krzysztof Kozlowski , Matthias Brugger , Vinod Koul , Stephen Boyd , David Airlie , Rob Herring , Philipp Zabel , Krzysztof Kozlowski , Daniel Vetter , Chunfeng Yun , CK Hu , Jitao shi , Chun-Kuang Hu , Michael Turquette , Kishon Vijay Abraham I Content-Type: text/plain; charset="UTF-8" X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Mattijs Korpershoek , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, Pablo Sun , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, 22 Sep 2022 09:18, Krzysztof Kozlowski wrote: >On 19/09/2022 18:56, Guillaume Ranquet wrote: >> Add mt8195 SoC bindings for hdmi and hdmi-ddc >> >> Make port1 optional for mt8195 as it only supports HDMI tx for now. >> Requires a ddc-i2c-bus phandle. >> Requires a power-domains phandle. >> >> Signed-off-by: Guillaume Ranquet >> >> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml >> index bdaf0b51e68c..abb231a0694b 100644 >> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml >> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml >> @@ -21,6 +21,10 @@ properties: >> - mediatek,mt7623-hdmi >> - mediatek,mt8167-hdmi >> - mediatek,mt8173-hdmi >> + - mediatek,mt8195-hdmi >> + >> + clocks: true >> + clock-names: true > >???? >Why is this moved? > >> >> reg: >> maxItems: 1 >> @@ -28,20 +32,6 @@ properties: >> interrupts: >> maxItems: 1 >> >> - clocks: >> - items: >> - - description: Pixel Clock >> - - description: HDMI PLL >> - - description: Bit Clock >> - - description: S/PDIF Clock >> - >> - clock-names: >> - items: >> - - const: pixel >> - - const: pll >> - - const: bclk >> - - const: spdif > >Clock definition with constraints should stay here. You just customize >it per variant. > Clocks are different between the two hardwares, so I've tried moving everything inside the if/else block. Is there a better way to express this? >> - >> phys: >> maxItems: 1 >> >> @@ -58,6 +48,16 @@ properties: >> description: | >> phandle link and register offset to the system configuration registers. >> >> + ddc-i2c-bus: >> + $ref: '/schemas/types.yaml#/definitions/phandle' > >Drop quotes > >> + description: Phandle to the ddc-i2c device > >Isn't this property of panel? > It's a property used in panels and connectors. But since this IP doesn't use a connector per say, I've added the property here. Which doesn't sound reasonnable when I'm explaining it like this... I'll see what I can do to fit a connector and have things look a bit more standard. >> + >> + power-domains: >> + description: >> + A phandle and PM domain specifier as defined by bindings >> + of the power controller specified by phandle. See >> + Documentation/devicetree/bindings/power/power-domain.yaml for details. > >No need for this text. This is standard property. You miss maxItems. > > >> + >> ports: >> $ref: /schemas/graph.yaml#/properties/ports >> >> @@ -76,7 +76,6 @@ properties: >> >> required: >> - port@0 >> - - port@1 >> >> required: >> - compatible >> @@ -86,9 +85,55 @@ required: >> - clock-names >> - phys >> - phy-names >> - - mediatek,syscon-hdmi >> - ports >> >> +allOf: >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: mediatek,mt8195-hdmi >> + then: >> + properties: >> + clocks: >> + items: >> + - description: APB >> + - description: HDCP >> + - description: HDCP 24M >> + - description: Split HDMI >> + clock-names: >> + items: >> + - const: hdmi_apb_sel >> + - const: hdcp_sel >> + - const: hdcp24_sel >> + - const: split_hdmi > >Clocks are entirely different. I am not sure there is benefit in keeping >these devices in one bindings. > I agree with that, but it was requested by CK that the driver and bindings be as common as possible. >> + >> + required: >> + - power-domains >> + - ddc-i2c-bus > >Blank line, > >> + else: >> + properties: >> + clocks: >> + items: >> + - description: Pixel Clock >> + - description: HDMI PLL >> + - description: Bit Clock >> + - description: S/PDIF Clock >> + >> + clock-names: >> + items: >> + - const: pixel >> + - const: pll >> + - const: bclk >> + - const: spdif >> + >> + ports: >> + required: >> + - port@1 >> + >> + required: >> + - mediatek,syscon-hdmi >> + >> additionalProperties: false >> >> examples: >> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml >> new file mode 100644 >> index 000000000000..3c80bcebe6d3 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml >> @@ -0,0 +1,45 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Mediatek HDMI DDC Device Tree Bindings for mt8195 > >Drop Device Tree Bindings > >> + >> +maintainers: >> + - CK Hu >> + - Jitao shi >> + >> +description: | >> + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. > >Why is this different than existing ddc bindings? > This ddc is actually part of the MT8195 hdmi IP. So it is a bit simpler than the mediatek,hdmi-ddc.yaml As it has only one clock, no reg, no interrupts. >> + >> +properties: >> + compatible: >> + enum: >> + - mediatek,mt8195-hdmi-ddc >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: ddc-i2c >> + >> +required: >> + - compatible >> + - clocks >> + - clock-names >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + hdmiddc0: ddc_i2c { > >No underscores in node names. Generic node names. > > >Best regards, >Krzysztof > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61D58C6FA83 for ; Tue, 27 Sep 2022 13:54:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date: MIME-Version:In-Reply-To:References:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=iMj7y6m1MJmfCsdau3OYPZVzW0CsmAvnoSOfXsPwoeI=; b=3+/s3RM5ve8I5X6eIyc2wsl8rL cp36viG4pA06ziA8TuMYGxuNMh3j5URTNL2ykGIS54ZoLVGxiTr27qycDBbee1k49Y3hcBMW2ZMf0 z5eHQ+CqlluER2bmnTmLdRZSEJxnTKoKUve3WFFdBuwjWTsmQ/7OS4jzG6fsS+HcS9bOH2PnjbtMi fG85OrfVA/FPo+t+t1ZavKXQerEQsCSEIUCfZaqOPLd6PxfdfEiGc5jESg1yr5vNXCcllP5//jLEN B9y3Ufg1mn+MR/kgk4FaZBiauu9Qdbobxk2JTH8NFc0htz6IvHVds4+QrYiNoAoz+aSGhL6bR0oal 1LkUwyWQ==; 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Tue, 27 Sep 2022 06:54:33 -0700 From: Guillaume Ranquet User-Agent: meli 0.7.2 References: <20220919-v1-0-4844816c9808@baylibre.com> <20220919-v1-4-4844816c9808@baylibre.com> <260bb17f-efc8-1287-3e03-f9b8e79a6e31@linaro.org> In-Reply-To: <260bb17f-efc8-1287-3e03-f9b8e79a6e31@linaro.org> MIME-Version: 1.0 Date: Tue, 27 Sep 2022 06:54:33 -0700 Message-ID: Subject: Re: [PATCH v1 04/17] dt-bindings: display: mediatek: add MT8195 hdmi bindings To: Krzysztof Kozlowski , Matthias Brugger , Vinod Koul , Stephen Boyd , David Airlie , Rob Herring , Philipp Zabel , Krzysztof Kozlowski , Daniel Vetter , Chunfeng Yun , CK Hu , Jitao shi , Chun-Kuang Hu , Michael Turquette , Kishon Vijay Abraham I Cc: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org, Pablo Sun , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Mattijs Korpershoek , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220927_065435_583420_4839CD8A X-CRM114-Status: GOOD ( 20.64 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Thu, 22 Sep 2022 09:18, Krzysztof Kozlowski wrote: >On 19/09/2022 18:56, Guillaume Ranquet wrote: >> Add mt8195 SoC bindings for hdmi and hdmi-ddc >> >> Make port1 optional for mt8195 as it only supports HDMI tx for now. >> Requires a ddc-i2c-bus phandle. >> Requires a power-domains phandle. >> >> Signed-off-by: Guillaume Ranquet >> >> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml >> index bdaf0b51e68c..abb231a0694b 100644 >> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml >> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml >> @@ -21,6 +21,10 @@ properties: >> - mediatek,mt7623-hdmi >> - mediatek,mt8167-hdmi >> - mediatek,mt8173-hdmi >> + - mediatek,mt8195-hdmi >> + >> + clocks: true >> + clock-names: true > >???? >Why is this moved? > >> >> reg: >> maxItems: 1 >> @@ -28,20 +32,6 @@ properties: >> interrupts: >> maxItems: 1 >> >> - clocks: >> - items: >> - - description: Pixel Clock >> - - description: HDMI PLL >> - - description: Bit Clock >> - - description: S/PDIF Clock >> - >> - clock-names: >> - items: >> - - const: pixel >> - - const: pll >> - - const: bclk >> - - const: spdif > >Clock definition with constraints should stay here. You just customize >it per variant. > Clocks are different between the two hardwares, so I've tried moving everything inside the if/else block. Is there a better way to express this? >> - >> phys: >> maxItems: 1 >> >> @@ -58,6 +48,16 @@ properties: >> description: | >> phandle link and register offset to the system configuration registers. >> >> + ddc-i2c-bus: >> + $ref: '/schemas/types.yaml#/definitions/phandle' > >Drop quotes > >> + description: Phandle to the ddc-i2c device > >Isn't this property of panel? > It's a property used in panels and connectors. But since this IP doesn't use a connector per say, I've added the property here. Which doesn't sound reasonnable when I'm explaining it like this... I'll see what I can do to fit a connector and have things look a bit more standard. >> + >> + power-domains: >> + description: >> + A phandle and PM domain specifier as defined by bindings >> + of the power controller specified by phandle. See >> + Documentation/devicetree/bindings/power/power-domain.yaml for details. > >No need for this text. This is standard property. You miss maxItems. > > >> + >> ports: >> $ref: /schemas/graph.yaml#/properties/ports >> >> @@ -76,7 +76,6 @@ properties: >> >> required: >> - port@0 >> - - port@1 >> >> required: >> - compatible >> @@ -86,9 +85,55 @@ required: >> - clock-names >> - phys >> - phy-names >> - - mediatek,syscon-hdmi >> - ports >> >> +allOf: >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: mediatek,mt8195-hdmi >> + then: >> + properties: >> + clocks: >> + items: >> + - description: APB >> + - description: HDCP >> + - description: HDCP 24M >> + - description: Split HDMI >> + clock-names: >> + items: >> + - const: hdmi_apb_sel >> + - const: hdcp_sel >> + - const: hdcp24_sel >> + - const: split_hdmi > >Clocks are entirely different. I am not sure there is benefit in keeping >these devices in one bindings. > I agree with that, but it was requested by CK that the driver and bindings be as common as possible. >> + >> + required: >> + - power-domains >> + - ddc-i2c-bus > >Blank line, > >> + else: >> + properties: >> + clocks: >> + items: >> + - description: Pixel Clock >> + - description: HDMI PLL >> + - description: Bit Clock >> + - description: S/PDIF Clock >> + >> + clock-names: >> + items: >> + - const: pixel >> + - const: pll >> + - const: bclk >> + - const: spdif >> + >> + ports: >> + required: >> + - port@1 >> + >> + required: >> + - mediatek,syscon-hdmi >> + >> additionalProperties: false >> >> examples: >> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml >> new file mode 100644 >> index 000000000000..3c80bcebe6d3 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml >> @@ -0,0 +1,45 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Mediatek HDMI DDC Device Tree Bindings for mt8195 > >Drop Device Tree Bindings > >> + >> +maintainers: >> + - CK Hu >> + - Jitao shi >> + >> +description: | >> + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. > >Why is this different than existing ddc bindings? > This ddc is actually part of the MT8195 hdmi IP. So it is a bit simpler than the mediatek,hdmi-ddc.yaml As it has only one clock, no reg, no interrupts. >> + >> +properties: >> + compatible: >> + enum: >> + - mediatek,mt8195-hdmi-ddc >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: ddc-i2c >> + >> +required: >> + - compatible >> + - clocks >> + - clock-names >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + hdmiddc0: ddc_i2c { > >No underscores in node names. Generic node names. > > >Best regards, >Krzysztof > -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 664BAC6FA83 for ; Tue, 27 Sep 2022 13:55:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date: MIME-Version:In-Reply-To:References:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; 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Tue, 27 Sep 2022 06:54:33 -0700 (PDT) Received: from 753933720722 named unknown by gmailapi.google.com with HTTPREST; Tue, 27 Sep 2022 06:54:33 -0700 From: Guillaume Ranquet User-Agent: meli 0.7.2 References: <20220919-v1-0-4844816c9808@baylibre.com> <20220919-v1-4-4844816c9808@baylibre.com> <260bb17f-efc8-1287-3e03-f9b8e79a6e31@linaro.org> In-Reply-To: <260bb17f-efc8-1287-3e03-f9b8e79a6e31@linaro.org> MIME-Version: 1.0 Date: Tue, 27 Sep 2022 06:54:33 -0700 Message-ID: Subject: Re: [PATCH v1 04/17] dt-bindings: display: mediatek: add MT8195 hdmi bindings To: Krzysztof Kozlowski , Matthias Brugger , Vinod Koul , Stephen Boyd , David Airlie , Rob Herring , Philipp Zabel , Krzysztof Kozlowski , Daniel Vetter , Chunfeng Yun , CK Hu , Jitao shi , Chun-Kuang Hu , Michael Turquette , Kishon Vijay Abraham I Cc: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org, Pablo Sun , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Mattijs Korpershoek , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220927_065435_002758_89FABC49 X-CRM114-Status: GOOD ( 22.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 22 Sep 2022 09:18, Krzysztof Kozlowski wrote: >On 19/09/2022 18:56, Guillaume Ranquet wrote: >> Add mt8195 SoC bindings for hdmi and hdmi-ddc >> >> Make port1 optional for mt8195 as it only supports HDMI tx for now. >> Requires a ddc-i2c-bus phandle. >> Requires a power-domains phandle. >> >> Signed-off-by: Guillaume Ranquet >> >> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml >> index bdaf0b51e68c..abb231a0694b 100644 >> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml >> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml >> @@ -21,6 +21,10 @@ properties: >> - mediatek,mt7623-hdmi >> - mediatek,mt8167-hdmi >> - mediatek,mt8173-hdmi >> + - mediatek,mt8195-hdmi >> + >> + clocks: true >> + clock-names: true > >???? >Why is this moved? > >> >> reg: >> maxItems: 1 >> @@ -28,20 +32,6 @@ properties: >> interrupts: >> maxItems: 1 >> >> - clocks: >> - items: >> - - description: Pixel Clock >> - - description: HDMI PLL >> - - description: Bit Clock >> - - description: S/PDIF Clock >> - >> - clock-names: >> - items: >> - - const: pixel >> - - const: pll >> - - const: bclk >> - - const: spdif > >Clock definition with constraints should stay here. You just customize >it per variant. > Clocks are different between the two hardwares, so I've tried moving everything inside the if/else block. Is there a better way to express this? >> - >> phys: >> maxItems: 1 >> >> @@ -58,6 +48,16 @@ properties: >> description: | >> phandle link and register offset to the system configuration registers. >> >> + ddc-i2c-bus: >> + $ref: '/schemas/types.yaml#/definitions/phandle' > >Drop quotes > >> + description: Phandle to the ddc-i2c device > >Isn't this property of panel? > It's a property used in panels and connectors. But since this IP doesn't use a connector per say, I've added the property here. Which doesn't sound reasonnable when I'm explaining it like this... I'll see what I can do to fit a connector and have things look a bit more standard. >> + >> + power-domains: >> + description: >> + A phandle and PM domain specifier as defined by bindings >> + of the power controller specified by phandle. See >> + Documentation/devicetree/bindings/power/power-domain.yaml for details. > >No need for this text. This is standard property. You miss maxItems. > > >> + >> ports: >> $ref: /schemas/graph.yaml#/properties/ports >> >> @@ -76,7 +76,6 @@ properties: >> >> required: >> - port@0 >> - - port@1 >> >> required: >> - compatible >> @@ -86,9 +85,55 @@ required: >> - clock-names >> - phys >> - phy-names >> - - mediatek,syscon-hdmi >> - ports >> >> +allOf: >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: mediatek,mt8195-hdmi >> + then: >> + properties: >> + clocks: >> + items: >> + - description: APB >> + - description: HDCP >> + - description: HDCP 24M >> + - description: Split HDMI >> + clock-names: >> + items: >> + - const: hdmi_apb_sel >> + - const: hdcp_sel >> + - const: hdcp24_sel >> + - const: split_hdmi > >Clocks are entirely different. I am not sure there is benefit in keeping >these devices in one bindings. > I agree with that, but it was requested by CK that the driver and bindings be as common as possible. >> + >> + required: >> + - power-domains >> + - ddc-i2c-bus > >Blank line, > >> + else: >> + properties: >> + clocks: >> + items: >> + - description: Pixel Clock >> + - description: HDMI PLL >> + - description: Bit Clock >> + - description: S/PDIF Clock >> + >> + clock-names: >> + items: >> + - const: pixel >> + - const: pll >> + - const: bclk >> + - const: spdif >> + >> + ports: >> + required: >> + - port@1 >> + >> + required: >> + - mediatek,syscon-hdmi >> + >> additionalProperties: false >> >> examples: >> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml >> new file mode 100644 >> index 000000000000..3c80bcebe6d3 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml >> @@ -0,0 +1,45 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Mediatek HDMI DDC Device Tree Bindings for mt8195 > >Drop Device Tree Bindings > >> + >> +maintainers: >> + - CK Hu >> + - Jitao shi >> + >> +description: | >> + The HDMI DDC i2c controller is used to interface with the HDMI DDC pins. > >Why is this different than existing ddc bindings? > This ddc is actually part of the MT8195 hdmi IP. So it is a bit simpler than the mediatek,hdmi-ddc.yaml As it has only one clock, no reg, no interrupts. >> + >> +properties: >> + compatible: >> + enum: >> + - mediatek,mt8195-hdmi-ddc >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: ddc-i2c >> + >> +required: >> + - compatible >> + - clocks >> + - clock-names >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + hdmiddc0: ddc_i2c { > >No underscores in node names. Generic node names. > > >Best regards, >Krzysztof > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel