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Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2607:f8b0:4864:20::d44 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm , "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Apr 28, 2020 at 5:50 PM Philippe Mathieu-Daud=C3=A9 wrote: > > MIDR_EL1 a 64-bit system register with the top 32-bit being RES0. > > This fixes when compiling with -Werror=3Dconversion: > > target/arm/cpu64.c: In function =E2=80=98aarch64_max_initfn=E2=80=99: > target/arm/cpu64.c:628:21: error: conversion from =E2=80=98uint64_t=E2= =80=99 {aka =E2=80=98long unsigned int=E2=80=99} to =E2=80=98uint32_t=E2=80= =99 {aka =E2=80=98unsigned int=E2=80=99} may change value [-Werror=3Dconver= sion] > 628 | cpu->midr =3D t; > | ^ > > Suggested-by: Laurent Desnogues > Suggested-by: Peter Maydell > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > I suppose cp15.c0_cpuid register in target/arm/cpu.h as uint32_t is OK. > > Since v1: Follow Laurent and Peter suggestion. > --- > target/arm/cpu.h | 3 ++- > target/arm/cpu.c | 4 +++- > 2 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 8b9f2961ba..4d1be56df9 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -894,7 +894,7 @@ struct ARMCPU { > uint64_t id_aa64dfr0; > uint64_t id_aa64dfr1; > } isar; > - uint32_t midr; > + uint64_t midr; > uint32_t revidr; > uint32_t reset_fpsid; > uint32_t ctr; > @@ -1685,6 +1685,7 @@ FIELD(MIDR_EL1, PARTNUM, 4, 12) > FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) > FIELD(MIDR_EL1, VARIANT, 20, 4) > FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) > +FIELD(MIDR_EL1, RESERVED, 32, 32) If you follow Peter advice to not check these 32-bits, you could remove that field definition and if you keep it please rename it RES0 :-). Thanks, Laurent > > FIELD(ID_ISAR0, SWAP, 0, 4) > FIELD(ID_ISAR0, BITCOUNT, 4, 4) > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index a79f233b17..aaa48e06ac 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1182,6 +1182,8 @@ void arm_cpu_post_init(Object *obj) > { > ARMCPU *cpu =3D ARM_CPU(obj); > > + assert(FIELD_EX64(cpu->midr, MIDR_EL1, RESERVED) =3D=3D 0); > + > /* M profile implies PMSA. We have to do this here rather than > * in realize with the other feature-implication checks because > * we look at the PMSA bit to see if we should add some properties. > @@ -2757,7 +2759,7 @@ static const ARMCPUInfo arm_cpus[] =3D { > static Property arm_cpu_properties[] =3D { > DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, fal= se), > DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), > - DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), > + DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), > DEFINE_PROP_UINT64("mp-affinity", ARMCPU, > mp_affinity, ARM64_AFFINITY_INVALID), > DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID= ), > -- > 2.21.1 >