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Date: Thu, 15 Mar 2012 22:29:08 +0300
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From: Alexey Starikovskiy <aystarik@gmail.com>
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Subject: Re: [Qemu-devel] [PATCH RFC v4 08/20] target-arm: Store cp15 c0_c1
 and c0_c2 in ARMCPUClass
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, Paul Brook <paul@codesourcery.com>, =?ISO-8859-1?Q?Andreas_F=E4rber?= <afaerber@suse.de>

On Thu, Mar 15, 2012 at 11:20 PM, Peter Maydell
<peter.maydell@linaro.org> wrote:
> On 15 March 2012 19:08, Paul Brook <paul@codesourcery.com> wrote:
>>> For now set them in the reset function.
>>
>>> + =A0 =A0/* TODO Move these into arm_cpu_initfn() once no longer zeroed=
 above.*/
>>> + =A0 =A0memcpy(env->cp15.c0_c1, klass->cp15.c0_c1, 8 * sizeof(uint32_t=
));
>>> + =A0 =A0memcpy(env->cp15.c0_c2, klass->cp15.c0_c2, 8 * sizeof(uint32_t=
)); +
>>
>> Why bother copying them into the CPU state? =A0These are readonly, so an=
ything
>> that needs them should be able to use the value straight from the class
>> definitions.
>
> In my (hugely delayed) cp15 rework attempt these probably go away anyway
> in favour of having each CPU register a pile of registers along the lines=
 of
>
> =A0 =A0{ .name =3D "ID_PFR0", .cp =3D 15, .crn =3D 0, .crm =3D 1, .opc1 =
=3D 0, .opc2 =3D 0,
> =A0 =A0 =A0.access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0x0=
0001231 },
> =A0 =A0{ .name =3D "ID_PFR1", .cp =3D 15, .crn =3D 0, .crm =3D 1, .opc1 =
=3D 0, .opc2 =3D 1,
> =A0 =A0 =A0.access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0x0=
0000011 },
> etc.
>
> I'm not sure there's any need to retain the CPUState (or equivalent) fiel=
ds
> for them at that point.
>
> -- PMM
>
Peter, with the reserved bits in most registers it might make sense to
have resetvalue in two
masks -- ones and zeros, so that you can prevent changing of those bits.

Alex.