From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756011AbbDOPs3 (ORCPT ); Wed, 15 Apr 2015 11:48:29 -0400 Received: from mail-lb0-f169.google.com ([209.85.217.169]:36188 "EHLO mail-lb0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756062AbbDOPsK (ORCPT ); Wed, 15 Apr 2015 11:48:10 -0400 MIME-Version: 1.0 In-Reply-To: References: <1427825817-26773-1-git-send-email-s.hauer@pengutronix.de> <20150414100810.GH4946@pengutronix.de> <20150414115702.GX9742@pengutronix.de> Date: Wed, 15 Apr 2015 17:48:08 +0200 Message-ID: Subject: Re: [PATCH v11]: clk: Add common clock support for Mediatek MT8135 and MT8173 From: Matthias Brugger To: Sascha Hauer Cc: Mike Turquette , Stephen Boyd , YH Chen , "linux-kernel@vger.kernel.org" , Henry Chen , linux-mediatek@lists.infradead.org, "=Sascha Hauer" , Yingjoe Chen , Eddie Huang , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset=ISO-8859-1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2015-04-15 17:11 GMT+02:00 Matthias Brugger : > 2015-04-14 13:57 GMT+02:00 Sascha Hauer : >> On Tue, Apr 14, 2015 at 01:01:30PM +0200, Matthias Brugger wrote: >>> Hi Sascha, >>> >>> 2015-04-14 12:08 GMT+02:00 Sascha Hauer : >>> > Hi Matthias, >>> > >>> > On Tue, Apr 07, 2015 at 01:47:58PM +0200, Matthias Brugger wrote: >>> >> Hi Sascha, >>> >> >>> >> >>> >> 2015-03-31 20:16 GMT+02:00 Sascha Hauer : >>> >> > >>> >> > The following changes since commit 9eccca0843205f87c00404b663188b88eb248051: >>> >> > >>> >> > Linux 4.0-rc3 (2015-03-08 16:09:09 -0700) >>> >> > >>> >> > are available in the git repository at: >>> >> > >>> >> > git://git.pengutronix.de/git/imx/linux-2.6.git tags/v4.0-clk-mediatek-v11 >>> >> > >>> >> > for you to fetch changes up to ae9129219143cfdefe8b3a463deb8c5cb8955525: >>> >> > >>> >> > dt-bindings: ARM: Mediatek: Document devicetree bindings for clock/reset controllers (2015-03-31 20:08:46 +0200) >>> >> > >>> >> > ---------------------------------------------------------------- >>> >> > This patchset contains the initial common clock support for Mediatek SoCs. >>> >> > Mediatek SoC's clock architecture comprises of various PLLs, dividers, muxes >>> >> > and clock gates. >>> >> >>> >> I tried the patch set on my mt8135 eval board. I used the dts bindings >>> >> from a former version of this set [1], but it does not boot the board >>> >> (based on v4.0-rc7). >>> >> Do you have any hint, what is happening, or are the bindings wrong? >>> > >>> > I just tried on a v4.0 with >>> > - this series applied >>> > - the dts patch applied (which is still up-to-date) >>> > - multi_v7_defconfig >>> > >>> > And it still works. What do you mean with "does not boot the board"? No >>> > console output? Could you try with earlyprintk? >>> >>> The probelms I see is, that with the clock patches, I'm not able to >>> boot into a initramfs [1]. >>> Whereas if I just comment topckgen and preicfg in the dts, I'm able to >>> get the a serial console of my initramfs [2]. >>> >>> I wonder if you are able to get serial console from the initramfs with >>> the clock patches + dts patch? >> >> So you get kernel messages but no output from initramfs? In this case >> the kernel disables the unused clocks in a late_initcall. The UART >> driver still uses the dummy clock provided in the dtsi, so the real >> UART clk gets disabled in the initcall. Try passing clk_ignore_unused to >> the kernel > > OK, I can boot to the initramfs with this kernel parameter, but it > fails to boot, when I change the uart clock. I suppose that PERI_UART3 > for debug port uart3 should be fine, but it looks like it doesn't > work. > I can see on the mt6589 datasheet that you have a register > PERI_UART_CK_SOURCE_SEL where you can decide if you want a 26 MHz or a > 52 MHz clock for the UART block. > Does this register exists on mt8135? If so, why is it not implemented? I found that PERI_UARTx_CK is connected to axi_sel but should be connected to uart_sel. Like this I'm able to reach to initramfs console, but the baud rate values are screwed up. As uart_sel is at 52 MHz, I suppose we need to change the entries in PERI_UART_CK_SOURCE_SEL. Cheers, Matthias -- motzblog.wordpress.com From mboxrd@z Thu Jan 1 00:00:00 1970 From: Matthias Brugger Subject: Re: [PATCH v11]: clk: Add common clock support for Mediatek MT8135 and MT8173 Date: Wed, 15 Apr 2015 17:48:08 +0200 Message-ID: References: <1427825817-26773-1-git-send-email-s.hauer@pengutronix.de> <20150414100810.GH4946@pengutronix.de> <20150414115702.GX9742@pengutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Sascha Hauer Cc: Mike Turquette , Stephen Boyd , YH Chen , "linux-kernel@vger.kernel.org" , Henry Chen , linux-mediatek@lists.infradead.org, =Sascha Hauer , Yingjoe Chen , Eddie Huang , "linux-arm-kernel@lists.infradead.org" List-Id: linux-mediatek@lists.infradead.org 2015-04-15 17:11 GMT+02:00 Matthias Brugger : > 2015-04-14 13:57 GMT+02:00 Sascha Hauer : >> On Tue, Apr 14, 2015 at 01:01:30PM +0200, Matthias Brugger wrote: >>> Hi Sascha, >>> >>> 2015-04-14 12:08 GMT+02:00 Sascha Hauer : >>> > Hi Matthias, >>> > >>> > On Tue, Apr 07, 2015 at 01:47:58PM +0200, Matthias Brugger wrote: >>> >> Hi Sascha, >>> >> >>> >> >>> >> 2015-03-31 20:16 GMT+02:00 Sascha Hauer : >>> >> > >>> >> > The following changes since commit 9eccca0843205f87c00404b663188b88eb248051: >>> >> > >>> >> > Linux 4.0-rc3 (2015-03-08 16:09:09 -0700) >>> >> > >>> >> > are available in the git repository at: >>> >> > >>> >> > git://git.pengutronix.de/git/imx/linux-2.6.git tags/v4.0-clk-mediatek-v11 >>> >> > >>> >> > for you to fetch changes up to ae9129219143cfdefe8b3a463deb8c5cb8955525: >>> >> > >>> >> > dt-bindings: ARM: Mediatek: Document devicetree bindings for clock/reset controllers (2015-03-31 20:08:46 +0200) >>> >> > >>> >> > ---------------------------------------------------------------- >>> >> > This patchset contains the initial common clock support for Mediatek SoCs. >>> >> > Mediatek SoC's clock architecture comprises of various PLLs, dividers, muxes >>> >> > and clock gates. >>> >> >>> >> I tried the patch set on my mt8135 eval board. I used the dts bindings >>> >> from a former version of this set [1], but it does not boot the board >>> >> (based on v4.0-rc7). >>> >> Do you have any hint, what is happening, or are the bindings wrong? >>> > >>> > I just tried on a v4.0 with >>> > - this series applied >>> > - the dts patch applied (which is still up-to-date) >>> > - multi_v7_defconfig >>> > >>> > And it still works. What do you mean with "does not boot the board"? No >>> > console output? Could you try with earlyprintk? >>> >>> The probelms I see is, that with the clock patches, I'm not able to >>> boot into a initramfs [1]. >>> Whereas if I just comment topckgen and preicfg in the dts, I'm able to >>> get the a serial console of my initramfs [2]. >>> >>> I wonder if you are able to get serial console from the initramfs with >>> the clock patches + dts patch? >> >> So you get kernel messages but no output from initramfs? In this case >> the kernel disables the unused clocks in a late_initcall. The UART >> driver still uses the dummy clock provided in the dtsi, so the real >> UART clk gets disabled in the initcall. Try passing clk_ignore_unused to >> the kernel > > OK, I can boot to the initramfs with this kernel parameter, but it > fails to boot, when I change the uart clock. I suppose that PERI_UART3 > for debug port uart3 should be fine, but it looks like it doesn't > work. > I can see on the mt6589 datasheet that you have a register > PERI_UART_CK_SOURCE_SEL where you can decide if you want a 26 MHz or a > 52 MHz clock for the UART block. > Does this register exists on mt8135? If so, why is it not implemented? I found that PERI_UARTx_CK is connected to axi_sel but should be connected to uart_sel. Like this I'm able to reach to initramfs console, but the baud rate values are screwed up. As uart_sel is at 52 MHz, I suppose we need to change the entries in PERI_UART_CK_SOURCE_SEL. Cheers, Matthias -- motzblog.wordpress.com From mboxrd@z Thu Jan 1 00:00:00 1970 From: matthias.bgg@gmail.com (Matthias Brugger) Date: Wed, 15 Apr 2015 17:48:08 +0200 Subject: [PATCH v11]: clk: Add common clock support for Mediatek MT8135 and MT8173 In-Reply-To: References: <1427825817-26773-1-git-send-email-s.hauer@pengutronix.de> <20150414100810.GH4946@pengutronix.de> <20150414115702.GX9742@pengutronix.de> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org 2015-04-15 17:11 GMT+02:00 Matthias Brugger : > 2015-04-14 13:57 GMT+02:00 Sascha Hauer : >> On Tue, Apr 14, 2015 at 01:01:30PM +0200, Matthias Brugger wrote: >>> Hi Sascha, >>> >>> 2015-04-14 12:08 GMT+02:00 Sascha Hauer : >>> > Hi Matthias, >>> > >>> > On Tue, Apr 07, 2015 at 01:47:58PM +0200, Matthias Brugger wrote: >>> >> Hi Sascha, >>> >> >>> >> >>> >> 2015-03-31 20:16 GMT+02:00 Sascha Hauer : >>> >> > >>> >> > The following changes since commit 9eccca0843205f87c00404b663188b88eb248051: >>> >> > >>> >> > Linux 4.0-rc3 (2015-03-08 16:09:09 -0700) >>> >> > >>> >> > are available in the git repository at: >>> >> > >>> >> > git://git.pengutronix.de/git/imx/linux-2.6.git tags/v4.0-clk-mediatek-v11 >>> >> > >>> >> > for you to fetch changes up to ae9129219143cfdefe8b3a463deb8c5cb8955525: >>> >> > >>> >> > dt-bindings: ARM: Mediatek: Document devicetree bindings for clock/reset controllers (2015-03-31 20:08:46 +0200) >>> >> > >>> >> > ---------------------------------------------------------------- >>> >> > This patchset contains the initial common clock support for Mediatek SoCs. >>> >> > Mediatek SoC's clock architecture comprises of various PLLs, dividers, muxes >>> >> > and clock gates. >>> >> >>> >> I tried the patch set on my mt8135 eval board. I used the dts bindings >>> >> from a former version of this set [1], but it does not boot the board >>> >> (based on v4.0-rc7). >>> >> Do you have any hint, what is happening, or are the bindings wrong? >>> > >>> > I just tried on a v4.0 with >>> > - this series applied >>> > - the dts patch applied (which is still up-to-date) >>> > - multi_v7_defconfig >>> > >>> > And it still works. What do you mean with "does not boot the board"? No >>> > console output? Could you try with earlyprintk? >>> >>> The probelms I see is, that with the clock patches, I'm not able to >>> boot into a initramfs [1]. >>> Whereas if I just comment topckgen and preicfg in the dts, I'm able to >>> get the a serial console of my initramfs [2]. >>> >>> I wonder if you are able to get serial console from the initramfs with >>> the clock patches + dts patch? >> >> So you get kernel messages but no output from initramfs? In this case >> the kernel disables the unused clocks in a late_initcall. The UART >> driver still uses the dummy clock provided in the dtsi, so the real >> UART clk gets disabled in the initcall. Try passing clk_ignore_unused to >> the kernel > > OK, I can boot to the initramfs with this kernel parameter, but it > fails to boot, when I change the uart clock. I suppose that PERI_UART3 > for debug port uart3 should be fine, but it looks like it doesn't > work. > I can see on the mt6589 datasheet that you have a register > PERI_UART_CK_SOURCE_SEL where you can decide if you want a 26 MHz or a > 52 MHz clock for the UART block. > Does this register exists on mt8135? If so, why is it not implemented? I found that PERI_UARTx_CK is connected to axi_sel but should be connected to uart_sel. Like this I'm able to reach to initramfs console, but the baud rate values are screwed up. As uart_sel is at 52 MHz, I suppose we need to change the entries in PERI_UART_CK_SOURCE_SEL. Cheers, Matthias -- motzblog.wordpress.com