On Thu, Mar 2, 2017 at 1:54 PM, Rafa=C5=82 Mi=C5=82ecki <zajec5@gmail.c= om> wrote:

On 02/28/2017 09:31 PM, Jon Mason wrote:

From: Jon Mason <jonmason@broadcom.com>

Add support for the ARM TWD Watchdog to the bcm5301x device tree.=C2=A0 The=
ARM TWD timer allocated the register space for the WDT, so this patch
necessitated shrinking that.=C2=A0 Also, the GIC masks were added for these= .

Signed-off-by: Jon Mason <jonmason@broadcom.com>
---
=C2=A0arch/arm/boot/dts/bcm5301x.dtsi | 15 ++++++++++++---
=C2=A01 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm53= 01x.dtsi
index 4fbb089..3fbc450 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -70,10 +70,19 @@
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 clocks =3D <&periph_clk>;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 };

-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0local-timer@20600 {=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0timer@20600 {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 compatible =3D "arm,cortex-a9-twd-timer";
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0reg =3D <0x20600 0x100>;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0interrupts =3D <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0reg =3D <0x20600 0x20>;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0interrupts =3D <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0IRQ_TYPE_LEVEL_HIGH)>;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0clocks =3D <&periph_clk>;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0};

If you follow my recent e-mail thread:
BCM5301X: GIC: PPI11 is secure or misconfigured (same for PPI13)
you'll see IRQ_TYPE_LEVEL_HIGH type isn't correct. It should be
IRQ_TYPE_EDGE_RISING.

I believe patch switching to IRQ_TYPE_EDGE_RISING should be sent with Cc st= able
for kernels 4.8+.

The same change is needed for "arm,cortex-a9-global-timer".

Would you find time to revise this patch?

I'll do 2 patches.=C2=A0 One to revise this one and one to address t= he issue you've discovered.=C2=A0 Will that be okay for you?

= =C2=A0