From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eugeni Dodonov Subject: Re: [PATCH 03/29] drm/i915: add Haswell DIP controls registers Date: Tue, 17 Apr 2012 09:02:44 -0300 Message-ID: References: <1334347745-11743-1-git-send-email-eugeni.dodonov@intel.com> <1334347745-11743-4-git-send-email-eugeni.dodonov@intel.com> <20120417101238.GE4104@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0927227199==" Return-path: Received: from mail-yw0-f49.google.com (mail-yw0-f49.google.com [209.85.213.49]) by gabe.freedesktop.org (Postfix) with ESMTP id B22789E756 for ; Tue, 17 Apr 2012 05:03:25 -0700 (PDT) Received: by yhjj52 with SMTP id j52so3278132yhj.36 for ; Tue, 17 Apr 2012 05:03:25 -0700 (PDT) In-Reply-To: <20120417101238.GE4104@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org, Eugeni Dodonov List-Id: intel-gfx@lists.freedesktop.org --===============0927227199== Content-Type: multipart/alternative; boundary=20cf304273fed99f9604bddeb953 --20cf304273fed99f9604bddeb953 Content-Type: text/plain; charset=ISO-8859-1 On Tue, Apr 17, 2012 at 07:12, Daniel Vetter wrote: > On Fri, Apr 13, 2012 at 05:08:39PM -0300, Eugeni Dodonov wrote: > > Haswell has different DIP control registers and offsets. > > > > Signed-off-by: Eugeni Dodonov > > I've read a bit through Bspec wrt dip writing and it looks like hsw is > rather differen from previous chips: > - with have a data reg for every type of dip > - the bits in the ctl reg moved around completely > > ... so I guess this patch and the follow-on one are pretty bogus. One > thing I've noticed is that intel_infoframe_index and intel_infoframe_flags > have way too generic names, they're only useful to frob the dip ctl reg on > pre-hsw afaics. I think we should rename them to i9xx_infoframe_ctl_inde > and _flags or something similar. > Yep, I only did the minimally-required stuff to have HDMI output, so the ones willing to use Haswell could have anything on their screen besides 'No Signal' :). But yes, those patches should receive more care for full hdmi and DIP support going forward. -- Eugeni Dodonov --20cf304273fed99f9604bddeb953 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
On Tue, Apr 17, 2012 at 07:12, Daniel Vetter <daniel@ffwll.ch&g= t; wrote:
On Fri, Apr 13, 2012 at 05:08:39PM -0300, Eugeni Dodonov = wrote:
> Haswell has different DIP control registers and offsets.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

I've read a bit through Bspec wrt dip writing and it looks like h= sw is
rather differen from previous chips:
- with have a data reg for every type of dip
- the bits in the ctl reg moved around completely

... so I guess this patch and the follow-on one are pretty bogus. One
thing I've noticed is that intel_infoframe_index and intel_infoframe_fl= ags
have way too generic names, they're only useful to frob the dip ctl reg= on
pre-hsw afaics. I think we should rename them to i9xx_infoframe_ctl_inde and _flags or something similar.

Yep, I= only did the minimally-required stuff to have HDMI output, so the ones wil= ling to use Haswell could have anything on their screen besides 'No Sig= nal' :).

But yes, those patches should receive more care for ful= l hdmi and DIP support going forward.

--
Euge= ni Dodonov
=
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