From mboxrd@z Thu Jan  1 00:00:00 1970
From: ivo <shandivo@gmail.com>
Subject: Re: SATA controller passthrough - option rom
Date: Tue, 10 Jul 2012 21:00:00 +0200
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Can I kindly ask your help to do that? I'm not that skilled :) (actually
I'm not at all)

Here should be the relevant information about the controller mappings:

ivobacco@thebeast:~$ dmesg | grep 00:1f.2
[    2.410721] pci 0000:00:1f.2: [8086:1c02] type 00 class 0x010601
[    2.410775] pci 0000:00:1f.2: reg 10: [io  0xf0b0-0xf0b7]
[    2.410792] pci 0000:00:1f.2: reg 14: [io  0xf0a0-0xf0a3]
[    2.410810] pci 0000:00:1f.2: reg 18: [io  0xf090-0xf097]
[    2.410828] pci 0000:00:1f.2: reg 1c: [io  0xf080-0xf083]
[    2.410845] pci 0000:00:1f.2: reg 20: [io  0xf060-0xf07f]
[    2.410863] pci 0000:00:1f.2: reg 24: [mem 0xf7d06000-0xf7d067ff]
[    2.410980] pci 0000:00:1f.2: PME# supported from D3hot
[    4.032998] ahci 0000:00:1f.2: version 3.0
[    4.048580] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 6 Gbps
0x3f impl SATA mode
[    4.048583] ahci 0000:00:1f.2: flags: 64bit ncq led clo pio slum part
ems apst
[    4.048589] ahci 0000:00:1f.2: setting latency timer to 64

lspci:
00:1f.2 0106: 8086:1c02 (rev 05) (prog-if 01 [AHCI 1.0])
 Subsystem: 1849:1c02
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B- DisINTx+
 Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0
 Interrupt: pin B routed to IRQ 309
Region 0: I/O ports at f0b0 [size=8]
Region 1: I/O ports at f0a0 [size=4]
 Region 2: I/O ports at f090 [size=8]
Region 3: I/O ports at f080 [size=4]
 Region 4: I/O ports at f060 [size=32]
Region 5: Memory at f7d06000 (32-bit, non-prefetchable) [size=2K]
 Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
Address: fee00438  Data: 0000
 Capabilities: [70] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
 Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [a8] SATA HBA v1.0 BAR4 Offset=00000004
 Capabilities: [b0] PCI Advanced Features
AFCap: TP+ FLR+
AFCtrl: FLR-
 AFStatus: TP-
Kernel driver in use: pciback




On Tue, Jul 10, 2012 at 8:17 PM, Kaushik Barde <kaushik.barde@huawei.com>wrote:

> If you can patch-up qemu ACPI (dsdt), & virtual BIOS to use controller
> information..****
>
> ** **
>
> Kaushik C. Barde
> US Software Lab **[image: huawei_logo]******
>
>
>
> ****
>
> ** **
>
> Address: Huawei Technologies Ltd.
> 2330 Central Expressway
> Santa Clara, CA, 95050, USA
> Tel: 408-330-4437
> www.huawei.com
>
> -------------------------------------------------------------------------------------------------------------------------------------
> This e-mail and its attachments contain confidential information from
> HUAWEI, which
> is intended only for the person or entity whose address is listed above.
> Any use of the
> information contained herein in any way (including, but not limited to,
> total or partial
> disclosure, reproduction, or dissemination) by persons other than the
> intended
> recipient(s) is prohibited. If you receive this e-mail in error, please
> notify the sender by
> phone or email immediately and delete it!****
>
> *From:* xen-devel-bounces@lists.xen.org [mailto:
> xen-devel-bounces@lists.xen.org] *On Behalf Of *ivo
> *Sent:* Tuesday, July 10, 2012 10:32 AM
> *To:* xen-devel@lists.xen.org
> *Subject:* [Xen-devel] SATA controller passthrough - option rom****
>
> ** **
>
> I'm using xen-unstable, and I've successfully made a passthrough of an
> intel storage controller to an HVM domU, binding with pciback.****
>
> ** **
>
> 00:1f.2 SATA controller: Intel Corporation 6 Series/C200 Series Chipset
> Family SATA AHCI Controller (rev 05)****
>
> ** **
>
> I can access the array from within Windows by installing Intel Rapide
> Storage Drivers, and everything works as it should.****
>
> I only have a small problem, I would like to boot the guest OS directly
> from the controller, but of course since there's no "option rom" loaded in
> the qemu bios, it doesn't work, because the boot manager can't access the
> array without drivers loaded.****
>
> ** **
>
> I was wondering, is there any way to let qemu load the option rom of the
> controller so I can boot from it? ****
>
> Is there any other storage controller which the option rom get
> "passthroughed" too? I hope I've been clear enough.****
>
> ** **
>
> Thanks, Ivo****
>

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Can I kindly ask your help to do that? I&#39;m not that skilled :) (actuall=
y I&#39;m not at all)<div><br></div><div>Here should be the relevant inform=
ation about the controller mappings:</div><div><br></div><div><div>ivobacco=
@thebeast:~$ dmesg | grep 00:1f.2</div>

<div>[ =A0 =A02.410721] pci 0000:00:1f.2: [8086:1c02] type 00 class 0x01060=
1</div><div>[ =A0 =A02.410775] pci 0000:00:1f.2: reg 10: [io =A00xf0b0-0xf0=
b7]</div><div>[ =A0 =A02.410792] pci 0000:00:1f.2: reg 14: [io =A00xf0a0-0x=
f0a3]</div>
<div>
[ =A0 =A02.410810] pci 0000:00:1f.2: reg 18: [io =A00xf090-0xf097]</div><di=
v>[ =A0 =A02.410828] pci 0000:00:1f.2: reg 1c: [io =A00xf080-0xf083]</div><=
div>[ =A0 =A02.410845] pci 0000:00:1f.2: reg 20: [io =A00xf060-0xf07f]</div=
><div>[ =A0 =A02.410863] pci 0000:00:1f.2: reg 24: [mem 0xf7d06000-0xf7d067=
ff]</div>

<div>[ =A0 =A02.410980] pci 0000:00:1f.2: PME# supported from D3hot</div><d=
iv>[ =A0 =A04.032998] ahci 0000:00:1f.2: version 3.0</div><div>[ =A0 =A04.0=
48580] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3f impl =
SATA mode</div>

<div>[ =A0 =A04.048583] ahci 0000:00:1f.2: flags: 64bit ncq led clo pio slu=
m part ems apst=A0</div><div>[ =A0 =A04.048589] ahci 0000:00:1f.2: setting =
latency timer to 64</div><div><div><br></div><div>lspci:</div><div>00:1f.2 =
0106: 8086:1c02 (rev 05) (prog-if 01 [AHCI 1.0])</div>

<div><span class=3D"Apple-tab-span" style=3D"white-space:pre">	</span>Subsy=
stem: 1849:1c02</div><div><span class=3D"Apple-tab-span" style=3D"white-spa=
ce:pre">	</span>Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-=
 ParErr- Stepping- SERR- FastB2B- DisINTx+</div>

<div><span class=3D"Apple-tab-span" style=3D"white-space:pre">	</span>Statu=
s: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=3Dmedium &gt;TAbort- &lt;TAbort=
- &lt;MAbort- &gt;SERR- &lt;PERR- INTx-</div><div><span class=3D"Apple-tab-=
span" style=3D"white-space:pre">	</span>Latency: 0</div>

<div><span class=3D"Apple-tab-span" style=3D"white-space:pre">	</span>Inter=
rupt: pin B routed to IRQ 309</div><div><span class=3D"Apple-tab-span" styl=
e=3D"white-space:pre">	</span>Region 0: I/O ports at f0b0 [size=3D8]</div><=
div><span class=3D"Apple-tab-span" style=3D"white-space:pre">	</span>Region=
 1: I/O ports at f0a0 [size=3D4]</div>

<div><span class=3D"Apple-tab-span" style=3D"white-space:pre">	</span>Regio=
n 2: I/O ports at f090 [size=3D8]</div><div><span class=3D"Apple-tab-span" =
style=3D"white-space:pre">	</span>Region 3: I/O ports at f080 [size=3D4]</d=
iv><div>

<span class=3D"Apple-tab-span" style=3D"white-space:pre">	</span>Region 4: =
I/O ports at f060 [size=3D32]</div><div><span class=3D"Apple-tab-span" styl=
e=3D"white-space:pre">	</span>Region 5: Memory at f7d06000 (32-bit, non-pre=
fetchable) [size=3D2K]</div>

<div><span class=3D"Apple-tab-span" style=3D"white-space:pre">	</span>Capab=
ilities: [80] MSI: Enable+ Count=3D1/1 Maskable- 64bit-</div><div><span cla=
ss=3D"Apple-tab-span" style=3D"white-space:pre">		</span>Address: fee00438 =
=A0Data: 0000</div>

<div><span class=3D"Apple-tab-span" style=3D"white-space:pre">	</span>Capab=
ilities: [70] Power Management version 3</div><div><span class=3D"Apple-tab=
-span" style=3D"white-space:pre">		</span>Flags: PMEClk- DSI- D1- D2- AuxCu=
rrent=3D0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)</div>

<div><span class=3D"Apple-tab-span" style=3D"white-space:pre">		</span>Stat=
us: D0 NoSoftRst+ PME-Enable- DSel=3D0 DScale=3D0 PME-</div><div><span clas=
s=3D"Apple-tab-span" style=3D"white-space:pre">	</span>Capabilities: [a8] S=
ATA HBA v1.0 BAR4 Offset=3D00000004</div>

<div><span class=3D"Apple-tab-span" style=3D"white-space:pre">	</span>Capab=
ilities: [b0] PCI Advanced Features</div><div><span class=3D"Apple-tab-span=
" style=3D"white-space:pre">		</span>AFCap: TP+ FLR+</div><div><span class=
=3D"Apple-tab-span" style=3D"white-space:pre">		</span>AFCtrl: FLR-</div>

<div><span class=3D"Apple-tab-span" style=3D"white-space:pre">		</span>AFSt=
atus: TP-</div><div><span class=3D"Apple-tab-span" style=3D"white-space:pre=
">	</span>Kernel driver in use: pciback</div></div><div><br></div><div><br>=
</div>

<div style=3D"font-size:medium"><br></div><br><div class=3D"gmail_quote">On=
 Tue, Jul 10, 2012 at 8:17 PM, Kaushik Barde <span dir=3D"ltr">&lt;<a href=
=3D"mailto:kaushik.barde@huawei.com" target=3D"_blank">kaushik.barde@huawei=
.com</a>&gt;</span> wrote:<br>

<blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1p=
x #ccc solid;padding-left:1ex"><div lang=3D"EN-US" link=3D"blue" vlink=3D"p=
urple"><div><p class=3D"MsoNormal"><span style=3D"font-size:10.0pt;font-fam=
ily:&quot;Verdana&quot;,&quot;sans-serif&quot;;color:blue">If you can patch=
-up qemu ACPI (dsdt), &amp; virtual BIOS to use controller information..<u>=
</u><u></u></span></p>

<p class=3D"MsoNormal"><span style=3D"font-size:10.0pt;font-family:&quot;Ve=
rdana&quot;,&quot;sans-serif&quot;;color:blue"><u></u>=A0<u></u></span></p>=
<p class=3D"MsoNormal"><span style=3D"font-size:10.0pt;font-family:&quot;Ar=
ial&quot;,&quot;sans-serif&quot;">Kaushik C. Barde<br>

</span><span style=3D"font-size:10.0pt;font-family:&quot;Arial&quot;,&quot;=
sans-serif&quot;;color:gray">US Software Lab </span><u></u><img width=3D"10=
2" height=3D"32" src=3D"cid:image001.jpg@01CD5E8D.9D96FC50" align=3D"left" =
alt=3D"huawei_logo"><u></u><span style=3D"color:blue"><u></u><u></u></span>=
</p>

<p class=3D"MsoNormal"><span style=3D"color:blue"><br><br></span><span styl=
e=3D"font-size:7.5pt;font-family:&quot;Arial&quot;,&quot;sans-serif&quot;;c=
olor:gray"><u></u><u></u></span></p><p class=3D"MsoNormal"><span style=3D"f=
ont-size:7.5pt;font-family:&quot;Arial&quot;,&quot;sans-serif&quot;;color:g=
ray"><u></u>=A0<u></u></span></p>

<p class=3D"MsoNormal"><span style=3D"font-size:7.5pt;font-family:&quot;Ari=
al&quot;,&quot;sans-serif&quot;;color:gray">Address: Huawei Technologies Lt=
d.<br>2330 Central Expressway<br>Santa Clara, CA, 95050, USA<br>Tel: 408-33=
0-4437<br>

<a href=3D"http://www.huawei.com" target=3D"_blank">www.huawei.com</a><br>-=
---------------------------------------------------------------------------=
---------------------------------------------------------<br>This e-mail an=
d its attachments contain confidential information from HUAWEI, which <br>

is intended only for the person or entity whose address is listed above. An=
y use of the <br>information contained herein in any way (including, but no=
t limited to, total or partial <br>disclosure, reproduction, or disseminati=
on) by persons other than the intended <br>

recipient(s) is prohibited. If you receive this e-mail in error, please not=
ify the sender by <br>phone or email immediately and delete it!</span><span=
 style=3D"font-size:10.0pt;font-family:&quot;Verdana&quot;,&quot;sans-serif=
&quot;;color:blue"><u></u><u></u></span></p>

<div style=3D"border:none;border-top:solid #b5c4df 1.0pt;padding:3.0pt 0in =
0in 0in"><p class=3D"MsoNormal"><b><span style=3D"font-size:10.0pt;font-fam=
ily:&quot;Tahoma&quot;,&quot;sans-serif&quot;">From:</span></b><span style=
=3D"font-size:10.0pt;font-family:&quot;Tahoma&quot;,&quot;sans-serif&quot;"=
> <a href=3D"mailto:xen-devel-bounces@lists.xen.org" target=3D"_blank">xen-=
devel-bounces@lists.xen.org</a> [mailto:<a href=3D"mailto:xen-devel-bounces=
@lists.xen.org" target=3D"_blank">xen-devel-bounces@lists.xen.org</a>] <b>O=
n Behalf Of </b>ivo<br>

<b>Sent:</b> Tuesday, July 10, 2012 10:32 AM<br><b>To:</b> <a href=3D"mailt=
o:xen-devel@lists.xen.org" target=3D"_blank">xen-devel@lists.xen.org</a><br=
><b>Subject:</b> [Xen-devel] SATA controller passthrough - option rom<u></u=
><u></u></span></p>

</div><div><div class=3D"h5"><p class=3D"MsoNormal"><u></u>=A0<u></u></p><d=
iv><p class=3D"MsoNormal">I&#39;m using xen-unstable, and I&#39;ve successf=
ully made a passthrough of an intel storage controller to an HVM domU, bind=
ing with pciback.<u></u><u></u></p>

</div><div><p class=3D"MsoNormal"><u></u>=A0<u></u></p></div><div><p class=
=3D"MsoNormal">00:1f.2 SATA controller: Intel Corporation 6 Series/C200 Ser=
ies Chipset Family SATA AHCI Controller (rev 05)<u></u><u></u></p></div><di=
v>
<p class=3D"MsoNormal">
<u></u>=A0<u></u></p></div><div><p class=3D"MsoNormal">I can access the arr=
ay from within Windows by installing Intel Rapide Storage Drivers, and ever=
ything works as it should.<u></u><u></u></p></div><div><p class=3D"MsoNorma=
l">

I only have a small problem, I would like to boot the guest OS directly fro=
m the controller, but of course since there&#39;s no &quot;option rom&quot;=
 loaded in the qemu bios, it doesn&#39;t work, because the boot manager can=
&#39;t access the array without drivers loaded.<u></u><u></u></p>

</div><div><p class=3D"MsoNormal"><u></u>=A0<u></u></p></div><div><p class=
=3D"MsoNormal">I was wondering, is there any way to let qemu load the optio=
n rom of the controller so I can boot from it?=A0<u></u><u></u></p></div><d=
iv><p class=3D"MsoNormal">

Is there any other storage controller which the option rom get &quot;passth=
roughed&quot; too? I hope I&#39;ve been clear enough.<u></u><u></u></p></di=
v><div><p class=3D"MsoNormal"><u></u>=A0<u></u></p></div><div><p class=3D"M=
soNormal">

Thanks, Ivo<u></u><u></u></p></div></div></div></div></div></blockquote></d=
iv><br></div>

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