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Tue, 05 Apr 2022 20:31:45 -0700 (PDT) MIME-Version: 1.0 References: <20220321055429.10260-1-jasowang@redhat.com> <20220321055429.10260-5-jasowang@redhat.com> In-Reply-To: From: Jason Wang Date: Wed, 6 Apr 2022 11:31:34 +0800 Message-ID: Subject: Re: [PATCH V2 4/4] intel-iommu: PASID support To: "Tian, Kevin" Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=jasowang@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=170.10.129.124; envelope-from=jasowang@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Liu, Yi L" , "yi.y.sun@linux.intel.com" , "qemu-devel@nongnu.org" , "peterx@redhat.com" , "mst@redhat.com" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sat, Apr 2, 2022 at 3:24 PM Tian, Kevin wrote: > > > From: Jason Wang > > Sent: Wednesday, March 30, 2022 4:32 PM > > > > On Wed, Mar 30, 2022 at 4:02 PM Tian, Kevin wrote: > > > > > > > From: Jason Wang > > > > Sent: Tuesday, March 29, 2022 12:49 PM > > > > > > > > On Mon, Mar 28, 2022 at 3:03 PM Tian, Kevin > > wrote: > > > > > > > > > > > From: Jason Wang > > > > > > Sent: Monday, March 21, 2022 1:54 PM > > > > > > > > > > > > + /* > > > > > > + * vtd-spec v3.4 3.14: > > > > > > + * > > > > > > + * """ > > > > > > + * Requests-with-PASID with input address in range 0xFEEx_xxxx > > are > > > > > > + * translated normally like any other request-with-PASID through > > > > > > + * DMA-remapping hardware. However, if such a request is > > processed > > > > > > + * using pass-through translation, it will be blocked as described > > > > > > + * in the paragraph below. > > > > > > > > > > While PASID+PT is blocked as described in the below paragraph, the > > > > > paragraph itself applies to all situations: > > > > > > > > > > 1) PT + noPASID > > > > > 2) translation + noPASID > > > > > 3) PT + PASID > > > > > 4) translation + PASID > > > > > > > > > > because... > > > > > > > > > > > + * > > > > > > + * Software must not program paging-structure entries to remap > > any > > > > > > + * address to the interrupt address range. Untranslated requests > > > > > > + * and translation requests that result in an address in the > > > > > > + * interrupt range will be blocked with condition code LGN.4 or > > > > > > + * SGN.8. > > > > > > > > > > ... if you look at the definition of LGN.4 or SGN.8: > > > > > > > > > > LGN.4: When legacy mode (RTADDR_REG.TTM=00b) is enabled, > > hardware > > > > > detected an output address (i.e. address after remapping) in the > > > > > interrupt address range (0xFEEx_xxxx). For Translated requests and > > > > > requests with pass-through translation type (TT=10), the output > > > > > address is the same as the address in the request > > > > > > > > > > The last sentence in the first paragraph above just highlights the fact > > that > > > > > when input address of PT is in interrupt range then it is blocked by > > LGN.4 > > > > > or SGN.8 due to output address also in interrupt range. > > > > > > > > > > > + * """ > > > > > > + * > > > > > > + * We enable per as memory region (iommu_ir_fault) for catching > > > > > > + * the tranlsation for interrupt range through PASID + PT. > > > > > > + */ > > > > > > + if (pt && as->pasid != PCI_NO_PASID) { > > > > > > + memory_region_set_enabled(&as->iommu_ir_fault, true); > > > > > > + } else { > > > > > > + memory_region_set_enabled(&as->iommu_ir_fault, false); > > > > > > + } > > > > > > + > > > > > > > > > > Given above this should be a bug fix for nopasid first and then apply it > > > > > to pasid path too. > > > > > > > > Actually, nopasid path patches were posted here. > > > > > > > > https://www.mail-archive.com/qemu- > > devel@nongnu.org/msg867878.html > > > > > > > > Thanks > > > > > > > > > > Can you elaborate why they are handled differently? > > > > It's because that patch is for the case where pasid mode is not > > implemented. We might need it for -stable. > > > > So will that patch be replaced after this one goes in? That path will be merged first if I understand correctly. Then this patch could be applied on top. > By any means > the new iommu_ir_fault region could be applied to both nopasid > and pasid i.e. no need toggle it when address space is switched. Actually it's needed only when PT is enabled. When PT is disabled, the translation is done via iommu_translate. Considering the previous patch will be merged, I will fix this !PT in the next version. Thanks > > Thanks > Kevin