From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FE0BC432C0 for ; Thu, 21 Nov 2019 16:06:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0E96620637 for ; Thu, 21 Nov 2019 16:06:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="VZ1qDEao" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726803AbfKUQG0 (ORCPT ); Thu, 21 Nov 2019 11:06:26 -0500 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:53809 "EHLO us-smtp-delivery-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726541AbfKUQG0 (ORCPT ); Thu, 21 Nov 2019 11:06:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1574352384; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2bUmJw5NVvVVplfFLTrj0DWj0K1ssd2HaG6I0BvVfDc=; b=VZ1qDEaodViSDGiu4IZVwLGVcllu2AfAZB+V93m01oQXuRKKKIf2VDrTdABtnRkWNqFO2B D8xfusEjXTUE5auPvNxoZlwXR7N+LwtnYivg3K/SkoeYmrjRwv8ZNB+FqyjkawrHliZiu6 q4RgSxsRs4U9LXzkPoYo79eZP6/utUc= Received: from mail-qt1-f198.google.com (mail-qt1-f198.google.com [209.85.160.198]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-304-ALnY89q1P2yoRVFqlkTrbg-1; Thu, 21 Nov 2019 11:06:23 -0500 Received: by mail-qt1-f198.google.com with SMTP id v92so2557796qtd.18 for ; Thu, 21 Nov 2019 08:06:23 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=4u5SaUcnCKvjh6UsP+VC2r3Fd3UTQ4sI8vEm9p9IspQ=; b=PQHEAlOiZcELUCpNACov6bpr0NEc+uMIZEqiFgSqOultVB0fSz7uylsBodf+v7AA+J Zgnzu7ZdlIb232m9ij6L11mirVzPr+25TcgjynXc0hpcUF7NjuAlKwQQzB8algImZxBP uEqlK8gEr03LQGANWpq2F0JHkABNMCuBqhcD5po2tKQBbT3g7od8afIr/Rj7ZYoO993/ L5daACdhETk+XUlT4WEwtK+m0qVapei4Ud2YBv61rZXX8GeJHQEhRYH/fxIiffydOvca DPgTT3RHNu1wWDw+PhBKRCB9CsIsAdZhl8vJ09mHLsUq4OQILvY9XPUe93UsRo/RD/AC O7wg== X-Gm-Message-State: APjAAAXN7gRXbDhREYXNZK8am9yROY//RMqPnI6S7uS7xL2K7xAt0Oal j/WuiiX/HaCAFbuJXW1aZ7bMHI78ySH2peKBiYQCPqZIIr6cq8JAgDN+10wGZpJp4/r0IH5C4gB Xv3XmMk2fh6aQ3WUSpgmVy3RHq2M+kko3QOODQJWw X-Received: by 2002:ac8:73c6:: with SMTP id v6mr9366599qtp.137.1574352381603; Thu, 21 Nov 2019 08:06:21 -0800 (PST) X-Google-Smtp-Source: APXvYqyMWsnX6Oq8sVu9TbpGunjITLNboA1N6sHCOJjdw/pIhaC+MKSuuxVJFGx9BLlu7cQMJ12GJrcBaxUzBIiQcN8= X-Received: by 2002:ac8:73c6:: with SMTP id v6mr9366479qtp.137.1574352380570; Thu, 21 Nov 2019 08:06:20 -0800 (PST) MIME-Version: 1.0 References: <20191120120913.GE11621@lahna.fi.intel.com> <20191120151542.GH11621@lahna.fi.intel.com> <20191120155301.GL11621@lahna.fi.intel.com> <20191121112821.GU11621@lahna.fi.intel.com> <20191121114610.GW11621@lahna.fi.intel.com> In-Reply-To: From: Karol Herbst Date: Thu, 21 Nov 2019 17:06:09 +0100 Message-ID: Subject: Re: [PATCH v4] pci: prevent putting nvidia GPUs into lower device states on certain intel bridges To: "Rafael J. Wysocki" Cc: Mika Westerberg , Bjorn Helgaas , LKML , Lyude Paul , "Rafael J . Wysocki" , Linux PCI , Linux PM , dri-devel , nouveau , Dave Airlie , Mario Limonciello X-MC-Unique: ALnY89q1P2yoRVFqlkTrbg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 21, 2019 at 4:47 PM Rafael J. Wysocki wrote= : > > On Thu, Nov 21, 2019 at 1:53 PM Karol Herbst wrote: > > > > On Thu, Nov 21, 2019 at 12:46 PM Mika Westerberg > > wrote: > > > > > > On Thu, Nov 21, 2019 at 12:34:22PM +0100, Rafael J. Wysocki wrote: > > > > On Thu, Nov 21, 2019 at 12:28 PM Mika Westerberg > > > > wrote: > > > > > > > > > > On Wed, Nov 20, 2019 at 11:29:33PM +0100, Rafael J. Wysocki wrote= : > > > > > > > last week or so I found systems where the GPU was under the "= PCI > > > > > > > Express Root Port" (name from lspci) and on those systems all= of that > > > > > > > seems to work. So I am wondering if it's indeed just the 0x19= 01 one, > > > > > > > which also explains Mikas case that Thunderbolt stuff works a= s devices > > > > > > > never get populated under this particular bridge controller, = but under > > > > > > > those "Root Port"s > > > > > > > > > > > > It always is a PCIe port, but its location within the SoC may m= atter. > > > > > > > > > > Exactly. Intel hardware has PCIe ports on CPU side (these are cal= led > > > > > PEG, PCI Express Graphics, ports), and the PCH side. I think the = IP is > > > > > still the same. > > > > > > > > > yeah, I meant the bridge controller with the ID 0x1901 is on the CPU > > side. And if the Nvidia GPU is on a port on the PCH side it all seems > > to work just fine. > > But that may involve different AML too, may it not? > > > > > > > Also some custom AML-based power management is involved and tha= t may > > > > > > be making specific assumptions on the configuration of the SoC = and the > > > > > > GPU at the time of its invocation which unfortunately are not k= nown to > > > > > > us. > > > > > > > > > > > > However, it looks like the AML invoked to power down the GPU fr= om > > > > > > acpi_pci_set_power_state() gets confused if it is not in PCI D0= at > > > > > > that point, so it looks like that AML tries to access device me= mory on > > > > > > the GPU (beyond the PCI config space) or similar which is not > > > > > > accessible in PCI power states below D0. > > > > > > > > > > Or the PCI config space of the GPU when the parent root port is i= n D3hot > > > > > (as it is the case here). Also then the GPU config space is not > > > > > accessible. > > > > > > > > Why would the parent port be in D3hot at that point? Wouldn't that= be > > > > a suspend ordering violation? > > > > > > No. We put the GPU into D3hot first, then the root port and then turn > > > off the power resource (which is attached to the root port) resulting > > > the topology entering D3cold. > > > > > > > If the kernel does a D0 -> D3hot -> D0 cycle this works as well, but > > the power savings are way lower, so I kind of prefer skipping D3hot > > instead of D3cold. Skipping D3hot doesn't seem to make any difference > > in power savings in my testing. > > OK > > What exactly did you do to skip D3cold in your testing? > For that I poked into the PCI registers directly and skipped doing the ACPI calls and simply checked for the idle power consumption on my laptop. But I guess I should retest with calling pci_d3cold_disable from nouveau instead? Or is there a different preferable way of testing this? From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7E1BC432C3 for ; Thu, 21 Nov 2019 16:06:30 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 89F2A206D7 for ; Thu, 21 Nov 2019 16:06:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 89F2A206D7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ECD696F477; Thu, 21 Nov 2019 16:06:29 +0000 (UTC) Received: from us-smtp-delivery-1.mimecast.com (us-smtp-2.mimecast.com [205.139.110.61]) by gabe.freedesktop.org (Postfix) with ESMTPS id 801196F40A for ; Thu, 21 Nov 2019 16:06:28 +0000 (UTC) Received: from mail-qv1-f71.google.com (mail-qv1-f71.google.com [209.85.219.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-204-NaynWFZBNB-_JbEo9h7ZmQ-1; Thu, 21 Nov 2019 11:06:22 -0500 Received: by mail-qv1-f71.google.com with SMTP id w2so2595449qvz.10 for ; Thu, 21 Nov 2019 08:06:22 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=4u5SaUcnCKvjh6UsP+VC2r3Fd3UTQ4sI8vEm9p9IspQ=; b=AQqe5NRVAIb6GiauVJzK7etQJ+y8x0RHi07NVA+hWQfnG5ST8ZYv22aEdbCDDPGZ7M PwEtk8m32G6wynZxrt7OXxvmOz0uB32uaEyi3W5Tv/MA//yWsd3AJqsW+qeXoOPf08df OlvlsxoFzu8iTQWp9mUQUZ0ikyhIn/fHi6GHhJlbzdMhi7fQiWDjnxlWKFibZn/XcpL6 VoW3zn4XXTTddqoUbQjQ1hliCWxc3vTGNfKghBi05P4mn4R2Yqw+625RWa4uC5d5ywCh CYEclp+A/pmrUeVQNg9Ms1R30p7csMQzNAAZoEBUr5j/pFUu2jXGT6mWVK1kTvv/usRG aDZw== X-Gm-Message-State: APjAAAVwWT5lDJKi/zGP68zV5zg5G5gxdmlhYpMJhCnvGJJSUrYo3E4s 3w0/Wxyky0bammDcu3vciIq0O+Ft3c7+H3yLmPnBqLYIDPpFwczyqYNJQemjLYYE2zA030AD7IC zIEXTI3nAnw/O0mXhp49Gczx9DNoj2Mlbd9QfyZq78Zdr X-Received: by 2002:ac8:73c6:: with SMTP id v6mr9366594qtp.137.1574352381580; Thu, 21 Nov 2019 08:06:21 -0800 (PST) X-Google-Smtp-Source: APXvYqyMWsnX6Oq8sVu9TbpGunjITLNboA1N6sHCOJjdw/pIhaC+MKSuuxVJFGx9BLlu7cQMJ12GJrcBaxUzBIiQcN8= X-Received: by 2002:ac8:73c6:: with SMTP id v6mr9366479qtp.137.1574352380570; Thu, 21 Nov 2019 08:06:20 -0800 (PST) MIME-Version: 1.0 References: <20191120120913.GE11621@lahna.fi.intel.com> <20191120151542.GH11621@lahna.fi.intel.com> <20191120155301.GL11621@lahna.fi.intel.com> <20191121112821.GU11621@lahna.fi.intel.com> <20191121114610.GW11621@lahna.fi.intel.com> In-Reply-To: From: Karol Herbst Date: Thu, 21 Nov 2019 17:06:09 +0100 Message-ID: Subject: Re: [PATCH v4] pci: prevent putting nvidia GPUs into lower device states on certain intel bridges To: "Rafael J. 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Wysocki" , LKML , dri-devel , Bjorn Helgaas , nouveau Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Message-ID: <20191121160609.aOm-mgGRduNq5eYMwA-w0tVit6z6ZqStnd3osmdDUmg@z> T24gVGh1LCBOb3YgMjEsIDIwMTkgYXQgNDo0NyBQTSBSYWZhZWwgSi4gV3lzb2NraSA8cmFmYWVs QGtlcm5lbC5vcmc+IHdyb3RlOgo+Cj4gT24gVGh1LCBOb3YgMjEsIDIwMTkgYXQgMTo1MyBQTSBL YXJvbCBIZXJic3QgPGtoZXJic3RAcmVkaGF0LmNvbT4gd3JvdGU6Cj4gPgo+ID4gT24gVGh1LCBO b3YgMjEsIDIwMTkgYXQgMTI6NDYgUE0gTWlrYSBXZXN0ZXJiZXJnCj4gPiA8bWlrYS53ZXN0ZXJi ZXJnQGludGVsLmNvbT4gd3JvdGU6Cj4gPiA+Cj4gPiA+IE9uIFRodSwgTm92IDIxLCAyMDE5IGF0 IDEyOjM0OjIyUE0gKzAxMDAsIFJhZmFlbCBKLiBXeXNvY2tpIHdyb3RlOgo+ID4gPiA+IE9uIFRo dSwgTm92IDIxLCAyMDE5IGF0IDEyOjI4IFBNIE1pa2EgV2VzdGVyYmVyZwo+ID4gPiA+IDxtaWth Lndlc3RlcmJlcmdAaW50ZWwuY29tPiB3cm90ZToKPiA+ID4gPiA+Cj4gPiA+ID4gPiBPbiBXZWQs IE5vdiAyMCwgMjAxOSBhdCAxMToyOTozM1BNICswMTAwLCBSYWZhZWwgSi4gV3lzb2NraSB3cm90 ZToKPiA+ID4gPiA+ID4gPiBsYXN0IHdlZWsgb3Igc28gSSBmb3VuZCBzeXN0ZW1zIHdoZXJlIHRo ZSBHUFUgd2FzIHVuZGVyIHRoZSAiUENJCj4gPiA+ID4gPiA+ID4gRXhwcmVzcyBSb290IFBvcnQi IChuYW1lIGZyb20gbHNwY2kpIGFuZCBvbiB0aG9zZSBzeXN0ZW1zIGFsbCBvZiB0aGF0Cj4gPiA+ ID4gPiA+ID4gc2VlbXMgdG8gd29yay4gU28gSSBhbSB3b25kZXJpbmcgaWYgaXQncyBpbmRlZWQg anVzdCB0aGUgMHgxOTAxIG9uZSwKPiA+ID4gPiA+ID4gPiB3aGljaCBhbHNvIGV4cGxhaW5zIE1p a2FzIGNhc2UgdGhhdCBUaHVuZGVyYm9sdCBzdHVmZiB3b3JrcyBhcyBkZXZpY2VzCj4gPiA+ID4g PiA+ID4gbmV2ZXIgZ2V0IHBvcHVsYXRlZCB1bmRlciB0aGlzIHBhcnRpY3VsYXIgYnJpZGdlIGNv bnRyb2xsZXIsIGJ1dCB1bmRlcgo+ID4gPiA+ID4gPiA+IHRob3NlICJSb290IFBvcnQicwo+ID4g PiA+ID4gPgo+ID4gPiA+ID4gPiBJdCBhbHdheXMgaXMgYSBQQ0llIHBvcnQsIGJ1dCBpdHMgbG9j YXRpb24gd2l0aGluIHRoZSBTb0MgbWF5IG1hdHRlci4KPiA+ID4gPiA+Cj4gPiA+ID4gPiBFeGFj dGx5LiBJbnRlbCBoYXJkd2FyZSBoYXMgUENJZSBwb3J0cyBvbiBDUFUgc2lkZSAodGhlc2UgYXJl IGNhbGxlZAo+ID4gPiA+ID4gUEVHLCBQQ0kgRXhwcmVzcyBHcmFwaGljcywgcG9ydHMpLCBhbmQg dGhlIFBDSCBzaWRlLiBJIHRoaW5rIHRoZSBJUCBpcwo+ID4gPiA+ID4gc3RpbGwgdGhlIHNhbWUu Cj4gPiA+ID4gPgo+ID4KPiA+IHllYWgsIEkgbWVhbnQgdGhlIGJyaWRnZSBjb250cm9sbGVyIHdp dGggdGhlIElEIDB4MTkwMSBpcyBvbiB0aGUgQ1BVCj4gPiBzaWRlLiBBbmQgaWYgdGhlIE52aWRp YSBHUFUgaXMgb24gYSBwb3J0IG9uIHRoZSBQQ0ggc2lkZSBpdCBhbGwgc2VlbXMKPiA+IHRvIHdv cmsganVzdCBmaW5lLgo+Cj4gQnV0IHRoYXQgbWF5IGludm9sdmUgZGlmZmVyZW50IEFNTCB0b28s IG1heSBpdCBub3Q/Cj4KPiA+ID4gPiA+ID4gQWxzbyBzb21lIGN1c3RvbSBBTUwtYmFzZWQgcG93 ZXIgbWFuYWdlbWVudCBpcyBpbnZvbHZlZCBhbmQgdGhhdCBtYXkKPiA+ID4gPiA+ID4gYmUgbWFr aW5nIHNwZWNpZmljIGFzc3VtcHRpb25zIG9uIHRoZSBjb25maWd1cmF0aW9uIG9mIHRoZSBTb0Mg YW5kIHRoZQo+ID4gPiA+ID4gPiBHUFUgYXQgdGhlIHRpbWUgb2YgaXRzIGludm9jYXRpb24gd2hp Y2ggdW5mb3J0dW5hdGVseSBhcmUgbm90IGtub3duIHRvCj4gPiA+ID4gPiA+IHVzLgo+ID4gPiA+ ID4gPgo+ID4gPiA+ID4gPiBIb3dldmVyLCBpdCBsb29rcyBsaWtlIHRoZSBBTUwgaW52b2tlZCB0 byBwb3dlciBkb3duIHRoZSBHUFUgZnJvbQo+ID4gPiA+ID4gPiBhY3BpX3BjaV9zZXRfcG93ZXJf c3RhdGUoKSBnZXRzIGNvbmZ1c2VkIGlmIGl0IGlzIG5vdCBpbiBQQ0kgRDAgYXQKPiA+ID4gPiA+ ID4gdGhhdCBwb2ludCwgc28gaXQgbG9va3MgbGlrZSB0aGF0IEFNTCB0cmllcyB0byBhY2Nlc3Mg ZGV2aWNlIG1lbW9yeSBvbgo+ID4gPiA+ID4gPiB0aGUgR1BVIChiZXlvbmQgdGhlIFBDSSBjb25m aWcgc3BhY2UpIG9yIHNpbWlsYXIgd2hpY2ggaXMgbm90Cj4gPiA+ID4gPiA+IGFjY2Vzc2libGUg aW4gUENJIHBvd2VyIHN0YXRlcyBiZWxvdyBEMC4KPiA+ID4gPiA+Cj4gPiA+ID4gPiBPciB0aGUg UENJIGNvbmZpZyBzcGFjZSBvZiB0aGUgR1BVIHdoZW4gdGhlIHBhcmVudCByb290IHBvcnQgaXMg aW4gRDNob3QKPiA+ID4gPiA+IChhcyBpdCBpcyB0aGUgY2FzZSBoZXJlKS4gQWxzbyB0aGVuIHRo ZSBHUFUgY29uZmlnIHNwYWNlIGlzIG5vdAo+ID4gPiA+ID4gYWNjZXNzaWJsZS4KPiA+ID4gPgo+ ID4gPiA+IFdoeSB3b3VsZCB0aGUgcGFyZW50IHBvcnQgYmUgaW4gRDNob3QgYXQgdGhhdCBwb2lu dD8gIFdvdWxkbid0IHRoYXQgYmUKPiA+ID4gPiBhIHN1c3BlbmQgb3JkZXJpbmcgdmlvbGF0aW9u Pwo+ID4gPgo+ID4gPiBOby4gV2UgcHV0IHRoZSBHUFUgaW50byBEM2hvdCBmaXJzdCwgdGhlbiB0 aGUgcm9vdCBwb3J0IGFuZCB0aGVuIHR1cm4KPiA+ID4gb2ZmIHRoZSBwb3dlciByZXNvdXJjZSAo d2hpY2ggaXMgYXR0YWNoZWQgdG8gdGhlIHJvb3QgcG9ydCkgcmVzdWx0aW5nCj4gPiA+IHRoZSB0 b3BvbG9neSBlbnRlcmluZyBEM2NvbGQuCj4gPiA+Cj4gPgo+ID4gSWYgdGhlIGtlcm5lbCBkb2Vz IGEgRDAgLT4gRDNob3QgLT4gRDAgY3ljbGUgdGhpcyB3b3JrcyBhcyB3ZWxsLCBidXQKPiA+IHRo ZSBwb3dlciBzYXZpbmdzIGFyZSB3YXkgbG93ZXIsIHNvIEkga2luZCBvZiBwcmVmZXIgc2tpcHBp bmcgRDNob3QKPiA+IGluc3RlYWQgb2YgRDNjb2xkLiBTa2lwcGluZyBEM2hvdCBkb2Vzbid0IHNl ZW0gdG8gbWFrZSBhbnkgZGlmZmVyZW5jZQo+ID4gaW4gcG93ZXIgc2F2aW5ncyBpbiBteSB0ZXN0 aW5nLgo+Cj4gT0sKPgo+IFdoYXQgZXhhY3RseSBkaWQgeW91IGRvIHRvIHNraXAgRDNjb2xkIGlu IHlvdXIgdGVzdGluZz8KPgoKRm9yIHRoYXQgSSBwb2tlZCBpbnRvIHRoZSBQQ0kgcmVnaXN0ZXJz IGRpcmVjdGx5IGFuZCBza2lwcGVkIGRvaW5nIHRoZQpBQ1BJIGNhbGxzIGFuZCBzaW1wbHkgY2hl Y2tlZCBmb3IgdGhlIGlkbGUgcG93ZXIgY29uc3VtcHRpb24gb24gbXkKbGFwdG9wLiBCdXQgSSBn dWVzcyBJIHNob3VsZCByZXRlc3Qgd2l0aCBjYWxsaW5nIHBjaV9kM2NvbGRfZGlzYWJsZQpmcm9t IG5vdXZlYXUgaW5zdGVhZD8gT3IgaXMgdGhlcmUgYSBkaWZmZXJlbnQgcHJlZmVyYWJsZSB3YXkg b2YKdGVzdGluZyB0aGlzPwoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0 b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJp LWRldmVs