From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 979F9C761A6 for ; Thu, 30 Mar 2023 11:29:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4tLcgAeG5EQVa7FLvKb5NH/iGANFHP6FFkGWiTubX7k=; b=nOwcxPY0/Pyf4C TVKJ06DYWZTZi36588Q2l8eCLuy7kfS81iO0kK6q1HLLiknRK+xuVG97xx7SI71ee4fDOu9NlYZ89 ah2OLr6HJce+gjGpMsHECALkHrac0VVKLTd7ZyRAmLCr9fwCR63sJOn4YRrjmNa1aGccojGzoTceM oSkWJycph1ECMQfbzH/+39tD3oR5IcbS1KKCX5nkRww7qxgjj8tyUt5R5Raxy1ZnJG6ACYqHFirli 2if4HC1AcsYMt4L+PTSTLeq/uqFnqfqJW81brbWd2pUvcQYeCyPvE2cvC0NZ/tMY/oj8n36WIrZ2U S7mqJNRg4PsJlstZcetQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1phqSS-003bxv-0a; Thu, 30 Mar 2023 11:28:44 +0000 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1phqSO-003bwl-1N for linux-arm-kernel@lists.infradead.org; Thu, 30 Mar 2023 11:28:42 +0000 Received: by mail-ed1-x536.google.com with SMTP id cn12so75129144edb.4 for ; Thu, 30 Mar 2023 04:28:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jms.id.au; s=google; t=1680175716; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=LfXTazrIqQOqSoCNtuJBv5FpzZaZI28AUZo3y4hwU4w=; b=lHcaIW4cUy//H8HVZfexBBueP8HsEigTuxQgwE1y46Urb1rTHqQhP+jNj4q9mqMB8q CuLQt+E5iXZ4EIiU0d3WudQHWX/1Sft41IkAGmnpaveAPDjB+a4DXErVjyH6D4kfot/C n4XuurOXpn8bC3gWLrnSKJSLnHPqL943Gm4II= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680175716; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=LfXTazrIqQOqSoCNtuJBv5FpzZaZI28AUZo3y4hwU4w=; b=YwcpcDQNsUCSQH2EGoF8HX5csCtzM5hjXP1LM7lOBS/WJhN12UHZoAaiCNg0RWBiAC DyPEAOUe5578n2h9t/TCREQyZCWSZFAF+NWoHNFXYUY0mPH+O74dWCgqeV+pmfQb/bF2 oW0xN6BYm4yI7VVIX6VuRjdD/O7Ab/g0adQ6UsJHTRzz6Vf7cT1iu5ku4jTLSozjtPFK cFPodkJJJ1owy88MpYincc87meawHY8O/TPT29aGcRLQeEl9rKsvi0E0RY8AcInpeKbh x4dPgz2zTiWWsHNDLz7FdfsA9CsYsNrO35DiKC6HWMDJkRuYcMwwLbkcB+MNXwzsw/d4 fhOg== X-Gm-Message-State: AAQBX9dHpAZe4CBm61ZiAUrpoGnu0nOeOs6PorAlXOOM7v59g6+dY2ds 7W5e21oSTVFvYbQah+lsM0Do3X+qTSFHCHTBm1FTluWS X-Google-Smtp-Source: AKy350ZB+tUWxGR/yhCFs0d4NJivH/V76VVah8UvW7Z2BgCqltUswQLqdcIFnq0vXyAVXCUQ1alc/KO5PAfs/Xz/2Go= X-Received: by 2002:a50:cd47:0:b0:4fc:532e:215d with SMTP id d7-20020a50cd47000000b004fc532e215dmr11580695edj.6.1680175716145; Thu, 30 Mar 2023 04:28:36 -0700 (PDT) MIME-Version: 1.0 References: <20230327121317.4081816-1-arnd@kernel.org> <20230327121317.4081816-19-arnd@kernel.org> In-Reply-To: <20230327121317.4081816-19-arnd@kernel.org> From: Joel Stanley Date: Thu, 30 Mar 2023 11:28:23 +0000 Message-ID: Subject: Re: [PATCH 18/21] ARM: drop SMP support for ARM11MPCore To: Arnd Bergmann Cc: linux-arm-kernel@lists.infradead.org, Andrew Jeffery X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230330_042840_468218_06BC5BC6 X-CRM114-Status: GOOD ( 40.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 27 Mar 2023 at 12:18, Arnd Bergmann wrote: > Take the easy way out here and drop support for multiprocessing on > ARMv6, along with the CONFIG_DMA_CACHE_RWFO option and the cache > management implementation for it. This also helps with other ARMv6 > issues, but for the moment leaves the ability to build a kernel that > can run on both ARMv7 SMP and single-processor ARMv6, which we probably > want to stop supporting as well, but not as part of this series. Why's that? I currently build a kernel for the ast2600 (dual core cortex a7) and ast2500 (arm1176). Cheers, Joel > > Cc: Neil Armstrong > Cc: Daniel Golle > Cc: Linus Walleij > Cc: linux-oxnas@groups.io > Signed-off-by: Arnd Bergmann > --- > I could use some help clarifying the above changelog text to describe > the exact problem, and how the CONFIG_DMA_CACHE_RWFO actually works on > MPCore. The TRMs for both 1176 and 11MPCore only describe prefetching > into the instruction cache, not the data cache, but this can end up in > the outercache as a result. The 1176 has some extra control bits to > control prefetching, but I found no reference that explains why an > MPCore does not run into the problem. > --- > arch/arm/mach-oxnas/Kconfig | 4 - > arch/arm/mach-oxnas/Makefile | 1 - > arch/arm/mach-oxnas/headsmp.S | 23 ------ > arch/arm/mach-oxnas/platsmp.c | 96 ---------------------- > arch/arm/mach-versatile/platsmp-realview.c | 4 - > arch/arm/mm/Kconfig | 19 ----- > arch/arm/mm/cache-v6.S | 31 ------- > 7 files changed, 178 deletions(-) > delete mode 100644 arch/arm/mach-oxnas/headsmp.S > delete mode 100644 arch/arm/mach-oxnas/platsmp.c > > diff --git a/arch/arm/mach-oxnas/Kconfig b/arch/arm/mach-oxnas/Kconfig > index a9ded7079268..a054235c3d6c 100644 > --- a/arch/arm/mach-oxnas/Kconfig > +++ b/arch/arm/mach-oxnas/Kconfig > @@ -28,10 +28,6 @@ config MACH_OX820 > bool "Support OX820 Based Products" > depends on ARCH_MULTI_V6 > select ARM_GIC > - select DMA_CACHE_RWFO if SMP > - select HAVE_SMP > - select HAVE_ARM_SCU if SMP > - select HAVE_ARM_TWD if SMP > help > Include Support for the Oxford Semiconductor OX820 SoC Based Products. > > diff --git a/arch/arm/mach-oxnas/Makefile b/arch/arm/mach-oxnas/Makefile > index 0e78ecfe6c49..a4e40e534e6a 100644 > --- a/arch/arm/mach-oxnas/Makefile > +++ b/arch/arm/mach-oxnas/Makefile > @@ -1,2 +1 @@ > # SPDX-License-Identifier: GPL-2.0-only > -obj-$(CONFIG_SMP) += platsmp.o headsmp.o > diff --git a/arch/arm/mach-oxnas/headsmp.S b/arch/arm/mach-oxnas/headsmp.S > deleted file mode 100644 > index 9c0f1479f33a..000000000000 > --- a/arch/arm/mach-oxnas/headsmp.S > +++ /dev/null > @@ -1,23 +0,0 @@ > -/* SPDX-License-Identifier: GPL-2.0-only */ > -/* > - * Copyright (C) 2013 Ma Haijun > - * Copyright (c) 2003 ARM Limited > - * All Rights Reserved > - */ > -#include > -#include > - > - __INIT > - > -/* > - * OX820 specific entry point for secondary CPUs. > - */ > -ENTRY(ox820_secondary_startup) > - mov r4, #0 > - /* invalidate both caches and branch target cache */ > - mcr p15, 0, r4, c7, c7, 0 > - /* > - * we've been released from the holding pen: secondary_stack > - * should now contain the SVC stack for this core > - */ > - b secondary_startup > diff --git a/arch/arm/mach-oxnas/platsmp.c b/arch/arm/mach-oxnas/platsmp.c > deleted file mode 100644 > index f0a50b9e61df..000000000000 > --- a/arch/arm/mach-oxnas/platsmp.c > +++ /dev/null > @@ -1,96 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0-only > -/* > - * Copyright (C) 2016 Neil Armstrong > - * Copyright (C) 2013 Ma Haijun > - * Copyright (C) 2002 ARM Ltd. > - * All Rights Reserved > - */ > -#include > -#include > -#include > -#include > - > -#include > -#include > -#include > -#include > - > -extern void ox820_secondary_startup(void); > - > -static void __iomem *cpu_ctrl; > -static void __iomem *gic_cpu_ctrl; > - > -#define HOLDINGPEN_CPU_OFFSET 0xc8 > -#define HOLDINGPEN_LOCATION_OFFSET 0xc4 > - > -#define GIC_NCPU_OFFSET(cpu) (0x100 + (cpu)*0x100) > -#define GIC_CPU_CTRL 0x00 > -#define GIC_CPU_CTRL_ENABLE 1 > - > -static int __init ox820_boot_secondary(unsigned int cpu, > - struct task_struct *idle) > -{ > - /* > - * Write the address of secondary startup into the > - * system-wide flags register. The BootMonitor waits > - * until it receives a soft interrupt, and then the > - * secondary CPU branches to this address. > - */ > - writel(virt_to_phys(ox820_secondary_startup), > - cpu_ctrl + HOLDINGPEN_LOCATION_OFFSET); > - > - writel(cpu, cpu_ctrl + HOLDINGPEN_CPU_OFFSET); > - > - /* > - * Enable GIC cpu interface in CPU Interface Control Register > - */ > - writel(GIC_CPU_CTRL_ENABLE, > - gic_cpu_ctrl + GIC_NCPU_OFFSET(cpu) + GIC_CPU_CTRL); > - > - /* > - * Send the secondary CPU a soft interrupt, thereby causing > - * the boot monitor to read the system wide flags register, > - * and branch to the address found there. > - */ > - arch_send_wakeup_ipi_mask(cpumask_of(cpu)); > - > - return 0; > -} > - > -static void __init ox820_smp_prepare_cpus(unsigned int max_cpus) > -{ > - struct device_node *np; > - void __iomem *scu_base; > - > - np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-scu"); > - scu_base = of_iomap(np, 0); > - of_node_put(np); > - if (!scu_base) > - return; > - > - /* Remap CPU Interrupt Interface Registers */ > - np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-gic"); > - gic_cpu_ctrl = of_iomap(np, 1); > - of_node_put(np); > - if (!gic_cpu_ctrl) > - goto unmap_scu; > - > - np = of_find_compatible_node(NULL, NULL, "oxsemi,ox820-sys-ctrl"); > - cpu_ctrl = of_iomap(np, 0); > - of_node_put(np); > - if (!cpu_ctrl) > - goto unmap_scu; > - > - scu_enable(scu_base); > - flush_cache_all(); > - > -unmap_scu: > - iounmap(scu_base); > -} > - > -static const struct smp_operations ox820_smp_ops __initconst = { > - .smp_prepare_cpus = ox820_smp_prepare_cpus, > - .smp_boot_secondary = ox820_boot_secondary, > -}; > - > -CPU_METHOD_OF_DECLARE(ox820_smp, "oxsemi,ox820-smp", &ox820_smp_ops); > diff --git a/arch/arm/mach-versatile/platsmp-realview.c b/arch/arm/mach-versatile/platsmp-realview.c > index 5d363385c801..fa31fd2d211d 100644 > --- a/arch/arm/mach-versatile/platsmp-realview.c > +++ b/arch/arm/mach-versatile/platsmp-realview.c > @@ -18,16 +18,12 @@ > #define REALVIEW_SYS_FLAGSSET_OFFSET 0x30 > > static const struct of_device_id realview_scu_match[] = { > - { .compatible = "arm,arm11mp-scu", }, > { .compatible = "arm,cortex-a9-scu", }, > { .compatible = "arm,cortex-a5-scu", }, > { } > }; > > static const struct of_device_id realview_syscon_match[] = { > - { .compatible = "arm,core-module-integrator", }, > - { .compatible = "arm,realview-eb-syscon", }, > - { .compatible = "arm,realview-pb11mp-syscon", }, > { .compatible = "arm,realview-pbx-syscon", }, > { }, > }; > diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig > index c5bbae86f725..16b62bc0a970 100644 > --- a/arch/arm/mm/Kconfig > +++ b/arch/arm/mm/Kconfig > @@ -937,25 +937,6 @@ config VDSO > You must have glibc 2.22 or later for programs to seamlessly > take advantage of this. > > -config DMA_CACHE_RWFO > - bool "Enable read/write for ownership DMA cache maintenance" > - depends on CPU_V6K && SMP > - default y > - help > - The Snoop Control Unit on ARM11MPCore does not detect the > - cache maintenance operations and the dma_{map,unmap}_area() > - functions may leave stale cache entries on other CPUs. By > - enabling this option, Read or Write For Ownership in the ARMv6 > - DMA cache maintenance functions is performed. These LDR/STR > - instructions change the cache line state to shared or modified > - so that the cache operation has the desired effect. > - > - Note that the workaround is only valid on processors that do > - not perform speculative loads into the D-cache. For such > - processors, if cache maintenance operations are not broadcast > - in hardware, other workarounds are needed (e.g. cache > - maintenance broadcasting in software via FIQ). > - > config OUTER_CACHE > bool > > diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S > index abae7ff5defc..f6ee53c1de20 100644 > --- a/arch/arm/mm/cache-v6.S > +++ b/arch/arm/mm/cache-v6.S > @@ -201,10 +201,6 @@ ENTRY(v6_flush_kern_dcache_area) > * - end - virtual end address of region > */ > ENTRY(v6_dma_inv_range) > -#ifdef CONFIG_DMA_CACHE_RWFO > - ldrb r2, [r0] @ read for ownership > - strb r2, [r0] @ write for ownership > -#endif > tst r0, #D_CACHE_LINE_SIZE - 1 > bic r0, r0, #D_CACHE_LINE_SIZE - 1 > #ifdef HARVARD_CACHE > @@ -213,10 +209,6 @@ ENTRY(v6_dma_inv_range) > mcrne p15, 0, r0, c7, c11, 1 @ clean unified line > #endif > tst r1, #D_CACHE_LINE_SIZE - 1 > -#ifdef CONFIG_DMA_CACHE_RWFO > - ldrbne r2, [r1, #-1] @ read for ownership > - strbne r2, [r1, #-1] @ write for ownership > -#endif > bic r1, r1, #D_CACHE_LINE_SIZE - 1 > #ifdef HARVARD_CACHE > mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line > @@ -231,10 +223,6 @@ ENTRY(v6_dma_inv_range) > #endif > add r0, r0, #D_CACHE_LINE_SIZE > cmp r0, r1 > -#ifdef CONFIG_DMA_CACHE_RWFO > - ldrlo r2, [r0] @ read for ownership > - strlo r2, [r0] @ write for ownership > -#endif > blo 1b > mov r0, #0 > mcr p15, 0, r0, c7, c10, 4 @ drain write buffer > @@ -248,9 +236,6 @@ ENTRY(v6_dma_inv_range) > ENTRY(v6_dma_clean_range) > bic r0, r0, #D_CACHE_LINE_SIZE - 1 > 1: > -#ifdef CONFIG_DMA_CACHE_RWFO > - ldr r2, [r0] @ read for ownership > -#endif > #ifdef HARVARD_CACHE > mcr p15, 0, r0, c7, c10, 1 @ clean D line > #else > @@ -269,10 +254,6 @@ ENTRY(v6_dma_clean_range) > * - end - virtual end address of region > */ > ENTRY(v6_dma_flush_range) > -#ifdef CONFIG_DMA_CACHE_RWFO > - ldrb r2, [r0] @ read for ownership > - strb r2, [r0] @ write for ownership > -#endif > bic r0, r0, #D_CACHE_LINE_SIZE - 1 > 1: > #ifdef HARVARD_CACHE > @@ -282,10 +263,6 @@ ENTRY(v6_dma_flush_range) > #endif > add r0, r0, #D_CACHE_LINE_SIZE > cmp r0, r1 > -#ifdef CONFIG_DMA_CACHE_RWFO > - ldrblo r2, [r0] @ read for ownership > - strblo r2, [r0] @ write for ownership > -#endif > blo 1b > mov r0, #0 > mcr p15, 0, r0, c7, c10, 4 @ drain write buffer > @@ -301,13 +278,7 @@ ENTRY(v6_dma_map_area) > add r1, r1, r0 > teq r2, #DMA_FROM_DEVICE > beq v6_dma_inv_range > -#ifndef CONFIG_DMA_CACHE_RWFO > b v6_dma_clean_range > -#else > - teq r2, #DMA_TO_DEVICE > - beq v6_dma_clean_range > - b v6_dma_flush_range > -#endif > ENDPROC(v6_dma_map_area) > > /* > @@ -317,11 +288,9 @@ ENDPROC(v6_dma_map_area) > * - dir - DMA direction > */ > ENTRY(v6_dma_unmap_area) > -#ifndef CONFIG_DMA_CACHE_RWFO > add r1, r1, r0 > teq r2, #DMA_TO_DEVICE > bne v6_dma_inv_range > -#endif > ret lr > ENDPROC(v6_dma_unmap_area) > > -- > 2.39.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel