From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752599AbdGCGvw (ORCPT ); Mon, 3 Jul 2017 02:51:52 -0400 Received: from mail-yw0-f175.google.com ([209.85.161.175]:34063 "EHLO mail-yw0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752080AbdGCGvu (ORCPT ); Mon, 3 Jul 2017 02:51:50 -0400 MIME-Version: 1.0 In-Reply-To: <20170607204916.n3wh3fkwbfctdv6s@rob-hp-laptop> References: <20170530060851.29923-1-joel@jms.id.au> <20170530060851.29923-2-joel@jms.id.au> <20170607204916.n3wh3fkwbfctdv6s@rob-hp-laptop> From: Joel Stanley Date: Mon, 3 Jul 2017 16:21:29 +0930 X-Google-Sender-Auth: Q3nTQQQvxMGvLMM_vl0Sqq0QJG0 Message-ID: Subject: Re: [PATCH v2 1/2] dt-bindings: reset: Add bindings for basic reset controller To: Rob Herring Cc: Philipp Zabel , Mark Rutland , devicetree , Linux Kernel Mailing List , Benjamin Herrenschmidt , Andrew Jeffery Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jun 8, 2017 at 6:19 AM, Rob Herring wrote: > On Tue, May 30, 2017 at 03:38:50PM +0930, Joel Stanley wrote: >> This adds the bindings documentation for a basic single-register reset >> controller. >> >> The bindings describe a single 32-bit register that contains up to 32 >> reset lines, each deasserted by clearing the appropriate bit in the >> register. Optionally a property can be provided that changes this >> behaviour to assert on clear. >> > > I think this is a good idea for kernel code, but not for bindings. We > don't really want per register bindings. > > The problem with any generic/simple/basic binding is they always start > that way. Then we add one property at a time not in any well planned > way. I can easily come up with additions. For example, what about > self-clearing reset bits. Or 2 bits per reset. Or multiple resets that > have to be controlled together. 8 or 16-bit registers. Thanks for the explanation. I will send a v3 with aspeed specific bindings. How should I handle the driver? Were you suggesting I keep it generic, but with my aspeed compatible? Cheers, Joel > > IRQs and GPIOs could also be described in some cases with just groups of > 32-bit registers for set,clear,status,mask,etc., but we don't do that in > bindings for the same reasons. > > Rob From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joel Stanley Subject: Re: [PATCH v2 1/2] dt-bindings: reset: Add bindings for basic reset controller Date: Mon, 3 Jul 2017 16:21:29 +0930 Message-ID: References: <20170530060851.29923-1-joel@jms.id.au> <20170530060851.29923-2-joel@jms.id.au> <20170607204916.n3wh3fkwbfctdv6s@rob-hp-laptop> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: <20170607204916.n3wh3fkwbfctdv6s@rob-hp-laptop> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Rob Herring Cc: Philipp Zabel , Mark Rutland , devicetree , Linux Kernel Mailing List , Benjamin Herrenschmidt , Andrew Jeffery List-Id: devicetree@vger.kernel.org On Thu, Jun 8, 2017 at 6:19 AM, Rob Herring wrote: > On Tue, May 30, 2017 at 03:38:50PM +0930, Joel Stanley wrote: >> This adds the bindings documentation for a basic single-register reset >> controller. >> >> The bindings describe a single 32-bit register that contains up to 32 >> reset lines, each deasserted by clearing the appropriate bit in the >> register. Optionally a property can be provided that changes this >> behaviour to assert on clear. >> > > I think this is a good idea for kernel code, but not for bindings. We > don't really want per register bindings. > > The problem with any generic/simple/basic binding is they always start > that way. Then we add one property at a time not in any well planned > way. I can easily come up with additions. For example, what about > self-clearing reset bits. Or 2 bits per reset. Or multiple resets that > have to be controlled together. 8 or 16-bit registers. Thanks for the explanation. I will send a v3 with aspeed specific bindings. How should I handle the driver? Were you suggesting I keep it generic, but with my aspeed compatible? Cheers, Joel > > IRQs and GPIOs could also be described in some cases with just groups of > 32-bit registers for set,clear,status,mask,etc., but we don't do that in > bindings for the same reasons. > > Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html