* [PATCH v5 0/5] Remove LPC register partitioning
@ 2021-01-14 13:16 ` Chia-Wei, Wang
0 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, cyrilbur, haiyue.wang, rlippert
The LPC controller has no concept of the BMC and the Host partitions.
The incorrect partitioning can impose unnecessary range restrictions
on register access through the syscon regmap interface.
For instance, HICRB contains the I/O port address configuration
of KCS channel 1/2. However, the KCS#1/#2 drivers cannot access
HICRB as it is located at the other LPC partition.
In addition, to be backward compatible, the newly added HW control
bits could be located at any reserved bits over the LPC addressing
space.
Thereby, this patch series aims to remove the LPC partitioning for
better driver development and maintenance. This requires the change
to both the device tree and the driver implementation. To ensure
both sides are synchronously updated, a v2 binding check is added.
Chagnes since v4:
- Add child node example in dt-bindings.
Chagnes since v3:
- Revise binding check as suggested by Haiyue Wang.
Changes since v2:
- Add v2 binding check to ensure the synchronization between the
device tree change and the driver register offset fix.
Changes since v1:
- Add the fix to the aspeed-lpc binding documentation.
Chia-Wei, Wang (5):
dt-bindings: aspeed-lpc: Remove LPC partitioning
ARM: dts: Remove LPC BMC and Host partitions
ipmi: kcs: aspeed: Adapt to new LPC DTS layout
pinctrl: aspeed-g5: Adapt to new LPC device tree layout
soc: aspeed: Adapt to new LPC device tree layout
.../devicetree/bindings/mfd/aspeed-lpc.txt | 100 ++++---------
arch/arm/boot/dts/aspeed-g4.dtsi | 74 ++++------
arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++----------
arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++----------
drivers/char/ipmi/kcs_bmc_aspeed.c | 27 ++--
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 ++-
drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++-
drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +--
8 files changed, 229 insertions(+), 302 deletions(-)
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 0/5] Remove LPC register partitioning
@ 2021-01-14 13:16 ` Chia-Wei, Wang
0 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, cyrilbur, haiyue.wang
The LPC controller has no concept of the BMC and the Host partitions.
The incorrect partitioning can impose unnecessary range restrictions
on register access through the syscon regmap interface.
For instance, HICRB contains the I/O port address configuration
of KCS channel 1/2. However, the KCS#1/#2 drivers cannot access
HICRB as it is located at the other LPC partition.
In addition, to be backward compatible, the newly added HW control
bits could be located at any reserved bits over the LPC addressing
space.
Thereby, this patch series aims to remove the LPC partitioning for
better driver development and maintenance. This requires the change
to both the device tree and the driver implementation. To ensure
both sides are synchronously updated, a v2 binding check is added.
Chagnes since v4:
- Add child node example in dt-bindings.
Chagnes since v3:
- Revise binding check as suggested by Haiyue Wang.
Changes since v2:
- Add v2 binding check to ensure the synchronization between the
device tree change and the driver register offset fix.
Changes since v1:
- Add the fix to the aspeed-lpc binding documentation.
Chia-Wei, Wang (5):
dt-bindings: aspeed-lpc: Remove LPC partitioning
ARM: dts: Remove LPC BMC and Host partitions
ipmi: kcs: aspeed: Adapt to new LPC DTS layout
pinctrl: aspeed-g5: Adapt to new LPC device tree layout
soc: aspeed: Adapt to new LPC device tree layout
.../devicetree/bindings/mfd/aspeed-lpc.txt | 100 ++++---------
arch/arm/boot/dts/aspeed-g4.dtsi | 74 ++++------
arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++----------
arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++----------
drivers/char/ipmi/kcs_bmc_aspeed.c | 27 ++--
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 ++-
drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++-
drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +--
8 files changed, 229 insertions(+), 302 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-14 13:16 ` Chia-Wei, Wang
-1 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, haiyue.wang, cyrilbur, rlippert
The LPC controller has no concept of the BMC and the Host partitions.
This patch fixes the documentation by removing the description on LPC
partitions. The register offsets illustrated in the DTS node examples
are also fixed to adapt to the LPC DTS change.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
---
.../devicetree/bindings/mfd/aspeed-lpc.txt | 100 +++++-------------
1 file changed, 25 insertions(+), 75 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
index d0a38ba8b9ce..936aa108eab4 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
@@ -9,13 +9,7 @@ primary use case of the Aspeed LPC controller is as a slave on the bus
conditions it can also take the role of bus master.
The LPC controller is represented as a multi-function device to account for the
-mix of functionality it provides. The principle split is between the register
-layout at the start of the I/O space which is, to quote the Aspeed datasheet,
-"basically compatible with the [LPC registers from the] popular BMC controller
-H8S/2168[1]", and everything else, where everything else is an eclectic
-collection of functions with a esoteric register layout. "Everything else",
-here labeled the "host" portion of the controller, includes, but is not limited
-to:
+mix of functionality, which includes, but is not limited to:
* An IPMI Block Transfer[2] Controller
@@ -44,80 +38,36 @@ Required properties
===================
- compatible: One of:
- "aspeed,ast2400-lpc", "simple-mfd"
- "aspeed,ast2500-lpc", "simple-mfd"
- "aspeed,ast2600-lpc", "simple-mfd"
+ "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
+ "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
+ "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
- reg: contains the physical address and length values of the Aspeed
LPC memory region.
- #address-cells: <1>
- #size-cells: <1>
-- ranges: Maps 0 to the physical address and length of the LPC memory
- region
-
-Required LPC Child nodes
-========================
-
-BMC Node
---------
-
-- compatible: One of:
- "aspeed,ast2400-lpc-bmc"
- "aspeed,ast2500-lpc-bmc"
- "aspeed,ast2600-lpc-bmc"
-
-- reg: contains the physical address and length values of the
- H8S/2168-compatible LPC controller memory region
-
-Host Node
----------
-
-- compatible: One of:
- "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"
- "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"
- "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"
-
-- reg: contains the address and length values of the host-related
- register space for the Aspeed LPC controller
-
-- #address-cells: <1>
-- #size-cells: <1>
-- ranges: Maps 0 to the address and length of the host-related LPC memory
+- ranges: Maps 0 to the physical address and length of the LPC memory
region
Example:
lpc: lpc@1e789000 {
- compatible = "aspeed,ast2500-lpc", "simple-mfd";
+ compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
- lpc_bmc: lpc-bmc@0 {
- compatible = "aspeed,ast2500-lpc-bmc";
+ lpc_snoop: lpc-snoop@0 {
+ compatible = "aspeed,ast2600-lpc-snoop";
reg = <0x0 0x80>;
- };
-
- lpc_host: lpc-host@80 {
- compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
- reg = <0x80 0x1e0>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x80 0x1e0>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ snoop-ports = <0x80>;
};
};
-BMC Node Children
-==================
-
-
-Host Node Children
-==================
LPC Host Interface Controller
-------------------
@@ -149,14 +99,12 @@ Optional properties:
Example:
-lpc-host@80 {
- lpc_ctrl: lpc-ctrl@0 {
- compatible = "aspeed,ast2500-lpc-ctrl";
- reg = <0x0 0x80>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- memory-region = <&flash_memory>;
- flash = <&spi>;
- };
+lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2500-lpc-ctrl";
+ reg = <0x80 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ memory-region = <&flash_memory>;
+ flash = <&spi>;
};
LPC Host Controller
@@ -179,9 +127,9 @@ Required properties:
Example:
-lhc: lhc@20 {
+lhc: lhc@a0 {
compatible = "aspeed,ast2500-lhc";
- reg = <0x20 0x24 0x48 0x8>;
+ reg = <0xa0 0x24 0xc8 0x8>;
};
LPC reset control
@@ -192,16 +140,18 @@ state of the LPC bus. Some systems may chose to modify this configuration.
Required properties:
- - compatible: "aspeed,ast2600-lpc-reset" or
- "aspeed,ast2500-lpc-reset"
- "aspeed,ast2400-lpc-reset"
+ - compatible: One of:
+ "aspeed,ast2600-lpc-reset";
+ "aspeed,ast2500-lpc-reset";
+ "aspeed,ast2400-lpc-reset";
+
- reg: offset and length of the IP in the LHC memory region
- #reset-controller indicates the number of reset cells expected
Example:
-lpc_reset: reset-controller@18 {
+lpc_reset: reset-controller@98 {
compatible = "aspeed,ast2500-lpc-reset";
- reg = <0x18 0x4>;
+ reg = <0x98 0x4>;
#reset-cells = <1>;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-01-14 13:16 ` Chia-Wei, Wang
0 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, cyrilbur, haiyue.wang, rlippert
The LPC controller has no concept of the BMC and the Host partitions.
This patch fixes the documentation by removing the description on LPC
partitions. The register offsets illustrated in the DTS node examples
are also fixed to adapt to the LPC DTS change.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
---
.../devicetree/bindings/mfd/aspeed-lpc.txt | 100 +++++-------------
1 file changed, 25 insertions(+), 75 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
index d0a38ba8b9ce..936aa108eab4 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
@@ -9,13 +9,7 @@ primary use case of the Aspeed LPC controller is as a slave on the bus
conditions it can also take the role of bus master.
The LPC controller is represented as a multi-function device to account for the
-mix of functionality it provides. The principle split is between the register
-layout at the start of the I/O space which is, to quote the Aspeed datasheet,
-"basically compatible with the [LPC registers from the] popular BMC controller
-H8S/2168[1]", and everything else, where everything else is an eclectic
-collection of functions with a esoteric register layout. "Everything else",
-here labeled the "host" portion of the controller, includes, but is not limited
-to:
+mix of functionality, which includes, but is not limited to:
* An IPMI Block Transfer[2] Controller
@@ -44,80 +38,36 @@ Required properties
===================
- compatible: One of:
- "aspeed,ast2400-lpc", "simple-mfd"
- "aspeed,ast2500-lpc", "simple-mfd"
- "aspeed,ast2600-lpc", "simple-mfd"
+ "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
+ "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
+ "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
- reg: contains the physical address and length values of the Aspeed
LPC memory region.
- #address-cells: <1>
- #size-cells: <1>
-- ranges: Maps 0 to the physical address and length of the LPC memory
- region
-
-Required LPC Child nodes
-========================
-
-BMC Node
---------
-
-- compatible: One of:
- "aspeed,ast2400-lpc-bmc"
- "aspeed,ast2500-lpc-bmc"
- "aspeed,ast2600-lpc-bmc"
-
-- reg: contains the physical address and length values of the
- H8S/2168-compatible LPC controller memory region
-
-Host Node
----------
-
-- compatible: One of:
- "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"
- "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"
- "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"
-
-- reg: contains the address and length values of the host-related
- register space for the Aspeed LPC controller
-
-- #address-cells: <1>
-- #size-cells: <1>
-- ranges: Maps 0 to the address and length of the host-related LPC memory
+- ranges: Maps 0 to the physical address and length of the LPC memory
region
Example:
lpc: lpc@1e789000 {
- compatible = "aspeed,ast2500-lpc", "simple-mfd";
+ compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
- lpc_bmc: lpc-bmc@0 {
- compatible = "aspeed,ast2500-lpc-bmc";
+ lpc_snoop: lpc-snoop@0 {
+ compatible = "aspeed,ast2600-lpc-snoop";
reg = <0x0 0x80>;
- };
-
- lpc_host: lpc-host@80 {
- compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
- reg = <0x80 0x1e0>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x80 0x1e0>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ snoop-ports = <0x80>;
};
};
-BMC Node Children
-==================
-
-
-Host Node Children
-==================
LPC Host Interface Controller
-------------------
@@ -149,14 +99,12 @@ Optional properties:
Example:
-lpc-host@80 {
- lpc_ctrl: lpc-ctrl@0 {
- compatible = "aspeed,ast2500-lpc-ctrl";
- reg = <0x0 0x80>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- memory-region = <&flash_memory>;
- flash = <&spi>;
- };
+lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2500-lpc-ctrl";
+ reg = <0x80 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ memory-region = <&flash_memory>;
+ flash = <&spi>;
};
LPC Host Controller
@@ -179,9 +127,9 @@ Required properties:
Example:
-lhc: lhc@20 {
+lhc: lhc@a0 {
compatible = "aspeed,ast2500-lhc";
- reg = <0x20 0x24 0x48 0x8>;
+ reg = <0xa0 0x24 0xc8 0x8>;
};
LPC reset control
@@ -192,16 +140,18 @@ state of the LPC bus. Some systems may chose to modify this configuration.
Required properties:
- - compatible: "aspeed,ast2600-lpc-reset" or
- "aspeed,ast2500-lpc-reset"
- "aspeed,ast2400-lpc-reset"
+ - compatible: One of:
+ "aspeed,ast2600-lpc-reset";
+ "aspeed,ast2500-lpc-reset";
+ "aspeed,ast2400-lpc-reset";
+
- reg: offset and length of the IP in the LHC memory region
- #reset-controller indicates the number of reset cells expected
Example:
-lpc_reset: reset-controller@18 {
+lpc_reset: reset-controller@98 {
compatible = "aspeed,ast2500-lpc-reset";
- reg = <0x18 0x4>;
+ reg = <0x98 0x4>;
#reset-cells = <1>;
};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-01-14 13:16 ` Chia-Wei, Wang
0 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, cyrilbur, haiyue.wang
The LPC controller has no concept of the BMC and the Host partitions.
This patch fixes the documentation by removing the description on LPC
partitions. The register offsets illustrated in the DTS node examples
are also fixed to adapt to the LPC DTS change.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
---
.../devicetree/bindings/mfd/aspeed-lpc.txt | 100 +++++-------------
1 file changed, 25 insertions(+), 75 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
index d0a38ba8b9ce..936aa108eab4 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
@@ -9,13 +9,7 @@ primary use case of the Aspeed LPC controller is as a slave on the bus
conditions it can also take the role of bus master.
The LPC controller is represented as a multi-function device to account for the
-mix of functionality it provides. The principle split is between the register
-layout at the start of the I/O space which is, to quote the Aspeed datasheet,
-"basically compatible with the [LPC registers from the] popular BMC controller
-H8S/2168[1]", and everything else, where everything else is an eclectic
-collection of functions with a esoteric register layout. "Everything else",
-here labeled the "host" portion of the controller, includes, but is not limited
-to:
+mix of functionality, which includes, but is not limited to:
* An IPMI Block Transfer[2] Controller
@@ -44,80 +38,36 @@ Required properties
===================
- compatible: One of:
- "aspeed,ast2400-lpc", "simple-mfd"
- "aspeed,ast2500-lpc", "simple-mfd"
- "aspeed,ast2600-lpc", "simple-mfd"
+ "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
+ "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
+ "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
- reg: contains the physical address and length values of the Aspeed
LPC memory region.
- #address-cells: <1>
- #size-cells: <1>
-- ranges: Maps 0 to the physical address and length of the LPC memory
- region
-
-Required LPC Child nodes
-========================
-
-BMC Node
---------
-
-- compatible: One of:
- "aspeed,ast2400-lpc-bmc"
- "aspeed,ast2500-lpc-bmc"
- "aspeed,ast2600-lpc-bmc"
-
-- reg: contains the physical address and length values of the
- H8S/2168-compatible LPC controller memory region
-
-Host Node
----------
-
-- compatible: One of:
- "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"
- "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"
- "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"
-
-- reg: contains the address and length values of the host-related
- register space for the Aspeed LPC controller
-
-- #address-cells: <1>
-- #size-cells: <1>
-- ranges: Maps 0 to the address and length of the host-related LPC memory
+- ranges: Maps 0 to the physical address and length of the LPC memory
region
Example:
lpc: lpc@1e789000 {
- compatible = "aspeed,ast2500-lpc", "simple-mfd";
+ compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
- lpc_bmc: lpc-bmc@0 {
- compatible = "aspeed,ast2500-lpc-bmc";
+ lpc_snoop: lpc-snoop@0 {
+ compatible = "aspeed,ast2600-lpc-snoop";
reg = <0x0 0x80>;
- };
-
- lpc_host: lpc-host@80 {
- compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
- reg = <0x80 0x1e0>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x80 0x1e0>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ snoop-ports = <0x80>;
};
};
-BMC Node Children
-==================
-
-
-Host Node Children
-==================
LPC Host Interface Controller
-------------------
@@ -149,14 +99,12 @@ Optional properties:
Example:
-lpc-host@80 {
- lpc_ctrl: lpc-ctrl@0 {
- compatible = "aspeed,ast2500-lpc-ctrl";
- reg = <0x0 0x80>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- memory-region = <&flash_memory>;
- flash = <&spi>;
- };
+lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2500-lpc-ctrl";
+ reg = <0x80 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ memory-region = <&flash_memory>;
+ flash = <&spi>;
};
LPC Host Controller
@@ -179,9 +127,9 @@ Required properties:
Example:
-lhc: lhc@20 {
+lhc: lhc@a0 {
compatible = "aspeed,ast2500-lhc";
- reg = <0x20 0x24 0x48 0x8>;
+ reg = <0xa0 0x24 0xc8 0x8>;
};
LPC reset control
@@ -192,16 +140,18 @@ state of the LPC bus. Some systems may chose to modify this configuration.
Required properties:
- - compatible: "aspeed,ast2600-lpc-reset" or
- "aspeed,ast2500-lpc-reset"
- "aspeed,ast2400-lpc-reset"
+ - compatible: One of:
+ "aspeed,ast2600-lpc-reset";
+ "aspeed,ast2500-lpc-reset";
+ "aspeed,ast2400-lpc-reset";
+
- reg: offset and length of the IP in the LHC memory region
- #reset-controller indicates the number of reset cells expected
Example:
-lpc_reset: reset-controller@18 {
+lpc_reset: reset-controller@98 {
compatible = "aspeed,ast2500-lpc-reset";
- reg = <0x18 0x4>;
+ reg = <0x98 0x4>;
#reset-cells = <1>;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-20 4:57 ` Andrew Jeffery
-1 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-20 4:57 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Haiyue Wang, Cyril Bur, Robert Lippert
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> The LPC controller has no concept of the BMC and the Host partitions.
> This patch fixes the documentation by removing the description on LPC
> partitions. The register offsets illustrated in the DTS node examples
> are also fixed to adapt to the LPC DTS change.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-01-20 4:57 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-20 4:57 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang, Robert Lippert
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> The LPC controller has no concept of the BMC and the Host partitions.
> This patch fixes the documentation by removing the description on LPC
> partitions. The register offsets illustrated in the DTS node examples
> are also fixed to adapt to the LPC DTS change.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-01-20 4:57 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-20 4:57 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> The LPC controller has no concept of the BMC and the Host partitions.
> This patch fixes the documentation by removing the description on LPC
> partitions. The register offsets illustrated in the DTS node examples
> are also fixed to adapt to the LPC DTS change.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-25 21:25 ` Rob Herring
-1 siblings, 0 replies; 72+ messages in thread
From: Rob Herring @ 2021-01-25 21:25 UTC (permalink / raw)
To: Chia-Wei, Wang
Cc: linux-arm-kernel, BMC-SW, lee.jones, joel, linux-kernel, andrew,
haiyue.wang, linus.walleij, cyrilbur, linux-aspeed, robh+dt,
devicetree, minyard, rlippert, openbmc
On Thu, 14 Jan 2021 21:16:18 +0800, Chia-Wei, Wang wrote:
> The LPC controller has no concept of the BMC and the Host partitions.
> This patch fixes the documentation by removing the description on LPC
> partitions. The register offsets illustrated in the DTS node examples
> are also fixed to adapt to the LPC DTS change.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 100 +++++-------------
> 1 file changed, 25 insertions(+), 75 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-01-25 21:25 ` Rob Herring
0 siblings, 0 replies; 72+ messages in thread
From: Rob Herring @ 2021-01-25 21:25 UTC (permalink / raw)
To: Chia-Wei, Wang
Cc: BMC-SW, haiyue.wang, minyard, linux-aspeed, devicetree, andrew,
linus.walleij, linux-kernel, openbmc, rlippert, robh+dt, joel,
lee.jones, cyrilbur, linux-arm-kernel
On Thu, 14 Jan 2021 21:16:18 +0800, Chia-Wei, Wang wrote:
> The LPC controller has no concept of the BMC and the Host partitions.
> This patch fixes the documentation by removing the description on LPC
> partitions. The register offsets illustrated in the DTS node examples
> are also fixed to adapt to the LPC DTS change.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 100 +++++-------------
> 1 file changed, 25 insertions(+), 75 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-01-25 21:25 ` Rob Herring
0 siblings, 0 replies; 72+ messages in thread
From: Rob Herring @ 2021-01-25 21:25 UTC (permalink / raw)
To: Chia-Wei, Wang
Cc: BMC-SW, haiyue.wang, minyard, linux-aspeed, devicetree, andrew,
linus.walleij, linux-kernel, openbmc, robh+dt, lee.jones,
cyrilbur, linux-arm-kernel
On Thu, 14 Jan 2021 21:16:18 +0800, Chia-Wei, Wang wrote:
> The LPC controller has no concept of the BMC and the Host partitions.
> This patch fixes the documentation by removing the description on LPC
> partitions. The register offsets illustrated in the DTS node examples
> are also fixed to adapt to the LPC DTS change.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 100 +++++-------------
> 1 file changed, 25 insertions(+), 75 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-27 0:24 ` Andrew Jeffery
-1 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-27 0:24 UTC (permalink / raw)
To: Lee Jones
Cc: BMC-SW, Haiyue Wang, Robert Lippert, Chia-Wei, Wang, Rob Herring,
Joel Stanley, Linus Walleij, Corey Minyard, devicetree,
linux-arm-kernel, linux-aspeed, linux-kernel, openbmc
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> The LPC controller has no concept of the BMC and the Host partitions.
> This patch fixes the documentation by removing the description on LPC
> partitions. The register offsets illustrated in the DTS node examples
> are also fixed to adapt to the LPC DTS change.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Any thoughts Lee? If you ack it would you be happy for the patch to go through
the Aspeed tree?
Andrew
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-01-27 0:24 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-27 0:24 UTC (permalink / raw)
To: Lee Jones
Cc: linux-arm-kernel, BMC-SW, linux-aspeed, Corey Minyard,
Robert Lippert, Chia-Wei, Wang, linux-kernel, openbmc,
devicetree, Rob Herring, Joel Stanley, Linus Walleij,
Haiyue Wang
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> The LPC controller has no concept of the BMC and the Host partitions.
> This patch fixes the documentation by removing the description on LPC
> partitions. The register offsets illustrated in the DTS node examples
> are also fixed to adapt to the LPC DTS change.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Any thoughts Lee? If you ack it would you be happy for the patch to go through
the Aspeed tree?
Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-01-27 0:24 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-27 0:24 UTC (permalink / raw)
To: Lee Jones
Cc: linux-arm-kernel, BMC-SW, linux-aspeed, Corey Minyard, Chia-Wei,
Wang, linux-kernel, openbmc, devicetree, Rob Herring,
Linus Walleij, Haiyue Wang
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> The LPC controller has no concept of the BMC and the Host partitions.
> This patch fixes the documentation by removing the description on LPC
> partitions. The register offsets illustrated in the DTS node examples
> are also fixed to adapt to the LPC DTS change.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Any thoughts Lee? If you ack it would you be happy for the patch to go through
the Aspeed tree?
Andrew
^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
2021-01-27 0:24 ` Andrew Jeffery
(?)
@ 2021-02-17 7:40 ` ChiaWei Wang
-1 siblings, 0 replies; 72+ messages in thread
From: ChiaWei Wang @ 2021-02-17 7:40 UTC (permalink / raw)
To: Andrew Jeffery, Lee Jones
Cc: BMC-SW, Haiyue Wang, Robert Lippert, Rob Herring, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Hi All,
Do you have update on this patch series?
Aspeed has subsequent LPC module upstream plan.
We hope that the following patches can be on the basis of the fixed LPC layout.
Thanks.
Chiawei
> -----Original Message-----
> From: Andrew Jeffery <andrew@aj.id.au>
> Sent: Wednesday, January 27, 2021 8:25 AM
> To: Lee Jones <lee.jones@linaro.org>
> Subject: Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
>
>
>
> On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > The LPC controller has no concept of the BMC and the Host partitions.
> > This patch fixes the documentation by removing the description on LPC
> > partitions. The register offsets illustrated in the DTS node examples
> > are also fixed to adapt to the LPC DTS change.
> >
> > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
>
> Any thoughts Lee? If you ack it would you be happy for the patch to go through
> the Aspeed tree?
>
> Andrew
^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-02-17 7:40 ` ChiaWei Wang
0 siblings, 0 replies; 72+ messages in thread
From: ChiaWei Wang @ 2021-02-17 7:40 UTC (permalink / raw)
To: Andrew Jeffery, Lee Jones
Cc: linux-arm-kernel, BMC-SW, linux-aspeed, Corey Minyard,
Robert Lippert, Linus Walleij, linux-kernel, devicetree,
Rob Herring, Joel Stanley, openbmc, Haiyue Wang
Hi All,
Do you have update on this patch series?
Aspeed has subsequent LPC module upstream plan.
We hope that the following patches can be on the basis of the fixed LPC layout.
Thanks.
Chiawei
> -----Original Message-----
> From: Andrew Jeffery <andrew@aj.id.au>
> Sent: Wednesday, January 27, 2021 8:25 AM
> To: Lee Jones <lee.jones@linaro.org>
> Subject: Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
>
>
>
> On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > The LPC controller has no concept of the BMC and the Host partitions.
> > This patch fixes the documentation by removing the description on LPC
> > partitions. The register offsets illustrated in the DTS node examples
> > are also fixed to adapt to the LPC DTS change.
> >
> > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
>
> Any thoughts Lee? If you ack it would you be happy for the patch to go through
> the Aspeed tree?
>
> Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-02-17 7:40 ` ChiaWei Wang
0 siblings, 0 replies; 72+ messages in thread
From: ChiaWei Wang @ 2021-02-17 7:40 UTC (permalink / raw)
To: Andrew Jeffery, Lee Jones
Cc: linux-arm-kernel, BMC-SW, linux-aspeed, Corey Minyard,
Linus Walleij, linux-kernel, devicetree, Rob Herring, openbmc,
Haiyue Wang
Hi All,
Do you have update on this patch series?
Aspeed has subsequent LPC module upstream plan.
We hope that the following patches can be on the basis of the fixed LPC layout.
Thanks.
Chiawei
> -----Original Message-----
> From: Andrew Jeffery <andrew@aj.id.au>
> Sent: Wednesday, January 27, 2021 8:25 AM
> To: Lee Jones <lee.jones@linaro.org>
> Subject: Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
>
>
>
> On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > The LPC controller has no concept of the BMC and the Host partitions.
> > This patch fixes the documentation by removing the description on LPC
> > partitions. The register offsets illustrated in the DTS node examples
> > are also fixed to adapt to the LPC DTS change.
> >
> > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
>
> Any thoughts Lee? If you ack it would you be happy for the patch to go through
> the Aspeed tree?
>
> Andrew
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
2021-02-17 7:40 ` ChiaWei Wang
(?)
@ 2021-02-17 7:44 ` Joel Stanley
-1 siblings, 0 replies; 72+ messages in thread
From: Joel Stanley @ 2021-02-17 7:44 UTC (permalink / raw)
To: ChiaWei Wang
Cc: Andrew Jeffery, Lee Jones, BMC-SW, Haiyue Wang, Robert Lippert,
Rob Herring, Linus Walleij, Corey Minyard, devicetree,
linux-arm-kernel, linux-aspeed, linux-kernel, openbmc
Hi Chaiwei,
On Wed, 17 Feb 2021 at 07:40, ChiaWei Wang <chiawei_wang@aspeedtech.com> wrote:
>
> Hi All,
>
> Do you have update on this patch series?
> Aspeed has subsequent LPC module upstream plan.
> We hope that the following patches can be on the basis of the fixed LPC layout.
Andrew has expressed his support for your changes. I will take time to
closely review your proposal this week.
We will set the goal of having this rework merged for the next merge window.
Cheers,
Joel
> Thanks.
>
> Chiawei
>
> > -----Original Message-----
> > From: Andrew Jeffery <andrew@aj.id.au>
> > Sent: Wednesday, January 27, 2021 8:25 AM
> > To: Lee Jones <lee.jones@linaro.org>
> > Subject: Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
> >
> >
> >
> > On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > > The LPC controller has no concept of the BMC and the Host partitions.
> > > This patch fixes the documentation by removing the description on LPC
> > > partitions. The register offsets illustrated in the DTS node examples
> > > are also fixed to adapt to the LPC DTS change.
> > >
> > > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> >
> > Any thoughts Lee? If you ack it would you be happy for the patch to go through
> > the Aspeed tree?
> >
> > Andrew
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-02-17 7:44 ` Joel Stanley
0 siblings, 0 replies; 72+ messages in thread
From: Joel Stanley @ 2021-02-17 7:44 UTC (permalink / raw)
To: ChiaWei Wang
Cc: BMC-SW, linux-aspeed, Corey Minyard, Robert Lippert,
Andrew Jeffery, Linus Walleij, linux-kernel, devicetree,
Rob Herring, linux-arm-kernel, Lee Jones, openbmc, Haiyue Wang
Hi Chaiwei,
On Wed, 17 Feb 2021 at 07:40, ChiaWei Wang <chiawei_wang@aspeedtech.com> wrote:
>
> Hi All,
>
> Do you have update on this patch series?
> Aspeed has subsequent LPC module upstream plan.
> We hope that the following patches can be on the basis of the fixed LPC layout.
Andrew has expressed his support for your changes. I will take time to
closely review your proposal this week.
We will set the goal of having this rework merged for the next merge window.
Cheers,
Joel
> Thanks.
>
> Chiawei
>
> > -----Original Message-----
> > From: Andrew Jeffery <andrew@aj.id.au>
> > Sent: Wednesday, January 27, 2021 8:25 AM
> > To: Lee Jones <lee.jones@linaro.org>
> > Subject: Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
> >
> >
> >
> > On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > > The LPC controller has no concept of the BMC and the Host partitions.
> > > This patch fixes the documentation by removing the description on LPC
> > > partitions. The register offsets illustrated in the DTS node examples
> > > are also fixed to adapt to the LPC DTS change.
> > >
> > > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> >
> > Any thoughts Lee? If you ack it would you be happy for the patch to go through
> > the Aspeed tree?
> >
> > Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-02-17 7:44 ` Joel Stanley
0 siblings, 0 replies; 72+ messages in thread
From: Joel Stanley @ 2021-02-17 7:44 UTC (permalink / raw)
To: ChiaWei Wang
Cc: BMC-SW, linux-aspeed, Corey Minyard, Andrew Jeffery,
Linus Walleij, linux-kernel, devicetree, Rob Herring,
linux-arm-kernel, Lee Jones, openbmc, Haiyue Wang
Hi Chaiwei,
On Wed, 17 Feb 2021 at 07:40, ChiaWei Wang <chiawei_wang@aspeedtech.com> wrote:
>
> Hi All,
>
> Do you have update on this patch series?
> Aspeed has subsequent LPC module upstream plan.
> We hope that the following patches can be on the basis of the fixed LPC layout.
Andrew has expressed his support for your changes. I will take time to
closely review your proposal this week.
We will set the goal of having this rework merged for the next merge window.
Cheers,
Joel
> Thanks.
>
> Chiawei
>
> > -----Original Message-----
> > From: Andrew Jeffery <andrew@aj.id.au>
> > Sent: Wednesday, January 27, 2021 8:25 AM
> > To: Lee Jones <lee.jones@linaro.org>
> > Subject: Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
> >
> >
> >
> > On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > > The LPC controller has no concept of the BMC and the Host partitions.
> > > This patch fixes the documentation by removing the description on LPC
> > > partitions. The register offsets illustrated in the DTS node examples
> > > are also fixed to adapt to the LPC DTS change.
> > >
> > > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> >
> > Any thoughts Lee? If you ack it would you be happy for the patch to go through
> > the Aspeed tree?
> >
> > Andrew
^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
2021-02-17 7:44 ` Joel Stanley
(?)
@ 2021-02-17 8:04 ` ChiaWei Wang
-1 siblings, 0 replies; 72+ messages in thread
From: ChiaWei Wang @ 2021-02-17 8:04 UTC (permalink / raw)
To: Joel Stanley
Cc: Andrew Jeffery, Lee Jones, BMC-SW, Haiyue Wang, Robert Lippert,
Rob Herring, Linus Walleij, Corey Minyard, devicetree,
linux-arm-kernel, linux-aspeed, linux-kernel, openbmc
Hi Joel,
Thanks for your feedback.
Really appreciate all your review effort.
Chiawei
> -----Original Message-----
> From: Joel Stanley <joel@jms.id.au>
> Sent: Wednesday, February 17, 2021 3:45 PM
> To: ChiaWei Wang <chiawei_wang@aspeedtech.com>
> Subject: Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
>
> Hi Chaiwei,
>
> On Wed, 17 Feb 2021 at 07:40, ChiaWei Wang
> <chiawei_wang@aspeedtech.com> wrote:
> >
> > Hi All,
> >
> > Do you have update on this patch series?
> > Aspeed has subsequent LPC module upstream plan.
> > We hope that the following patches can be on the basis of the fixed LPC
> layout.
>
> Andrew has expressed his support for your changes. I will take time to closely
> review your proposal this week.
>
> We will set the goal of having this rework merged for the next merge window.
>
> Cheers,
>
> Joel
>
>
> > Thanks.
> >
> > Chiawei
> >
> > > -----Original Message-----
> > > From: Andrew Jeffery <andrew@aj.id.au>
> > > Sent: Wednesday, January 27, 2021 8:25 AM
> > > To: Lee Jones <lee.jones@linaro.org>
> > > Subject: Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC
> > > partitioning
> > >
> > >
> > >
> > > On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > > > The LPC controller has no concept of the BMC and the Host partitions.
> > > > This patch fixes the documentation by removing the description on
> > > > LPC partitions. The register offsets illustrated in the DTS node
> > > > examples are also fixed to adapt to the LPC DTS change.
> > > >
> > > > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> > >
> > > Any thoughts Lee? If you ack it would you be happy for the patch to
> > > go through the Aspeed tree?
> > >
> > > Andrew
^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-02-17 8:04 ` ChiaWei Wang
0 siblings, 0 replies; 72+ messages in thread
From: ChiaWei Wang @ 2021-02-17 8:04 UTC (permalink / raw)
To: Joel Stanley
Cc: BMC-SW, linux-aspeed, Corey Minyard, Robert Lippert,
Andrew Jeffery, Linus Walleij, linux-kernel, devicetree,
Rob Herring, linux-arm-kernel, Lee Jones, openbmc, Haiyue Wang
Hi Joel,
Thanks for your feedback.
Really appreciate all your review effort.
Chiawei
> -----Original Message-----
> From: Joel Stanley <joel@jms.id.au>
> Sent: Wednesday, February 17, 2021 3:45 PM
> To: ChiaWei Wang <chiawei_wang@aspeedtech.com>
> Subject: Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
>
> Hi Chaiwei,
>
> On Wed, 17 Feb 2021 at 07:40, ChiaWei Wang
> <chiawei_wang@aspeedtech.com> wrote:
> >
> > Hi All,
> >
> > Do you have update on this patch series?
> > Aspeed has subsequent LPC module upstream plan.
> > We hope that the following patches can be on the basis of the fixed LPC
> layout.
>
> Andrew has expressed his support for your changes. I will take time to closely
> review your proposal this week.
>
> We will set the goal of having this rework merged for the next merge window.
>
> Cheers,
>
> Joel
>
>
> > Thanks.
> >
> > Chiawei
> >
> > > -----Original Message-----
> > > From: Andrew Jeffery <andrew@aj.id.au>
> > > Sent: Wednesday, January 27, 2021 8:25 AM
> > > To: Lee Jones <lee.jones@linaro.org>
> > > Subject: Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC
> > > partitioning
> > >
> > >
> > >
> > > On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > > > The LPC controller has no concept of the BMC and the Host partitions.
> > > > This patch fixes the documentation by removing the description on
> > > > LPC partitions. The register offsets illustrated in the DTS node
> > > > examples are also fixed to adapt to the LPC DTS change.
> > > >
> > > > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> > >
> > > Any thoughts Lee? If you ack it would you be happy for the patch to
> > > go through the Aspeed tree?
> > >
> > > Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-02-17 8:04 ` ChiaWei Wang
0 siblings, 0 replies; 72+ messages in thread
From: ChiaWei Wang @ 2021-02-17 8:04 UTC (permalink / raw)
To: Joel Stanley
Cc: BMC-SW, linux-aspeed, Corey Minyard, Andrew Jeffery,
Linus Walleij, linux-kernel, devicetree, Rob Herring,
linux-arm-kernel, Lee Jones, openbmc, Haiyue Wang
Hi Joel,
Thanks for your feedback.
Really appreciate all your review effort.
Chiawei
> -----Original Message-----
> From: Joel Stanley <joel@jms.id.au>
> Sent: Wednesday, February 17, 2021 3:45 PM
> To: ChiaWei Wang <chiawei_wang@aspeedtech.com>
> Subject: Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
>
> Hi Chaiwei,
>
> On Wed, 17 Feb 2021 at 07:40, ChiaWei Wang
> <chiawei_wang@aspeedtech.com> wrote:
> >
> > Hi All,
> >
> > Do you have update on this patch series?
> > Aspeed has subsequent LPC module upstream plan.
> > We hope that the following patches can be on the basis of the fixed LPC
> layout.
>
> Andrew has expressed his support for your changes. I will take time to closely
> review your proposal this week.
>
> We will set the goal of having this rework merged for the next merge window.
>
> Cheers,
>
> Joel
>
>
> > Thanks.
> >
> > Chiawei
> >
> > > -----Original Message-----
> > > From: Andrew Jeffery <andrew@aj.id.au>
> > > Sent: Wednesday, January 27, 2021 8:25 AM
> > > To: Lee Jones <lee.jones@linaro.org>
> > > Subject: Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC
> > > partitioning
> > >
> > >
> > >
> > > On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > > > The LPC controller has no concept of the BMC and the Host partitions.
> > > > This patch fixes the documentation by removing the description on
> > > > LPC partitions. The register offsets illustrated in the DTS node
> > > > examples are also fixed to adapt to the LPC DTS change.
> > > >
> > > > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> > >
> > > Any thoughts Lee? If you ack it would you be happy for the patch to
> > > go through the Aspeed tree?
> > >
> > > Andrew
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
2021-02-17 7:44 ` Joel Stanley
(?)
@ 2021-02-17 8:04 ` Andrew Jeffery
-1 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-02-17 8:04 UTC (permalink / raw)
To: Joel Stanley, Chia-Wei, Wang
Cc: BMC-SW, linux-aspeed, Corey Minyard, Robert Lippert,
Linus Walleij, linux-kernel, devicetree, Rob Herring,
linux-arm-kernel, Lee Jones, openbmc, Haiyue Wang
On Wed, 17 Feb 2021, at 18:14, Joel Stanley wrote:
> Hi Chaiwei,
>
> On Wed, 17 Feb 2021 at 07:40, ChiaWei Wang <chiawei_wang@aspeedtech.com> wrote:
> >
> > Hi All,
> >
> > Do you have update on this patch series?
> > Aspeed has subsequent LPC module upstream plan.
> > We hope that the following patches can be on the basis of the fixed LPC layout.
>
> Andrew has expressed his support for your changes. I will take time to
> closely review your proposal this week.
>
> We will set the goal of having this rework merged for the next merge window.
>
FWIW I have a patch series that builds on top of Chiawei's changes. Once
some weather has passed and some power is restored I should be able to test
then send it out.
Andrew
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-02-17 8:04 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-02-17 8:04 UTC (permalink / raw)
To: Joel Stanley, Chia-Wei, Wang
Cc: BMC-SW, linux-aspeed, Corey Minyard, Robert Lippert,
Linus Walleij, linux-kernel, devicetree, Rob Herring,
Haiyue Wang, Lee Jones, openbmc, linux-arm-kernel
On Wed, 17 Feb 2021, at 18:14, Joel Stanley wrote:
> Hi Chaiwei,
>
> On Wed, 17 Feb 2021 at 07:40, ChiaWei Wang <chiawei_wang@aspeedtech.com> wrote:
> >
> > Hi All,
> >
> > Do you have update on this patch series?
> > Aspeed has subsequent LPC module upstream plan.
> > We hope that the following patches can be on the basis of the fixed LPC layout.
>
> Andrew has expressed his support for your changes. I will take time to
> closely review your proposal this week.
>
> We will set the goal of having this rework merged for the next merge window.
>
FWIW I have a patch series that builds on top of Chiawei's changes. Once
some weather has passed and some power is restored I should be able to test
then send it out.
Andrew
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
@ 2021-02-17 8:04 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-02-17 8:04 UTC (permalink / raw)
To: Joel Stanley, Chia-Wei, Wang
Cc: BMC-SW, linux-aspeed, Corey Minyard, Linus Walleij, linux-kernel,
devicetree, Rob Herring, Haiyue Wang, Lee Jones, openbmc,
linux-arm-kernel
On Wed, 17 Feb 2021, at 18:14, Joel Stanley wrote:
> Hi Chaiwei,
>
> On Wed, 17 Feb 2021 at 07:40, ChiaWei Wang <chiawei_wang@aspeedtech.com> wrote:
> >
> > Hi All,
> >
> > Do you have update on this patch series?
> > Aspeed has subsequent LPC module upstream plan.
> > We hope that the following patches can be on the basis of the fixed LPC layout.
>
> Andrew has expressed his support for your changes. I will take time to
> closely review your proposal this week.
>
> We will set the goal of having this rework merged for the next merge window.
>
FWIW I have a patch series that builds on top of Chiawei's changes. Once
some weather has passed and some power is restored I should be able to test
then send it out.
Andrew
^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 2/5] ARM: dts: Remove LPC BMC and Host partitions
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-14 13:16 ` Chia-Wei, Wang
-1 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, haiyue.wang, cyrilbur, rlippert
The LPC controller has no concept of the BMC and the Host partitions.
A concrete instance is that the HICRB[5:4] are for the I/O port address
configurtaion of KCS channel 1/2. However, the KCS driver cannot access
HICRB for channel 1/2 initialization via syscon regmap interface due to
the parition boundary. (i.e. offset 80h)
In addition, for the HW design backward compatibility, a newly added HW
control bit could be located at any reserved one over the LPC addressing
space. Thereby, this patch removes the lpc-bmc and lpc-host child node
and thus the LPC partitioning.
Note that this change requires the synchronization between device tree
change and the driver change. To prevent the misuse of old devicetrees
with new drivers, or vice versa, the v2 compatible strings are adopted
for the LPC device as listed:
"aspeed,ast2400-lpc-v2"
"aspeed,ast2500-lpc-v2"
"aspeed,ast2600-lpc-v2"
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 74 +++++++----------
arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++++++++-----------------
arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++++++++-----------------
3 files changed, 148 insertions(+), 196 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index b3dafbc8caca..ee22bc036440 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -343,58 +343,44 @@
};
lpc: lpc@1e789000 {
- compatible = "aspeed,ast2400-lpc", "simple-mfd";
+ compatible = "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
+ reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
- lpc_bmc: lpc-bmc@0 {
- compatible = "aspeed,ast2400-lpc-bmc";
- reg = <0x0 0x80>;
+ lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2400-lpc-ctrl";
+ reg = <0x80 0x10>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ status = "disabled";
};
- lpc_host: lpc-host@80 {
- compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
- reg = <0x80 0x1e0>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x80 0x1e0>;
-
- lpc_ctrl: lpc-ctrl@0 {
- compatible = "aspeed,ast2400-lpc-ctrl";
- reg = <0x0 0x10>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- status = "disabled";
- };
-
- lpc_snoop: lpc-snoop@10 {
- compatible = "aspeed,ast2400-lpc-snoop";
- reg = <0x10 0x8>;
- interrupts = <8>;
- status = "disabled";
- };
-
- lhc: lhc@20 {
- compatible = "aspeed,ast2400-lhc";
- reg = <0x20 0x24 0x48 0x8>;
- };
-
- lpc_reset: reset-controller@18 {
- compatible = "aspeed,ast2400-lpc-reset";
- reg = <0x18 0x4>;
- #reset-cells = <1>;
- };
-
- ibt: ibt@c0 {
- compatible = "aspeed,ast2400-ibt-bmc";
- reg = <0xc0 0x18>;
- interrupts = <8>;
- status = "disabled";
- };
+ lpc_snoop: lpc-snoop@90 {
+ compatible = "aspeed,ast2400-lpc-snoop";
+ reg = <0x90 0x8>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ lhc: lhc@a0 {
+ compatible = "aspeed,ast2400-lhc";
+ reg = <0xa0 0x24 0xc8 0x8>;
+ };
+
+ lpc_reset: reset-controller@98 {
+ compatible = "aspeed,ast2400-lpc-reset";
+ reg = <0x98 0x4>;
+ #reset-cells = <1>;
+ };
+
+ ibt: ibt@140 {
+ compatible = "aspeed,ast2400-ibt-bmc";
+ reg = <0x140 0x18>;
+ interrupts = <8>;
+ status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 5bc0de0f3365..10ca2100f69b 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -434,90 +434,73 @@
};
lpc: lpc@1e789000 {
- compatible = "aspeed,ast2500-lpc", "simple-mfd";
+ compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
+ reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
- lpc_bmc: lpc-bmc@0 {
- compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon";
- reg = <0x0 0x80>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x80>;
-
- kcs1: kcs@24 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
- interrupts = <8>;
- status = "disabled";
- };
- kcs2: kcs@28 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
- interrupts = <8>;
- status = "disabled";
- };
- kcs3: kcs@2c {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
- interrupts = <8>;
- status = "disabled";
- };
+ kcs1: kcs@24 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ kcs2: kcs@28 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ kcs3: kcs@2c {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ kcs4: kcs@114 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
+ interrupts = <8>;
+ status = "disabled";
};
- lpc_host: lpc-host@80 {
- compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
- reg = <0x80 0x1e0>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x80 0x1e0>;
-
- kcs4: kcs@94 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>;
- interrupts = <8>;
- status = "disabled";
- };
-
- lpc_ctrl: lpc-ctrl@0 {
- compatible = "aspeed,ast2500-lpc-ctrl";
- reg = <0x0 0x10>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- status = "disabled";
- };
-
- lpc_snoop: lpc-snoop@10 {
- compatible = "aspeed,ast2500-lpc-snoop";
- reg = <0x10 0x8>;
- interrupts = <8>;
- status = "disabled";
- };
-
- lpc_reset: reset-controller@18 {
- compatible = "aspeed,ast2500-lpc-reset";
- reg = <0x18 0x4>;
- #reset-cells = <1>;
- };
-
- lhc: lhc@20 {
- compatible = "aspeed,ast2500-lhc";
- reg = <0x20 0x24 0x48 0x8>;
- };
-
-
- ibt: ibt@c0 {
- compatible = "aspeed,ast2500-ibt-bmc";
- reg = <0xc0 0x18>;
- interrupts = <8>;
- status = "disabled";
- };
+ lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2500-lpc-ctrl";
+ reg = <0x80 0x10>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ status = "disabled";
+ };
+
+ lpc_snoop: lpc-snoop@90 {
+ compatible = "aspeed,ast2500-lpc-snoop";
+ reg = <0x90 0x8>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ lpc_reset: reset-controller@98 {
+ compatible = "aspeed,ast2500-lpc-reset";
+ reg = <0x98 0x4>;
+ #reset-cells = <1>;
+ };
+
+ lhc: lhc@a0 {
+ compatible = "aspeed,ast2500-lhc";
+ reg = <0xa0 0x24 0xc8 0x8>;
+ };
+
+
+ ibt: ibt@140 {
+ compatible = "aspeed,ast2500-ibt-bmc";
+ reg = <0x140 0x18>;
+ interrupts = <8>;
+ status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 810b0676ab03..d91f48c3db62 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -460,90 +460,73 @@
};
lpc: lpc@1e789000 {
- compatible = "aspeed,ast2600-lpc", "simple-mfd";
+ compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
+ reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
- lpc_bmc: lpc-bmc@0 {
- compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon";
- reg = <0x0 0x80>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x80>;
-
- kcs1: kcs@24 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- kcs_chan = <1>;
- status = "disabled";
- };
- kcs2: kcs@28 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
- kcs3: kcs@2c {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
+ kcs1: kcs@24 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ kcs_chan = <1>;
+ status = "disabled";
+ };
+
+ kcs2: kcs@28 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ kcs3: kcs@2c {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ kcs4: kcs@114 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2600-lpc-ctrl";
+ reg = <0x80 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ status = "disabled";
+ };
+
+ lpc_snoop: lpc-snoop@80 {
+ compatible = "aspeed,ast2600-lpc-snoop";
+ reg = <0x80 0x80>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
- lpc_host: lpc-host@80 {
- compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon";
- reg = <0x80 0x1e0>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x80 0x1e0>;
-
- kcs4: kcs@94 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- lpc_ctrl: lpc-ctrl@0 {
- compatible = "aspeed,ast2600-lpc-ctrl";
- reg = <0x0 0x80>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- status = "disabled";
- };
-
- lpc_snoop: lpc-snoop@0 {
- compatible = "aspeed,ast2600-lpc-snoop";
- reg = <0x0 0x80>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- lhc: lhc@20 {
- compatible = "aspeed,ast2600-lhc";
- reg = <0x20 0x24 0x48 0x8>;
- };
-
- lpc_reset: reset-controller@18 {
- compatible = "aspeed,ast2600-lpc-reset";
- reg = <0x18 0x4>;
- #reset-cells = <1>;
- };
-
- ibt: ibt@c0 {
- compatible = "aspeed,ast2600-ibt-bmc";
- reg = <0xc0 0x18>;
- interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
+ lhc: lhc@a0 {
+ compatible = "aspeed,ast2600-lhc";
+ reg = <0xa0 0x24 0xc8 0x8>;
+ };
+
+ lpc_reset: reset-controller@98 {
+ compatible = "aspeed,ast2600-lpc-reset";
+ reg = <0x98 0x4>;
+ #reset-cells = <1>;
+ };
+
+ ibt: ibt@140 {
+ compatible = "aspeed,ast2600-ibt-bmc";
+ reg = <0x140 0x18>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
};
--
2.17.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH v5 2/5] ARM: dts: Remove LPC BMC and Host partitions
@ 2021-01-14 13:16 ` Chia-Wei, Wang
0 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, cyrilbur, haiyue.wang, rlippert
The LPC controller has no concept of the BMC and the Host partitions.
A concrete instance is that the HICRB[5:4] are for the I/O port address
configurtaion of KCS channel 1/2. However, the KCS driver cannot access
HICRB for channel 1/2 initialization via syscon regmap interface due to
the parition boundary. (i.e. offset 80h)
In addition, for the HW design backward compatibility, a newly added HW
control bit could be located at any reserved one over the LPC addressing
space. Thereby, this patch removes the lpc-bmc and lpc-host child node
and thus the LPC partitioning.
Note that this change requires the synchronization between device tree
change and the driver change. To prevent the misuse of old devicetrees
with new drivers, or vice versa, the v2 compatible strings are adopted
for the LPC device as listed:
"aspeed,ast2400-lpc-v2"
"aspeed,ast2500-lpc-v2"
"aspeed,ast2600-lpc-v2"
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 74 +++++++----------
arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++++++++-----------------
arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++++++++-----------------
3 files changed, 148 insertions(+), 196 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index b3dafbc8caca..ee22bc036440 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -343,58 +343,44 @@
};
lpc: lpc@1e789000 {
- compatible = "aspeed,ast2400-lpc", "simple-mfd";
+ compatible = "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
+ reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
- lpc_bmc: lpc-bmc@0 {
- compatible = "aspeed,ast2400-lpc-bmc";
- reg = <0x0 0x80>;
+ lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2400-lpc-ctrl";
+ reg = <0x80 0x10>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ status = "disabled";
};
- lpc_host: lpc-host@80 {
- compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
- reg = <0x80 0x1e0>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x80 0x1e0>;
-
- lpc_ctrl: lpc-ctrl@0 {
- compatible = "aspeed,ast2400-lpc-ctrl";
- reg = <0x0 0x10>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- status = "disabled";
- };
-
- lpc_snoop: lpc-snoop@10 {
- compatible = "aspeed,ast2400-lpc-snoop";
- reg = <0x10 0x8>;
- interrupts = <8>;
- status = "disabled";
- };
-
- lhc: lhc@20 {
- compatible = "aspeed,ast2400-lhc";
- reg = <0x20 0x24 0x48 0x8>;
- };
-
- lpc_reset: reset-controller@18 {
- compatible = "aspeed,ast2400-lpc-reset";
- reg = <0x18 0x4>;
- #reset-cells = <1>;
- };
-
- ibt: ibt@c0 {
- compatible = "aspeed,ast2400-ibt-bmc";
- reg = <0xc0 0x18>;
- interrupts = <8>;
- status = "disabled";
- };
+ lpc_snoop: lpc-snoop@90 {
+ compatible = "aspeed,ast2400-lpc-snoop";
+ reg = <0x90 0x8>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ lhc: lhc@a0 {
+ compatible = "aspeed,ast2400-lhc";
+ reg = <0xa0 0x24 0xc8 0x8>;
+ };
+
+ lpc_reset: reset-controller@98 {
+ compatible = "aspeed,ast2400-lpc-reset";
+ reg = <0x98 0x4>;
+ #reset-cells = <1>;
+ };
+
+ ibt: ibt@140 {
+ compatible = "aspeed,ast2400-ibt-bmc";
+ reg = <0x140 0x18>;
+ interrupts = <8>;
+ status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 5bc0de0f3365..10ca2100f69b 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -434,90 +434,73 @@
};
lpc: lpc@1e789000 {
- compatible = "aspeed,ast2500-lpc", "simple-mfd";
+ compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
+ reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
- lpc_bmc: lpc-bmc@0 {
- compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon";
- reg = <0x0 0x80>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x80>;
-
- kcs1: kcs@24 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
- interrupts = <8>;
- status = "disabled";
- };
- kcs2: kcs@28 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
- interrupts = <8>;
- status = "disabled";
- };
- kcs3: kcs@2c {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
- interrupts = <8>;
- status = "disabled";
- };
+ kcs1: kcs@24 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ kcs2: kcs@28 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ kcs3: kcs@2c {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ kcs4: kcs@114 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
+ interrupts = <8>;
+ status = "disabled";
};
- lpc_host: lpc-host@80 {
- compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
- reg = <0x80 0x1e0>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x80 0x1e0>;
-
- kcs4: kcs@94 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>;
- interrupts = <8>;
- status = "disabled";
- };
-
- lpc_ctrl: lpc-ctrl@0 {
- compatible = "aspeed,ast2500-lpc-ctrl";
- reg = <0x0 0x10>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- status = "disabled";
- };
-
- lpc_snoop: lpc-snoop@10 {
- compatible = "aspeed,ast2500-lpc-snoop";
- reg = <0x10 0x8>;
- interrupts = <8>;
- status = "disabled";
- };
-
- lpc_reset: reset-controller@18 {
- compatible = "aspeed,ast2500-lpc-reset";
- reg = <0x18 0x4>;
- #reset-cells = <1>;
- };
-
- lhc: lhc@20 {
- compatible = "aspeed,ast2500-lhc";
- reg = <0x20 0x24 0x48 0x8>;
- };
-
-
- ibt: ibt@c0 {
- compatible = "aspeed,ast2500-ibt-bmc";
- reg = <0xc0 0x18>;
- interrupts = <8>;
- status = "disabled";
- };
+ lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2500-lpc-ctrl";
+ reg = <0x80 0x10>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ status = "disabled";
+ };
+
+ lpc_snoop: lpc-snoop@90 {
+ compatible = "aspeed,ast2500-lpc-snoop";
+ reg = <0x90 0x8>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ lpc_reset: reset-controller@98 {
+ compatible = "aspeed,ast2500-lpc-reset";
+ reg = <0x98 0x4>;
+ #reset-cells = <1>;
+ };
+
+ lhc: lhc@a0 {
+ compatible = "aspeed,ast2500-lhc";
+ reg = <0xa0 0x24 0xc8 0x8>;
+ };
+
+
+ ibt: ibt@140 {
+ compatible = "aspeed,ast2500-ibt-bmc";
+ reg = <0x140 0x18>;
+ interrupts = <8>;
+ status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 810b0676ab03..d91f48c3db62 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -460,90 +460,73 @@
};
lpc: lpc@1e789000 {
- compatible = "aspeed,ast2600-lpc", "simple-mfd";
+ compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
+ reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
- lpc_bmc: lpc-bmc@0 {
- compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon";
- reg = <0x0 0x80>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x80>;
-
- kcs1: kcs@24 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- kcs_chan = <1>;
- status = "disabled";
- };
- kcs2: kcs@28 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
- kcs3: kcs@2c {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
+ kcs1: kcs@24 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ kcs_chan = <1>;
+ status = "disabled";
+ };
+
+ kcs2: kcs@28 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ kcs3: kcs@2c {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ kcs4: kcs@114 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2600-lpc-ctrl";
+ reg = <0x80 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ status = "disabled";
+ };
+
+ lpc_snoop: lpc-snoop@80 {
+ compatible = "aspeed,ast2600-lpc-snoop";
+ reg = <0x80 0x80>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
- lpc_host: lpc-host@80 {
- compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon";
- reg = <0x80 0x1e0>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x80 0x1e0>;
-
- kcs4: kcs@94 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- lpc_ctrl: lpc-ctrl@0 {
- compatible = "aspeed,ast2600-lpc-ctrl";
- reg = <0x0 0x80>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- status = "disabled";
- };
-
- lpc_snoop: lpc-snoop@0 {
- compatible = "aspeed,ast2600-lpc-snoop";
- reg = <0x0 0x80>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- lhc: lhc@20 {
- compatible = "aspeed,ast2600-lhc";
- reg = <0x20 0x24 0x48 0x8>;
- };
-
- lpc_reset: reset-controller@18 {
- compatible = "aspeed,ast2600-lpc-reset";
- reg = <0x18 0x4>;
- #reset-cells = <1>;
- };
-
- ibt: ibt@c0 {
- compatible = "aspeed,ast2600-ibt-bmc";
- reg = <0xc0 0x18>;
- interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
+ lhc: lhc@a0 {
+ compatible = "aspeed,ast2600-lhc";
+ reg = <0xa0 0x24 0xc8 0x8>;
+ };
+
+ lpc_reset: reset-controller@98 {
+ compatible = "aspeed,ast2600-lpc-reset";
+ reg = <0x98 0x4>;
+ #reset-cells = <1>;
+ };
+
+ ibt: ibt@140 {
+ compatible = "aspeed,ast2600-ibt-bmc";
+ reg = <0x140 0x18>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH v5 2/5] ARM: dts: Remove LPC BMC and Host partitions
@ 2021-01-14 13:16 ` Chia-Wei, Wang
0 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, cyrilbur, haiyue.wang
The LPC controller has no concept of the BMC and the Host partitions.
A concrete instance is that the HICRB[5:4] are for the I/O port address
configurtaion of KCS channel 1/2. However, the KCS driver cannot access
HICRB for channel 1/2 initialization via syscon regmap interface due to
the parition boundary. (i.e. offset 80h)
In addition, for the HW design backward compatibility, a newly added HW
control bit could be located at any reserved one over the LPC addressing
space. Thereby, this patch removes the lpc-bmc and lpc-host child node
and thus the LPC partitioning.
Note that this change requires the synchronization between device tree
change and the driver change. To prevent the misuse of old devicetrees
with new drivers, or vice versa, the v2 compatible strings are adopted
for the LPC device as listed:
"aspeed,ast2400-lpc-v2"
"aspeed,ast2500-lpc-v2"
"aspeed,ast2600-lpc-v2"
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 74 +++++++----------
arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++++++++-----------------
arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++++++++-----------------
3 files changed, 148 insertions(+), 196 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index b3dafbc8caca..ee22bc036440 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -343,58 +343,44 @@
};
lpc: lpc@1e789000 {
- compatible = "aspeed,ast2400-lpc", "simple-mfd";
+ compatible = "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
+ reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
- lpc_bmc: lpc-bmc@0 {
- compatible = "aspeed,ast2400-lpc-bmc";
- reg = <0x0 0x80>;
+ lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2400-lpc-ctrl";
+ reg = <0x80 0x10>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ status = "disabled";
};
- lpc_host: lpc-host@80 {
- compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
- reg = <0x80 0x1e0>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x80 0x1e0>;
-
- lpc_ctrl: lpc-ctrl@0 {
- compatible = "aspeed,ast2400-lpc-ctrl";
- reg = <0x0 0x10>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- status = "disabled";
- };
-
- lpc_snoop: lpc-snoop@10 {
- compatible = "aspeed,ast2400-lpc-snoop";
- reg = <0x10 0x8>;
- interrupts = <8>;
- status = "disabled";
- };
-
- lhc: lhc@20 {
- compatible = "aspeed,ast2400-lhc";
- reg = <0x20 0x24 0x48 0x8>;
- };
-
- lpc_reset: reset-controller@18 {
- compatible = "aspeed,ast2400-lpc-reset";
- reg = <0x18 0x4>;
- #reset-cells = <1>;
- };
-
- ibt: ibt@c0 {
- compatible = "aspeed,ast2400-ibt-bmc";
- reg = <0xc0 0x18>;
- interrupts = <8>;
- status = "disabled";
- };
+ lpc_snoop: lpc-snoop@90 {
+ compatible = "aspeed,ast2400-lpc-snoop";
+ reg = <0x90 0x8>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ lhc: lhc@a0 {
+ compatible = "aspeed,ast2400-lhc";
+ reg = <0xa0 0x24 0xc8 0x8>;
+ };
+
+ lpc_reset: reset-controller@98 {
+ compatible = "aspeed,ast2400-lpc-reset";
+ reg = <0x98 0x4>;
+ #reset-cells = <1>;
+ };
+
+ ibt: ibt@140 {
+ compatible = "aspeed,ast2400-ibt-bmc";
+ reg = <0x140 0x18>;
+ interrupts = <8>;
+ status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 5bc0de0f3365..10ca2100f69b 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -434,90 +434,73 @@
};
lpc: lpc@1e789000 {
- compatible = "aspeed,ast2500-lpc", "simple-mfd";
+ compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
+ reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
- lpc_bmc: lpc-bmc@0 {
- compatible = "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon";
- reg = <0x0 0x80>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x80>;
-
- kcs1: kcs@24 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
- interrupts = <8>;
- status = "disabled";
- };
- kcs2: kcs@28 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
- interrupts = <8>;
- status = "disabled";
- };
- kcs3: kcs@2c {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
- interrupts = <8>;
- status = "disabled";
- };
+ kcs1: kcs@24 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ kcs2: kcs@28 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ kcs3: kcs@2c {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ kcs4: kcs@114 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
+ interrupts = <8>;
+ status = "disabled";
};
- lpc_host: lpc-host@80 {
- compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
- reg = <0x80 0x1e0>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x80 0x1e0>;
-
- kcs4: kcs@94 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>;
- interrupts = <8>;
- status = "disabled";
- };
-
- lpc_ctrl: lpc-ctrl@0 {
- compatible = "aspeed,ast2500-lpc-ctrl";
- reg = <0x0 0x10>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- status = "disabled";
- };
-
- lpc_snoop: lpc-snoop@10 {
- compatible = "aspeed,ast2500-lpc-snoop";
- reg = <0x10 0x8>;
- interrupts = <8>;
- status = "disabled";
- };
-
- lpc_reset: reset-controller@18 {
- compatible = "aspeed,ast2500-lpc-reset";
- reg = <0x18 0x4>;
- #reset-cells = <1>;
- };
-
- lhc: lhc@20 {
- compatible = "aspeed,ast2500-lhc";
- reg = <0x20 0x24 0x48 0x8>;
- };
-
-
- ibt: ibt@c0 {
- compatible = "aspeed,ast2500-ibt-bmc";
- reg = <0xc0 0x18>;
- interrupts = <8>;
- status = "disabled";
- };
+ lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2500-lpc-ctrl";
+ reg = <0x80 0x10>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ status = "disabled";
+ };
+
+ lpc_snoop: lpc-snoop@90 {
+ compatible = "aspeed,ast2500-lpc-snoop";
+ reg = <0x90 0x8>;
+ interrupts = <8>;
+ status = "disabled";
+ };
+
+ lpc_reset: reset-controller@98 {
+ compatible = "aspeed,ast2500-lpc-reset";
+ reg = <0x98 0x4>;
+ #reset-cells = <1>;
+ };
+
+ lhc: lhc@a0 {
+ compatible = "aspeed,ast2500-lhc";
+ reg = <0xa0 0x24 0xc8 0x8>;
+ };
+
+
+ ibt: ibt@140 {
+ compatible = "aspeed,ast2500-ibt-bmc";
+ reg = <0x140 0x18>;
+ interrupts = <8>;
+ status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 810b0676ab03..d91f48c3db62 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -460,90 +460,73 @@
};
lpc: lpc@1e789000 {
- compatible = "aspeed,ast2600-lpc", "simple-mfd";
+ compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
reg = <0x1e789000 0x1000>;
+ reg-io-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
- lpc_bmc: lpc-bmc@0 {
- compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon";
- reg = <0x0 0x80>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x80>;
-
- kcs1: kcs@24 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- kcs_chan = <1>;
- status = "disabled";
- };
- kcs2: kcs@28 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
- kcs3: kcs@2c {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
+ kcs1: kcs@24 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ kcs_chan = <1>;
+ status = "disabled";
+ };
+
+ kcs2: kcs@28 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ kcs3: kcs@2c {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ kcs4: kcs@114 {
+ compatible = "aspeed,ast2500-kcs-bmc-v2";
+ reg = <0x114 0x1>, <0x118 0x1>, <0x11c 0x1>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2600-lpc-ctrl";
+ reg = <0x80 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ status = "disabled";
+ };
+
+ lpc_snoop: lpc-snoop@80 {
+ compatible = "aspeed,ast2600-lpc-snoop";
+ reg = <0x80 0x80>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
- lpc_host: lpc-host@80 {
- compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon";
- reg = <0x80 0x1e0>;
- reg-io-width = <4>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x80 0x1e0>;
-
- kcs4: kcs@94 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- lpc_ctrl: lpc-ctrl@0 {
- compatible = "aspeed,ast2600-lpc-ctrl";
- reg = <0x0 0x80>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- status = "disabled";
- };
-
- lpc_snoop: lpc-snoop@0 {
- compatible = "aspeed,ast2600-lpc-snoop";
- reg = <0x0 0x80>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- lhc: lhc@20 {
- compatible = "aspeed,ast2600-lhc";
- reg = <0x20 0x24 0x48 0x8>;
- };
-
- lpc_reset: reset-controller@18 {
- compatible = "aspeed,ast2600-lpc-reset";
- reg = <0x18 0x4>;
- #reset-cells = <1>;
- };
-
- ibt: ibt@c0 {
- compatible = "aspeed,ast2600-ibt-bmc";
- reg = <0xc0 0x18>;
- interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
+ lhc: lhc@a0 {
+ compatible = "aspeed,ast2600-lhc";
+ reg = <0xa0 0x24 0xc8 0x8>;
+ };
+
+ lpc_reset: reset-controller@98 {
+ compatible = "aspeed,ast2600-lpc-reset";
+ reg = <0x98 0x4>;
+ #reset-cells = <1>;
+ };
+
+ ibt: ibt@140 {
+ compatible = "aspeed,ast2600-ibt-bmc";
+ reg = <0x140 0x18>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
};
--
2.17.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* Re: [PATCH v5 2/5] ARM: dts: Remove LPC BMC and Host partitions
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-20 5:01 ` Andrew Jeffery
-1 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-20 5:01 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Haiyue Wang, Cyril Bur, Robert Lippert
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> The LPC controller has no concept of the BMC and the Host partitions.
>
> A concrete instance is that the HICRB[5:4] are for the I/O port address
> configurtaion of KCS channel 1/2. However, the KCS driver cannot access
> HICRB for channel 1/2 initialization via syscon regmap interface due to
> the parition boundary. (i.e. offset 80h)
>
> In addition, for the HW design backward compatibility, a newly added HW
> control bit could be located at any reserved one over the LPC addressing
> space. Thereby, this patch removes the lpc-bmc and lpc-host child node
> and thus the LPC partitioning.
>
> Note that this change requires the synchronization between device tree
> change and the driver change. To prevent the misuse of old devicetrees
> with new drivers, or vice versa, the v2 compatible strings are adopted
> for the LPC device as listed:
>
> "aspeed,ast2400-lpc-v2"
> "aspeed,ast2500-lpc-v2"
> "aspeed,ast2600-lpc-v2"
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 2/5] ARM: dts: Remove LPC BMC and Host partitions
@ 2021-01-20 5:01 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-20 5:01 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang, Robert Lippert
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> The LPC controller has no concept of the BMC and the Host partitions.
>
> A concrete instance is that the HICRB[5:4] are for the I/O port address
> configurtaion of KCS channel 1/2. However, the KCS driver cannot access
> HICRB for channel 1/2 initialization via syscon regmap interface due to
> the parition boundary. (i.e. offset 80h)
>
> In addition, for the HW design backward compatibility, a newly added HW
> control bit could be located at any reserved one over the LPC addressing
> space. Thereby, this patch removes the lpc-bmc and lpc-host child node
> and thus the LPC partitioning.
>
> Note that this change requires the synchronization between device tree
> change and the driver change. To prevent the misuse of old devicetrees
> with new drivers, or vice versa, the v2 compatible strings are adopted
> for the LPC device as listed:
>
> "aspeed,ast2400-lpc-v2"
> "aspeed,ast2500-lpc-v2"
> "aspeed,ast2600-lpc-v2"
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 2/5] ARM: dts: Remove LPC BMC and Host partitions
@ 2021-01-20 5:01 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-20 5:01 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> The LPC controller has no concept of the BMC and the Host partitions.
>
> A concrete instance is that the HICRB[5:4] are for the I/O port address
> configurtaion of KCS channel 1/2. However, the KCS driver cannot access
> HICRB for channel 1/2 initialization via syscon regmap interface due to
> the parition boundary. (i.e. offset 80h)
>
> In addition, for the HW design backward compatibility, a newly added HW
> control bit could be located at any reserved one over the LPC addressing
> space. Thereby, this patch removes the lpc-bmc and lpc-host child node
> and thus the LPC partitioning.
>
> Note that this change requires the synchronization between device tree
> change and the driver change. To prevent the misuse of old devicetrees
> with new drivers, or vice versa, the v2 compatible strings are adopted
> for the LPC device as listed:
>
> "aspeed,ast2400-lpc-v2"
> "aspeed,ast2500-lpc-v2"
> "aspeed,ast2600-lpc-v2"
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 2/5] ARM: dts: Remove LPC BMC and Host partitions
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-25 4:12 ` Andrew Jeffery
-1 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-25 4:12 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Haiyue Wang, Cyril Bur, Robert Lippert
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> The LPC controller has no concept of the BMC and the Host partitions.
>
> A concrete instance is that the HICRB[5:4] are for the I/O port address
> configurtaion of KCS channel 1/2. However, the KCS driver cannot access
> HICRB for channel 1/2 initialization via syscon regmap interface due to
> the parition boundary. (i.e. offset 80h)
>
> In addition, for the HW design backward compatibility, a newly added HW
> control bit could be located at any reserved one over the LPC addressing
> space. Thereby, this patch removes the lpc-bmc and lpc-host child node
> and thus the LPC partitioning.
>
> Note that this change requires the synchronization between device tree
> change and the driver change. To prevent the misuse of old devicetrees
> with new drivers, or vice versa, the v2 compatible strings are adopted
> for the LPC device as listed:
>
> "aspeed,ast2400-lpc-v2"
> "aspeed,ast2500-lpc-v2"
> "aspeed,ast2600-lpc-v2"
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 74 +++++++----------
> arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++++++++-----------------
> arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++++++++-----------------
I've booted a Witherspoon BMC and host with these patches applied, so for
aspeed-g5.dtsi:
Tested-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 2/5] ARM: dts: Remove LPC BMC and Host partitions
@ 2021-01-25 4:12 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-25 4:12 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang, Robert Lippert
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> The LPC controller has no concept of the BMC and the Host partitions.
>
> A concrete instance is that the HICRB[5:4] are for the I/O port address
> configurtaion of KCS channel 1/2. However, the KCS driver cannot access
> HICRB for channel 1/2 initialization via syscon regmap interface due to
> the parition boundary. (i.e. offset 80h)
>
> In addition, for the HW design backward compatibility, a newly added HW
> control bit could be located at any reserved one over the LPC addressing
> space. Thereby, this patch removes the lpc-bmc and lpc-host child node
> and thus the LPC partitioning.
>
> Note that this change requires the synchronization between device tree
> change and the driver change. To prevent the misuse of old devicetrees
> with new drivers, or vice versa, the v2 compatible strings are adopted
> for the LPC device as listed:
>
> "aspeed,ast2400-lpc-v2"
> "aspeed,ast2500-lpc-v2"
> "aspeed,ast2600-lpc-v2"
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 74 +++++++----------
> arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++++++++-----------------
> arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++++++++-----------------
I've booted a Witherspoon BMC and host with these patches applied, so for
aspeed-g5.dtsi:
Tested-by: Andrew Jeffery <andrew@aj.id.au>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 2/5] ARM: dts: Remove LPC BMC and Host partitions
@ 2021-01-25 4:12 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-25 4:12 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> The LPC controller has no concept of the BMC and the Host partitions.
>
> A concrete instance is that the HICRB[5:4] are for the I/O port address
> configurtaion of KCS channel 1/2. However, the KCS driver cannot access
> HICRB for channel 1/2 initialization via syscon regmap interface due to
> the parition boundary. (i.e. offset 80h)
>
> In addition, for the HW design backward compatibility, a newly added HW
> control bit could be located at any reserved one over the LPC addressing
> space. Thereby, this patch removes the lpc-bmc and lpc-host child node
> and thus the LPC partitioning.
>
> Note that this change requires the synchronization between device tree
> change and the driver change. To prevent the misuse of old devicetrees
> with new drivers, or vice versa, the v2 compatible strings are adopted
> for the LPC device as listed:
>
> "aspeed,ast2400-lpc-v2"
> "aspeed,ast2500-lpc-v2"
> "aspeed,ast2600-lpc-v2"
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 74 +++++++----------
> arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++++++++-----------------
> arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++++++++-----------------
I've booted a Witherspoon BMC and host with these patches applied, so for
aspeed-g5.dtsi:
Tested-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-14 13:16 ` Chia-Wei, Wang
-1 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, haiyue.wang, cyrilbur, rlippert
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Acked-by: Haiyue Wang <haiyue.wang@linux.intel.com>
---
drivers/char/ipmi/kcs_bmc_aspeed.c | 27 ++++++++++++++++-----------
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/drivers/char/ipmi/kcs_bmc_aspeed.c b/drivers/char/ipmi/kcs_bmc_aspeed.c
index a140203c079b..eefe362f65f0 100644
--- a/drivers/char/ipmi/kcs_bmc_aspeed.c
+++ b/drivers/char/ipmi/kcs_bmc_aspeed.c
@@ -27,7 +27,6 @@
#define KCS_CHANNEL_MAX 4
-/* mapped to lpc-bmc@0 IO space */
#define LPC_HICR0 0x000
#define LPC_HICR0_LPC3E BIT(7)
#define LPC_HICR0_LPC2E BIT(6)
@@ -52,15 +51,13 @@
#define LPC_STR1 0x03C
#define LPC_STR2 0x040
#define LPC_STR3 0x044
-
-/* mapped to lpc-host@80 IO space */
-#define LPC_HICRB 0x080
+#define LPC_HICRB 0x100
#define LPC_HICRB_IBFIF4 BIT(1)
#define LPC_HICRB_LPC4E BIT(0)
-#define LPC_LADR4 0x090
-#define LPC_IDR4 0x094
-#define LPC_ODR4 0x098
-#define LPC_STR4 0x09C
+#define LPC_LADR4 0x110
+#define LPC_IDR4 0x114
+#define LPC_ODR4 0x118
+#define LPC_STR4 0x11C
struct aspeed_kcs_bmc {
struct regmap *map;
@@ -348,12 +345,20 @@ static int aspeed_kcs_probe(struct platform_device *pdev)
struct device_node *np;
int rc;
- np = pdev->dev.of_node;
+ np = dev->of_node->parent;
+ if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) {
+ dev_err(dev, "unsupported LPC device binding\n");
+ return -ENODEV;
+ }
+
+ np = dev->of_node;
if (of_device_is_compatible(np, "aspeed,ast2400-kcs-bmc") ||
- of_device_is_compatible(np, "aspeed,ast2500-kcs-bmc"))
+ of_device_is_compatible(np, "aspeed,ast2500-kcs-bmc"))
kcs_bmc = aspeed_kcs_probe_of_v1(pdev);
else if (of_device_is_compatible(np, "aspeed,ast2400-kcs-bmc-v2") ||
- of_device_is_compatible(np, "aspeed,ast2500-kcs-bmc-v2"))
+ of_device_is_compatible(np, "aspeed,ast2500-kcs-bmc-v2"))
kcs_bmc = aspeed_kcs_probe_of_v2(pdev);
else
return -EINVAL;
--
2.17.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
@ 2021-01-14 13:16 ` Chia-Wei, Wang
0 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, cyrilbur, haiyue.wang, rlippert
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Acked-by: Haiyue Wang <haiyue.wang@linux.intel.com>
---
drivers/char/ipmi/kcs_bmc_aspeed.c | 27 ++++++++++++++++-----------
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/drivers/char/ipmi/kcs_bmc_aspeed.c b/drivers/char/ipmi/kcs_bmc_aspeed.c
index a140203c079b..eefe362f65f0 100644
--- a/drivers/char/ipmi/kcs_bmc_aspeed.c
+++ b/drivers/char/ipmi/kcs_bmc_aspeed.c
@@ -27,7 +27,6 @@
#define KCS_CHANNEL_MAX 4
-/* mapped to lpc-bmc@0 IO space */
#define LPC_HICR0 0x000
#define LPC_HICR0_LPC3E BIT(7)
#define LPC_HICR0_LPC2E BIT(6)
@@ -52,15 +51,13 @@
#define LPC_STR1 0x03C
#define LPC_STR2 0x040
#define LPC_STR3 0x044
-
-/* mapped to lpc-host@80 IO space */
-#define LPC_HICRB 0x080
+#define LPC_HICRB 0x100
#define LPC_HICRB_IBFIF4 BIT(1)
#define LPC_HICRB_LPC4E BIT(0)
-#define LPC_LADR4 0x090
-#define LPC_IDR4 0x094
-#define LPC_ODR4 0x098
-#define LPC_STR4 0x09C
+#define LPC_LADR4 0x110
+#define LPC_IDR4 0x114
+#define LPC_ODR4 0x118
+#define LPC_STR4 0x11C
struct aspeed_kcs_bmc {
struct regmap *map;
@@ -348,12 +345,20 @@ static int aspeed_kcs_probe(struct platform_device *pdev)
struct device_node *np;
int rc;
- np = pdev->dev.of_node;
+ np = dev->of_node->parent;
+ if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) {
+ dev_err(dev, "unsupported LPC device binding\n");
+ return -ENODEV;
+ }
+
+ np = dev->of_node;
if (of_device_is_compatible(np, "aspeed,ast2400-kcs-bmc") ||
- of_device_is_compatible(np, "aspeed,ast2500-kcs-bmc"))
+ of_device_is_compatible(np, "aspeed,ast2500-kcs-bmc"))
kcs_bmc = aspeed_kcs_probe_of_v1(pdev);
else if (of_device_is_compatible(np, "aspeed,ast2400-kcs-bmc-v2") ||
- of_device_is_compatible(np, "aspeed,ast2500-kcs-bmc-v2"))
+ of_device_is_compatible(np, "aspeed,ast2500-kcs-bmc-v2"))
kcs_bmc = aspeed_kcs_probe_of_v2(pdev);
else
return -EINVAL;
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
@ 2021-01-14 13:16 ` Chia-Wei, Wang
0 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, cyrilbur, haiyue.wang
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Acked-by: Haiyue Wang <haiyue.wang@linux.intel.com>
---
drivers/char/ipmi/kcs_bmc_aspeed.c | 27 ++++++++++++++++-----------
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/drivers/char/ipmi/kcs_bmc_aspeed.c b/drivers/char/ipmi/kcs_bmc_aspeed.c
index a140203c079b..eefe362f65f0 100644
--- a/drivers/char/ipmi/kcs_bmc_aspeed.c
+++ b/drivers/char/ipmi/kcs_bmc_aspeed.c
@@ -27,7 +27,6 @@
#define KCS_CHANNEL_MAX 4
-/* mapped to lpc-bmc@0 IO space */
#define LPC_HICR0 0x000
#define LPC_HICR0_LPC3E BIT(7)
#define LPC_HICR0_LPC2E BIT(6)
@@ -52,15 +51,13 @@
#define LPC_STR1 0x03C
#define LPC_STR2 0x040
#define LPC_STR3 0x044
-
-/* mapped to lpc-host@80 IO space */
-#define LPC_HICRB 0x080
+#define LPC_HICRB 0x100
#define LPC_HICRB_IBFIF4 BIT(1)
#define LPC_HICRB_LPC4E BIT(0)
-#define LPC_LADR4 0x090
-#define LPC_IDR4 0x094
-#define LPC_ODR4 0x098
-#define LPC_STR4 0x09C
+#define LPC_LADR4 0x110
+#define LPC_IDR4 0x114
+#define LPC_ODR4 0x118
+#define LPC_STR4 0x11C
struct aspeed_kcs_bmc {
struct regmap *map;
@@ -348,12 +345,20 @@ static int aspeed_kcs_probe(struct platform_device *pdev)
struct device_node *np;
int rc;
- np = pdev->dev.of_node;
+ np = dev->of_node->parent;
+ if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) {
+ dev_err(dev, "unsupported LPC device binding\n");
+ return -ENODEV;
+ }
+
+ np = dev->of_node;
if (of_device_is_compatible(np, "aspeed,ast2400-kcs-bmc") ||
- of_device_is_compatible(np, "aspeed,ast2500-kcs-bmc"))
+ of_device_is_compatible(np, "aspeed,ast2500-kcs-bmc"))
kcs_bmc = aspeed_kcs_probe_of_v1(pdev);
else if (of_device_is_compatible(np, "aspeed,ast2400-kcs-bmc-v2") ||
- of_device_is_compatible(np, "aspeed,ast2500-kcs-bmc-v2"))
+ of_device_is_compatible(np, "aspeed,ast2500-kcs-bmc-v2"))
kcs_bmc = aspeed_kcs_probe_of_v2(pdev);
else
return -EINVAL;
--
2.17.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* Re: [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-20 5:02 ` Andrew Jeffery
-1 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-20 5:02 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Haiyue Wang, Cyril Bur, Robert Lippert
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> Acked-by: Haiyue Wang <haiyue.wang@linux.intel.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
@ 2021-01-20 5:02 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-20 5:02 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang, Robert Lippert
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> Acked-by: Haiyue Wang <haiyue.wang@linux.intel.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
@ 2021-01-20 5:02 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-20 5:02 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> Acked-by: Haiyue Wang <haiyue.wang@linux.intel.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
2021-01-20 5:02 ` Andrew Jeffery
(?)
@ 2021-01-22 9:55 ` ChiaWei Wang
-1 siblings, 0 replies; 72+ messages in thread
From: ChiaWei Wang @ 2021-01-22 9:55 UTC (permalink / raw)
To: Andrew Jeffery, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Haiyue Wang, Cyril Bur, Robert Lippert
Hi Corey,
Could you help to review this patch to kcs_bmc_aspeed.c?
It mainly fixes the register layout/offsets of Aspeed LPC controller.
Thanks,
Chiawei
> -----Original Message-----
> From: Andrew Jeffery <andrew@aj.id.au>
> Sent: Wednesday, January 20, 2021 1:03 PM
> Subject: Re: [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
>
>
>
> On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > Add check against LPC device v2 compatible string to ensure that the
> > fixed device tree layout is adopted.
> > The LPC register offsets are also fixed accordingly.
> >
> > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> > Acked-by: Haiyue Wang <haiyue.wang@linux.intel.com>
>
> Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Thanks for the review.
^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
@ 2021-01-22 9:55 ` ChiaWei Wang
0 siblings, 0 replies; 72+ messages in thread
From: ChiaWei Wang @ 2021-01-22 9:55 UTC (permalink / raw)
To: Andrew Jeffery, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang, Robert Lippert
Hi Corey,
Could you help to review this patch to kcs_bmc_aspeed.c?
It mainly fixes the register layout/offsets of Aspeed LPC controller.
Thanks,
Chiawei
> -----Original Message-----
> From: Andrew Jeffery <andrew@aj.id.au>
> Sent: Wednesday, January 20, 2021 1:03 PM
> Subject: Re: [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
>
>
>
> On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > Add check against LPC device v2 compatible string to ensure that the
> > fixed device tree layout is adopted.
> > The LPC register offsets are also fixed accordingly.
> >
> > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> > Acked-by: Haiyue Wang <haiyue.wang@linux.intel.com>
>
> Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Thanks for the review.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
@ 2021-01-22 9:55 ` ChiaWei Wang
0 siblings, 0 replies; 72+ messages in thread
From: ChiaWei Wang @ 2021-01-22 9:55 UTC (permalink / raw)
To: Andrew Jeffery, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang
Hi Corey,
Could you help to review this patch to kcs_bmc_aspeed.c?
It mainly fixes the register layout/offsets of Aspeed LPC controller.
Thanks,
Chiawei
> -----Original Message-----
> From: Andrew Jeffery <andrew@aj.id.au>
> Sent: Wednesday, January 20, 2021 1:03 PM
> Subject: Re: [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
>
>
>
> On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > Add check against LPC device v2 compatible string to ensure that the
> > fixed device tree layout is adopted.
> > The LPC register offsets are also fixed accordingly.
> >
> > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> > Acked-by: Haiyue Wang <haiyue.wang@linux.intel.com>
>
> Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Thanks for the review.
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
2021-01-22 9:55 ` ChiaWei Wang
(?)
@ 2021-01-22 15:31 ` Corey Minyard
-1 siblings, 0 replies; 72+ messages in thread
From: Corey Minyard @ 2021-01-22 15:31 UTC (permalink / raw)
To: ChiaWei Wang
Cc: Andrew Jeffery, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, openbmc, BMC-SW, Haiyue Wang, Cyril Bur,
Robert Lippert
On Fri, Jan 22, 2021 at 09:55:56AM +0000, ChiaWei Wang wrote:
> Hi Corey,
>
> Could you help to review this patch to kcs_bmc_aspeed.c?
> It mainly fixes the register layout/offsets of Aspeed LPC controller.
I am not really qualified to review this. It looks ok from a structural
and style point of view, but that's all I can tell. So I'm ok with it.
Acked-by: Corey Minyard <cminyard@mvista.com>
>
> Thanks,
> Chiawei
>
> > -----Original Message-----
> > From: Andrew Jeffery <andrew@aj.id.au>
> > Sent: Wednesday, January 20, 2021 1:03 PM
> > Subject: Re: [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
> >
> >
> >
> > On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > > Add check against LPC device v2 compatible string to ensure that the
> > > fixed device tree layout is adopted.
> > > The LPC register offsets are also fixed accordingly.
> > >
> > > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> > > Acked-by: Haiyue Wang <haiyue.wang@linux.intel.com>
> >
> > Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
>
> Thanks for the review.
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
@ 2021-01-22 15:31 ` Corey Minyard
0 siblings, 0 replies; 72+ messages in thread
From: Corey Minyard @ 2021-01-22 15:31 UTC (permalink / raw)
To: ChiaWei Wang
Cc: devicetree, Haiyue Wang, linux-aspeed, BMC-SW, Andrew Jeffery,
Linus Walleij, linux-kernel, Cyril Bur, Robert Lippert,
Rob Herring, Joel Stanley, Lee Jones, openbmc, linux-arm-kernel
On Fri, Jan 22, 2021 at 09:55:56AM +0000, ChiaWei Wang wrote:
> Hi Corey,
>
> Could you help to review this patch to kcs_bmc_aspeed.c?
> It mainly fixes the register layout/offsets of Aspeed LPC controller.
I am not really qualified to review this. It looks ok from a structural
and style point of view, but that's all I can tell. So I'm ok with it.
Acked-by: Corey Minyard <cminyard@mvista.com>
>
> Thanks,
> Chiawei
>
> > -----Original Message-----
> > From: Andrew Jeffery <andrew@aj.id.au>
> > Sent: Wednesday, January 20, 2021 1:03 PM
> > Subject: Re: [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
> >
> >
> >
> > On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > > Add check against LPC device v2 compatible string to ensure that the
> > > fixed device tree layout is adopted.
> > > The LPC register offsets are also fixed accordingly.
> > >
> > > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> > > Acked-by: Haiyue Wang <haiyue.wang@linux.intel.com>
> >
> > Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
>
> Thanks for the review.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
@ 2021-01-22 15:31 ` Corey Minyard
0 siblings, 0 replies; 72+ messages in thread
From: Corey Minyard @ 2021-01-22 15:31 UTC (permalink / raw)
To: ChiaWei Wang
Cc: devicetree, Haiyue Wang, linux-aspeed, BMC-SW, Andrew Jeffery,
Linus Walleij, linux-kernel, Cyril Bur, Rob Herring, Lee Jones,
openbmc, linux-arm-kernel
On Fri, Jan 22, 2021 at 09:55:56AM +0000, ChiaWei Wang wrote:
> Hi Corey,
>
> Could you help to review this patch to kcs_bmc_aspeed.c?
> It mainly fixes the register layout/offsets of Aspeed LPC controller.
I am not really qualified to review this. It looks ok from a structural
and style point of view, but that's all I can tell. So I'm ok with it.
Acked-by: Corey Minyard <cminyard@mvista.com>
>
> Thanks,
> Chiawei
>
> > -----Original Message-----
> > From: Andrew Jeffery <andrew@aj.id.au>
> > Sent: Wednesday, January 20, 2021 1:03 PM
> > Subject: Re: [PATCH v5 3/5] ipmi: kcs: aspeed: Adapt to new LPC DTS layout
> >
> >
> >
> > On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > > Add check against LPC device v2 compatible string to ensure that the
> > > fixed device tree layout is adopted.
> > > The LPC register offsets are also fixed accordingly.
> > >
> > > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> > > Acked-by: Haiyue Wang <haiyue.wang@linux.intel.com>
> >
> > Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
>
> Thanks for the review.
^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-14 13:16 ` Chia-Wei, Wang
-1 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, haiyue.wang, cyrilbur, rlippert
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index 0cab4c2576e2..996ebcba4d38 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -60,7 +60,7 @@
#define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
/* LHCR0 is offset from the end of the H8S/2168-compatible registers */
-#define LHCR0 0x20
+#define LHCR0 0xa0
#define GFX064 0x64
#define B14 0
@@ -2648,14 +2648,19 @@ static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx,
}
if (ip == ASPEED_IP_LPC) {
- struct device_node *node;
+ struct device_node *np;
struct regmap *map;
- node = of_parse_phandle(ctx->dev->of_node,
+ np = of_parse_phandle(ctx->dev->of_node,
"aspeed,external-nodes", 1);
- if (node) {
- map = syscon_node_to_regmap(node->parent);
- of_node_put(node);
+ if (np) {
+ if (!of_device_is_compatible(np->parent, "aspeed,ast2400-lpc-v2") &&
+ !of_device_is_compatible(np->parent, "aspeed,ast2500-lpc-v2") &&
+ !of_device_is_compatible(np->parent, "aspeed,ast2600-lpc-v2"))
+ return ERR_PTR(-ENODEV);
+
+ map = syscon_node_to_regmap(np->parent);
+ of_node_put(np);
if (IS_ERR(map))
return map;
} else
--
2.17.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout
@ 2021-01-14 13:16 ` Chia-Wei, Wang
0 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, cyrilbur, haiyue.wang, rlippert
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index 0cab4c2576e2..996ebcba4d38 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -60,7 +60,7 @@
#define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
/* LHCR0 is offset from the end of the H8S/2168-compatible registers */
-#define LHCR0 0x20
+#define LHCR0 0xa0
#define GFX064 0x64
#define B14 0
@@ -2648,14 +2648,19 @@ static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx,
}
if (ip == ASPEED_IP_LPC) {
- struct device_node *node;
+ struct device_node *np;
struct regmap *map;
- node = of_parse_phandle(ctx->dev->of_node,
+ np = of_parse_phandle(ctx->dev->of_node,
"aspeed,external-nodes", 1);
- if (node) {
- map = syscon_node_to_regmap(node->parent);
- of_node_put(node);
+ if (np) {
+ if (!of_device_is_compatible(np->parent, "aspeed,ast2400-lpc-v2") &&
+ !of_device_is_compatible(np->parent, "aspeed,ast2500-lpc-v2") &&
+ !of_device_is_compatible(np->parent, "aspeed,ast2600-lpc-v2"))
+ return ERR_PTR(-ENODEV);
+
+ map = syscon_node_to_regmap(np->parent);
+ of_node_put(np);
if (IS_ERR(map))
return map;
} else
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout
@ 2021-01-14 13:16 ` Chia-Wei, Wang
0 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, cyrilbur, haiyue.wang
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index 0cab4c2576e2..996ebcba4d38 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -60,7 +60,7 @@
#define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
/* LHCR0 is offset from the end of the H8S/2168-compatible registers */
-#define LHCR0 0x20
+#define LHCR0 0xa0
#define GFX064 0x64
#define B14 0
@@ -2648,14 +2648,19 @@ static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx,
}
if (ip == ASPEED_IP_LPC) {
- struct device_node *node;
+ struct device_node *np;
struct regmap *map;
- node = of_parse_phandle(ctx->dev->of_node,
+ np = of_parse_phandle(ctx->dev->of_node,
"aspeed,external-nodes", 1);
- if (node) {
- map = syscon_node_to_regmap(node->parent);
- of_node_put(node);
+ if (np) {
+ if (!of_device_is_compatible(np->parent, "aspeed,ast2400-lpc-v2") &&
+ !of_device_is_compatible(np->parent, "aspeed,ast2500-lpc-v2") &&
+ !of_device_is_compatible(np->parent, "aspeed,ast2600-lpc-v2"))
+ return ERR_PTR(-ENODEV);
+
+ map = syscon_node_to_regmap(np->parent);
+ of_node_put(np);
if (IS_ERR(map))
return map;
} else
--
2.17.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* Re: [PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-18 14:59 ` Linus Walleij
-1 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2021-01-18 14:59 UTC (permalink / raw)
To: Chia-Wei, Wang
Cc: Rob Herring, Lee Jones, Joel Stanley, Andrew Jeffery,
Corey Minyard,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, linux-aspeed, linux-kernel, OpenBMC Maillist, BMC-SW,
haiyue.wang, cyrilbur, Robert Lippert
On Thu, Jan 14, 2021 at 2:17 PM Chia-Wei, Wang
<chiawei_wang@aspeedtech.com> wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
I suppose the patches need to go in together. Tell me if you
need me to apply this one patch to the pinctrl tree.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout
@ 2021-01-18 14:59 ` Linus Walleij
0 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2021-01-18 14:59 UTC (permalink / raw)
To: Chia-Wei, Wang
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
haiyue.wang, linux-aspeed, Corey Minyard, BMC-SW, Andrew Jeffery,
OpenBMC Maillist, linux-kernel, Robert Lippert, Rob Herring,
Joel Stanley, Lee Jones, cyrilbur, Linux ARM
On Thu, Jan 14, 2021 at 2:17 PM Chia-Wei, Wang
<chiawei_wang@aspeedtech.com> wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
I suppose the patches need to go in together. Tell me if you
need me to apply this one patch to the pinctrl tree.
Yours,
Linus Walleij
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout
@ 2021-01-18 14:59 ` Linus Walleij
0 siblings, 0 replies; 72+ messages in thread
From: Linus Walleij @ 2021-01-18 14:59 UTC (permalink / raw)
To: Chia-Wei, Wang
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
haiyue.wang, linux-aspeed, Corey Minyard, BMC-SW, Andrew Jeffery,
OpenBMC Maillist, linux-kernel, Rob Herring, Lee Jones, cyrilbur,
Linux ARM
On Thu, Jan 14, 2021 at 2:17 PM Chia-Wei, Wang
<chiawei_wang@aspeedtech.com> wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
I suppose the patches need to go in together. Tell me if you
need me to apply this one patch to the pinctrl tree.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-20 5:03 ` Andrew Jeffery
-1 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-20 5:03 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Haiyue Wang, Cyril Bur, Robert Lippert
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout
@ 2021-01-20 5:03 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-20 5:03 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang, Robert Lippert
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout
@ 2021-01-20 5:03 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-20 5:03 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-25 4:14 ` Andrew Jeffery
-1 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-25 4:14 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Haiyue Wang, Cyril Bur, Robert Lippert
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Using a Witherspoon (AST2500):
Tested-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout
@ 2021-01-25 4:14 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-25 4:14 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang, Robert Lippert
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Using a Witherspoon (AST2500):
Tested-by: Andrew Jeffery <andrew@aj.id.au>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 4/5] pinctrl: aspeed-g5: Adapt to new LPC device tree layout
@ 2021-01-25 4:14 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-25 4:14 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Using a Witherspoon (AST2500):
Tested-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 5/5] soc: aspeed: Adapt to new LPC device tree layout
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-14 13:16 ` Chia-Wei, Wang
-1 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, haiyue.wang, cyrilbur, rlippert
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
---
drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++++++++++++++------
drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +++++++++++++++--------
2 files changed, 29 insertions(+), 14 deletions(-)
diff --git a/drivers/soc/aspeed/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
index 439bcd6b8c4a..c557ffd0992c 100644
--- a/drivers/soc/aspeed/aspeed-lpc-ctrl.c
+++ b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
@@ -18,15 +18,15 @@
#define DEVICE_NAME "aspeed-lpc-ctrl"
-#define HICR5 0x0
+#define HICR5 0x80
#define HICR5_ENL2H BIT(8)
#define HICR5_ENFWH BIT(10)
-#define HICR6 0x4
+#define HICR6 0x84
#define SW_FWH2AHB BIT(17)
-#define HICR7 0x8
-#define HICR8 0xc
+#define HICR7 0x88
+#define HICR8 0x8c
struct aspeed_lpc_ctrl {
struct miscdevice miscdev;
@@ -215,6 +215,7 @@ static int aspeed_lpc_ctrl_probe(struct platform_device *pdev)
struct device_node *node;
struct resource resm;
struct device *dev;
+ struct device_node *np;
int rc;
dev = &pdev->dev;
@@ -270,8 +271,15 @@ static int aspeed_lpc_ctrl_probe(struct platform_device *pdev)
}
}
- lpc_ctrl->regmap = syscon_node_to_regmap(
- pdev->dev.parent->of_node);
+ np = pdev->dev.parent->of_node;
+ if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) {
+ dev_err(dev, "unsupported LPC device binding\n");
+ return -ENODEV;
+ }
+
+ lpc_ctrl->regmap = syscon_node_to_regmap(np);
if (IS_ERR(lpc_ctrl->regmap)) {
dev_err(dev, "Couldn't get regmap\n");
return -ENODEV;
diff --git a/drivers/soc/aspeed/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c
index 682ba0eb4eba..ab0f0a54fea6 100644
--- a/drivers/soc/aspeed/aspeed-lpc-snoop.c
+++ b/drivers/soc/aspeed/aspeed-lpc-snoop.c
@@ -28,26 +28,25 @@
#define NUM_SNOOP_CHANNELS 2
#define SNOOP_FIFO_SIZE 2048
-#define HICR5 0x0
+#define HICR5 0x80
#define HICR5_EN_SNP0W BIT(0)
#define HICR5_ENINT_SNP0W BIT(1)
#define HICR5_EN_SNP1W BIT(2)
#define HICR5_ENINT_SNP1W BIT(3)
-
-#define HICR6 0x4
+#define HICR6 0x84
#define HICR6_STR_SNP0W BIT(0)
#define HICR6_STR_SNP1W BIT(1)
-#define SNPWADR 0x10
+#define SNPWADR 0x90
#define SNPWADR_CH0_MASK GENMASK(15, 0)
#define SNPWADR_CH0_SHIFT 0
#define SNPWADR_CH1_MASK GENMASK(31, 16)
#define SNPWADR_CH1_SHIFT 16
-#define SNPWDR 0x14
+#define SNPWDR 0x94
#define SNPWDR_CH0_MASK GENMASK(7, 0)
#define SNPWDR_CH0_SHIFT 0
#define SNPWDR_CH1_MASK GENMASK(15, 8)
#define SNPWDR_CH1_SHIFT 8
-#define HICRB 0x80
+#define HICRB 0x100
#define HICRB_ENSNP0D BIT(14)
#define HICRB_ENSNP1D BIT(15)
@@ -258,6 +257,7 @@ static int aspeed_lpc_snoop_probe(struct platform_device *pdev)
{
struct aspeed_lpc_snoop *lpc_snoop;
struct device *dev;
+ struct device_node *np;
u32 port;
int rc;
@@ -267,8 +267,15 @@ static int aspeed_lpc_snoop_probe(struct platform_device *pdev)
if (!lpc_snoop)
return -ENOMEM;
- lpc_snoop->regmap = syscon_node_to_regmap(
- pdev->dev.parent->of_node);
+ np = pdev->dev.parent->of_node;
+ if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) {
+ dev_err(dev, "unsupported LPC device binding\n");
+ return -ENODEV;
+ }
+
+ lpc_snoop->regmap = syscon_node_to_regmap(np);
if (IS_ERR(lpc_snoop->regmap)) {
dev_err(dev, "Couldn't get regmap\n");
return -ENODEV;
--
2.17.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH v5 5/5] soc: aspeed: Adapt to new LPC device tree layout
@ 2021-01-14 13:16 ` Chia-Wei, Wang
0 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, cyrilbur, haiyue.wang, rlippert
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
---
drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++++++++++++++------
drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +++++++++++++++--------
2 files changed, 29 insertions(+), 14 deletions(-)
diff --git a/drivers/soc/aspeed/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
index 439bcd6b8c4a..c557ffd0992c 100644
--- a/drivers/soc/aspeed/aspeed-lpc-ctrl.c
+++ b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
@@ -18,15 +18,15 @@
#define DEVICE_NAME "aspeed-lpc-ctrl"
-#define HICR5 0x0
+#define HICR5 0x80
#define HICR5_ENL2H BIT(8)
#define HICR5_ENFWH BIT(10)
-#define HICR6 0x4
+#define HICR6 0x84
#define SW_FWH2AHB BIT(17)
-#define HICR7 0x8
-#define HICR8 0xc
+#define HICR7 0x88
+#define HICR8 0x8c
struct aspeed_lpc_ctrl {
struct miscdevice miscdev;
@@ -215,6 +215,7 @@ static int aspeed_lpc_ctrl_probe(struct platform_device *pdev)
struct device_node *node;
struct resource resm;
struct device *dev;
+ struct device_node *np;
int rc;
dev = &pdev->dev;
@@ -270,8 +271,15 @@ static int aspeed_lpc_ctrl_probe(struct platform_device *pdev)
}
}
- lpc_ctrl->regmap = syscon_node_to_regmap(
- pdev->dev.parent->of_node);
+ np = pdev->dev.parent->of_node;
+ if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) {
+ dev_err(dev, "unsupported LPC device binding\n");
+ return -ENODEV;
+ }
+
+ lpc_ctrl->regmap = syscon_node_to_regmap(np);
if (IS_ERR(lpc_ctrl->regmap)) {
dev_err(dev, "Couldn't get regmap\n");
return -ENODEV;
diff --git a/drivers/soc/aspeed/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c
index 682ba0eb4eba..ab0f0a54fea6 100644
--- a/drivers/soc/aspeed/aspeed-lpc-snoop.c
+++ b/drivers/soc/aspeed/aspeed-lpc-snoop.c
@@ -28,26 +28,25 @@
#define NUM_SNOOP_CHANNELS 2
#define SNOOP_FIFO_SIZE 2048
-#define HICR5 0x0
+#define HICR5 0x80
#define HICR5_EN_SNP0W BIT(0)
#define HICR5_ENINT_SNP0W BIT(1)
#define HICR5_EN_SNP1W BIT(2)
#define HICR5_ENINT_SNP1W BIT(3)
-
-#define HICR6 0x4
+#define HICR6 0x84
#define HICR6_STR_SNP0W BIT(0)
#define HICR6_STR_SNP1W BIT(1)
-#define SNPWADR 0x10
+#define SNPWADR 0x90
#define SNPWADR_CH0_MASK GENMASK(15, 0)
#define SNPWADR_CH0_SHIFT 0
#define SNPWADR_CH1_MASK GENMASK(31, 16)
#define SNPWADR_CH1_SHIFT 16
-#define SNPWDR 0x14
+#define SNPWDR 0x94
#define SNPWDR_CH0_MASK GENMASK(7, 0)
#define SNPWDR_CH0_SHIFT 0
#define SNPWDR_CH1_MASK GENMASK(15, 8)
#define SNPWDR_CH1_SHIFT 8
-#define HICRB 0x80
+#define HICRB 0x100
#define HICRB_ENSNP0D BIT(14)
#define HICRB_ENSNP1D BIT(15)
@@ -258,6 +257,7 @@ static int aspeed_lpc_snoop_probe(struct platform_device *pdev)
{
struct aspeed_lpc_snoop *lpc_snoop;
struct device *dev;
+ struct device_node *np;
u32 port;
int rc;
@@ -267,8 +267,15 @@ static int aspeed_lpc_snoop_probe(struct platform_device *pdev)
if (!lpc_snoop)
return -ENOMEM;
- lpc_snoop->regmap = syscon_node_to_regmap(
- pdev->dev.parent->of_node);
+ np = pdev->dev.parent->of_node;
+ if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) {
+ dev_err(dev, "unsupported LPC device binding\n");
+ return -ENODEV;
+ }
+
+ lpc_snoop->regmap = syscon_node_to_regmap(np);
if (IS_ERR(lpc_snoop->regmap)) {
dev_err(dev, "Couldn't get regmap\n");
return -ENODEV;
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH v5 5/5] soc: aspeed: Adapt to new LPC device tree layout
@ 2021-01-14 13:16 ` Chia-Wei, Wang
0 siblings, 0 replies; 72+ messages in thread
From: Chia-Wei, Wang @ 2021-01-14 13:16 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, cyrilbur, haiyue.wang
Add check against LPC device v2 compatible string to
ensure that the fixed device tree layout is adopted.
The LPC register offsets are also fixed accordingly.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
---
drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++++++++++++++------
drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +++++++++++++++--------
2 files changed, 29 insertions(+), 14 deletions(-)
diff --git a/drivers/soc/aspeed/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
index 439bcd6b8c4a..c557ffd0992c 100644
--- a/drivers/soc/aspeed/aspeed-lpc-ctrl.c
+++ b/drivers/soc/aspeed/aspeed-lpc-ctrl.c
@@ -18,15 +18,15 @@
#define DEVICE_NAME "aspeed-lpc-ctrl"
-#define HICR5 0x0
+#define HICR5 0x80
#define HICR5_ENL2H BIT(8)
#define HICR5_ENFWH BIT(10)
-#define HICR6 0x4
+#define HICR6 0x84
#define SW_FWH2AHB BIT(17)
-#define HICR7 0x8
-#define HICR8 0xc
+#define HICR7 0x88
+#define HICR8 0x8c
struct aspeed_lpc_ctrl {
struct miscdevice miscdev;
@@ -215,6 +215,7 @@ static int aspeed_lpc_ctrl_probe(struct platform_device *pdev)
struct device_node *node;
struct resource resm;
struct device *dev;
+ struct device_node *np;
int rc;
dev = &pdev->dev;
@@ -270,8 +271,15 @@ static int aspeed_lpc_ctrl_probe(struct platform_device *pdev)
}
}
- lpc_ctrl->regmap = syscon_node_to_regmap(
- pdev->dev.parent->of_node);
+ np = pdev->dev.parent->of_node;
+ if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) {
+ dev_err(dev, "unsupported LPC device binding\n");
+ return -ENODEV;
+ }
+
+ lpc_ctrl->regmap = syscon_node_to_regmap(np);
if (IS_ERR(lpc_ctrl->regmap)) {
dev_err(dev, "Couldn't get regmap\n");
return -ENODEV;
diff --git a/drivers/soc/aspeed/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c
index 682ba0eb4eba..ab0f0a54fea6 100644
--- a/drivers/soc/aspeed/aspeed-lpc-snoop.c
+++ b/drivers/soc/aspeed/aspeed-lpc-snoop.c
@@ -28,26 +28,25 @@
#define NUM_SNOOP_CHANNELS 2
#define SNOOP_FIFO_SIZE 2048
-#define HICR5 0x0
+#define HICR5 0x80
#define HICR5_EN_SNP0W BIT(0)
#define HICR5_ENINT_SNP0W BIT(1)
#define HICR5_EN_SNP1W BIT(2)
#define HICR5_ENINT_SNP1W BIT(3)
-
-#define HICR6 0x4
+#define HICR6 0x84
#define HICR6_STR_SNP0W BIT(0)
#define HICR6_STR_SNP1W BIT(1)
-#define SNPWADR 0x10
+#define SNPWADR 0x90
#define SNPWADR_CH0_MASK GENMASK(15, 0)
#define SNPWADR_CH0_SHIFT 0
#define SNPWADR_CH1_MASK GENMASK(31, 16)
#define SNPWADR_CH1_SHIFT 16
-#define SNPWDR 0x14
+#define SNPWDR 0x94
#define SNPWDR_CH0_MASK GENMASK(7, 0)
#define SNPWDR_CH0_SHIFT 0
#define SNPWDR_CH1_MASK GENMASK(15, 8)
#define SNPWDR_CH1_SHIFT 8
-#define HICRB 0x80
+#define HICRB 0x100
#define HICRB_ENSNP0D BIT(14)
#define HICRB_ENSNP1D BIT(15)
@@ -258,6 +257,7 @@ static int aspeed_lpc_snoop_probe(struct platform_device *pdev)
{
struct aspeed_lpc_snoop *lpc_snoop;
struct device *dev;
+ struct device_node *np;
u32 port;
int rc;
@@ -267,8 +267,15 @@ static int aspeed_lpc_snoop_probe(struct platform_device *pdev)
if (!lpc_snoop)
return -ENOMEM;
- lpc_snoop->regmap = syscon_node_to_regmap(
- pdev->dev.parent->of_node);
+ np = pdev->dev.parent->of_node;
+ if (!of_device_is_compatible(np, "aspeed,ast2400-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2500-lpc-v2") &&
+ !of_device_is_compatible(np, "aspeed,ast2600-lpc-v2")) {
+ dev_err(dev, "unsupported LPC device binding\n");
+ return -ENODEV;
+ }
+
+ lpc_snoop->regmap = syscon_node_to_regmap(np);
if (IS_ERR(lpc_snoop->regmap)) {
dev_err(dev, "Couldn't get regmap\n");
return -ENODEV;
--
2.17.1
^ permalink raw reply related [flat|nested] 72+ messages in thread* [PATCH v5 5/5] soc: aspeed: Adapt to new LPC device tree layout
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-20 5:10 ` Andrew Jeffery
-1 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-20 5:10 UTC (permalink / raw)
To: chiawei_wang
Cc: BMC-SW, andrew, cyrilbur, devicetree, haiyue.wang, joel,
lee.jones, linus.walleij, linux-arm-kernel, linux-aspeed,
linux-kernel, minyard, openbmc, rlippert, robh+dt
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> ---
> drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++++++++++++++------
> drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +++++++++++++++--------
In the future please do separate patches for separate drivers, but for now:
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 5/5] soc: aspeed: Adapt to new LPC device tree layout
@ 2021-01-20 5:10 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-20 5:10 UTC (permalink / raw)
To: chiawei_wang
Cc: linux-arm-kernel, BMC-SW, minyard, linux-aspeed, devicetree,
andrew, linus.walleij, linux-kernel, openbmc, rlippert, robh+dt,
joel, lee.jones, cyrilbur, haiyue.wang
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> ---
> drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++++++++++++++------
> drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +++++++++++++++--------
In the future please do separate patches for separate drivers, but for now:
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* [PATCH v5 5/5] soc: aspeed: Adapt to new LPC device tree layout
@ 2021-01-20 5:10 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-20 5:10 UTC (permalink / raw)
To: chiawei_wang
Cc: linux-arm-kernel, BMC-SW, minyard, linux-aspeed, devicetree,
andrew, linus.walleij, linux-kernel, openbmc, robh+dt, lee.jones,
cyrilbur, haiyue.wang
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> ---
> drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++++++++++++++------
> drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +++++++++++++++--------
In the future please do separate patches for separate drivers, but for now:
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 5/5] soc: aspeed: Adapt to new LPC device tree layout
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-25 4:15 ` Andrew Jeffery
-1 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-25 4:15 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Haiyue Wang, Cyril Bur, Robert Lippert
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> ---
> drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++++++++++++++------
> drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +++++++++++++++--------
Using a Witherspoon (AST2500) I've tested the aspeed-lpc-ctrl driver:
Tested-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 5/5] soc: aspeed: Adapt to new LPC device tree layout
@ 2021-01-25 4:15 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-25 4:15 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang, Robert Lippert
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> ---
> drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++++++++++++++------
> drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +++++++++++++++--------
Using a Witherspoon (AST2500) I've tested the aspeed-lpc-ctrl driver:
Tested-by: Andrew Jeffery <andrew@aj.id.au>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* Re: [PATCH v5 5/5] soc: aspeed: Adapt to new LPC device tree layout
@ 2021-01-25 4:15 ` Andrew Jeffery
0 siblings, 0 replies; 72+ messages in thread
From: Andrew Jeffery @ 2021-01-25 4:15 UTC (permalink / raw)
To: Chia-Wei, Wang, Rob Herring, Lee Jones, Joel Stanley,
Linus Walleij, Corey Minyard, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, openbmc
Cc: BMC-SW, Cyril Bur, Haiyue Wang
On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> Add check against LPC device v2 compatible string to
> ensure that the fixed device tree layout is adopted.
> The LPC register offsets are also fixed accordingly.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> ---
> drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++++++++++++++------
> drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +++++++++++++++--------
Using a Witherspoon (AST2500) I've tested the aspeed-lpc-ctrl driver:
Tested-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 0/5] Remove LPC register partitioning
2021-01-14 13:16 ` Chia-Wei, Wang
(?)
@ 2021-01-26 5:51 ` ChiaWei Wang
-1 siblings, 0 replies; 72+ messages in thread
From: ChiaWei Wang @ 2021-01-26 5:51 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, haiyue.wang, cyrilbur, rlippert
Thank you all for the reviewing effort.
Hi Joel,
Would you help to merge these patches into Aspeed tree?
If yes, we should also notify Linus Walleij to apply the pinctrl one to the pinctrl tree.
Thanks,
Chiawei
> -----Original Message-----
> From: ChiaWei Wang <chiawei_wang@aspeedtech.com>
> Sent: Thursday, January 14, 2021 9:16 PM
> To: robh+dt@kernel.org; lee.jones@linaro.org; joel@jms.id.au;
> andrew@aj.id.au; linus.walleij@linaro.org; minyard@acm.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-aspeed@lists.ozlabs.org; linux-kernel@vger.kernel.org;
> openbmc@lists.ozlabs.org
> Cc: BMC-SW <BMC-SW@aspeedtech.com>; haiyue.wang@linux.intel.com;
> cyrilbur@gmail.com; rlippert@google.com
> Subject: [PATCH v5 0/5] Remove LPC register partitioning
>
> The LPC controller has no concept of the BMC and the Host partitions.
> The incorrect partitioning can impose unnecessary range restrictions on
> register access through the syscon regmap interface.
>
> For instance, HICRB contains the I/O port address configuration of KCS channel
> 1/2. However, the KCS#1/#2 drivers cannot access HICRB as it is located at the
> other LPC partition.
>
> In addition, to be backward compatible, the newly added HW control bits could
> be located at any reserved bits over the LPC addressing space.
>
> Thereby, this patch series aims to remove the LPC partitioning for better driver
> development and maintenance. This requires the change to both the device
> tree and the driver implementation. To ensure both sides are synchronously
> updated, a v2 binding check is added.
>
> Chagnes since v4:
> - Add child node example in dt-bindings.
>
> Chagnes since v3:
> - Revise binding check as suggested by Haiyue Wang.
>
> Changes since v2:
> - Add v2 binding check to ensure the synchronization between the
> device tree change and the driver register offset fix.
>
> Changes since v1:
> - Add the fix to the aspeed-lpc binding documentation.
>
> Chia-Wei, Wang (5):
> dt-bindings: aspeed-lpc: Remove LPC partitioning
> ARM: dts: Remove LPC BMC and Host partitions
> ipmi: kcs: aspeed: Adapt to new LPC DTS layout
> pinctrl: aspeed-g5: Adapt to new LPC device tree layout
> soc: aspeed: Adapt to new LPC device tree layout
>
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 100 ++++---------
> arch/arm/boot/dts/aspeed-g4.dtsi | 74 ++++------
> arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++----------
> arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++----------
> drivers/char/ipmi/kcs_bmc_aspeed.c | 27 ++--
> drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 ++-
> drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++-
> drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +--
> 8 files changed, 229 insertions(+), 302 deletions(-)
>
> --
> 2.17.1
^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 0/5] Remove LPC register partitioning
@ 2021-01-26 5:51 ` ChiaWei Wang
0 siblings, 0 replies; 72+ messages in thread
From: ChiaWei Wang @ 2021-01-26 5:51 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, cyrilbur, haiyue.wang, rlippert
Thank you all for the reviewing effort.
Hi Joel,
Would you help to merge these patches into Aspeed tree?
If yes, we should also notify Linus Walleij to apply the pinctrl one to the pinctrl tree.
Thanks,
Chiawei
> -----Original Message-----
> From: ChiaWei Wang <chiawei_wang@aspeedtech.com>
> Sent: Thursday, January 14, 2021 9:16 PM
> To: robh+dt@kernel.org; lee.jones@linaro.org; joel@jms.id.au;
> andrew@aj.id.au; linus.walleij@linaro.org; minyard@acm.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-aspeed@lists.ozlabs.org; linux-kernel@vger.kernel.org;
> openbmc@lists.ozlabs.org
> Cc: BMC-SW <BMC-SW@aspeedtech.com>; haiyue.wang@linux.intel.com;
> cyrilbur@gmail.com; rlippert@google.com
> Subject: [PATCH v5 0/5] Remove LPC register partitioning
>
> The LPC controller has no concept of the BMC and the Host partitions.
> The incorrect partitioning can impose unnecessary range restrictions on
> register access through the syscon regmap interface.
>
> For instance, HICRB contains the I/O port address configuration of KCS channel
> 1/2. However, the KCS#1/#2 drivers cannot access HICRB as it is located at the
> other LPC partition.
>
> In addition, to be backward compatible, the newly added HW control bits could
> be located at any reserved bits over the LPC addressing space.
>
> Thereby, this patch series aims to remove the LPC partitioning for better driver
> development and maintenance. This requires the change to both the device
> tree and the driver implementation. To ensure both sides are synchronously
> updated, a v2 binding check is added.
>
> Chagnes since v4:
> - Add child node example in dt-bindings.
>
> Chagnes since v3:
> - Revise binding check as suggested by Haiyue Wang.
>
> Changes since v2:
> - Add v2 binding check to ensure the synchronization between the
> device tree change and the driver register offset fix.
>
> Changes since v1:
> - Add the fix to the aspeed-lpc binding documentation.
>
> Chia-Wei, Wang (5):
> dt-bindings: aspeed-lpc: Remove LPC partitioning
> ARM: dts: Remove LPC BMC and Host partitions
> ipmi: kcs: aspeed: Adapt to new LPC DTS layout
> pinctrl: aspeed-g5: Adapt to new LPC device tree layout
> soc: aspeed: Adapt to new LPC device tree layout
>
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 100 ++++---------
> arch/arm/boot/dts/aspeed-g4.dtsi | 74 ++++------
> arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++----------
> arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++----------
> drivers/char/ipmi/kcs_bmc_aspeed.c | 27 ++--
> drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 ++-
> drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++-
> drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +--
> 8 files changed, 229 insertions(+), 302 deletions(-)
>
> --
> 2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 72+ messages in thread
* RE: [PATCH v5 0/5] Remove LPC register partitioning
@ 2021-01-26 5:51 ` ChiaWei Wang
0 siblings, 0 replies; 72+ messages in thread
From: ChiaWei Wang @ 2021-01-26 5:51 UTC (permalink / raw)
To: robh+dt, lee.jones, joel, andrew, linus.walleij, minyard,
devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
openbmc
Cc: BMC-SW, cyrilbur, haiyue.wang
Thank you all for the reviewing effort.
Hi Joel,
Would you help to merge these patches into Aspeed tree?
If yes, we should also notify Linus Walleij to apply the pinctrl one to the pinctrl tree.
Thanks,
Chiawei
> -----Original Message-----
> From: ChiaWei Wang <chiawei_wang@aspeedtech.com>
> Sent: Thursday, January 14, 2021 9:16 PM
> To: robh+dt@kernel.org; lee.jones@linaro.org; joel@jms.id.au;
> andrew@aj.id.au; linus.walleij@linaro.org; minyard@acm.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-aspeed@lists.ozlabs.org; linux-kernel@vger.kernel.org;
> openbmc@lists.ozlabs.org
> Cc: BMC-SW <BMC-SW@aspeedtech.com>; haiyue.wang@linux.intel.com;
> cyrilbur@gmail.com; rlippert@google.com
> Subject: [PATCH v5 0/5] Remove LPC register partitioning
>
> The LPC controller has no concept of the BMC and the Host partitions.
> The incorrect partitioning can impose unnecessary range restrictions on
> register access through the syscon regmap interface.
>
> For instance, HICRB contains the I/O port address configuration of KCS channel
> 1/2. However, the KCS#1/#2 drivers cannot access HICRB as it is located at the
> other LPC partition.
>
> In addition, to be backward compatible, the newly added HW control bits could
> be located at any reserved bits over the LPC addressing space.
>
> Thereby, this patch series aims to remove the LPC partitioning for better driver
> development and maintenance. This requires the change to both the device
> tree and the driver implementation. To ensure both sides are synchronously
> updated, a v2 binding check is added.
>
> Chagnes since v4:
> - Add child node example in dt-bindings.
>
> Chagnes since v3:
> - Revise binding check as suggested by Haiyue Wang.
>
> Changes since v2:
> - Add v2 binding check to ensure the synchronization between the
> device tree change and the driver register offset fix.
>
> Changes since v1:
> - Add the fix to the aspeed-lpc binding documentation.
>
> Chia-Wei, Wang (5):
> dt-bindings: aspeed-lpc: Remove LPC partitioning
> ARM: dts: Remove LPC BMC and Host partitions
> ipmi: kcs: aspeed: Adapt to new LPC DTS layout
> pinctrl: aspeed-g5: Adapt to new LPC device tree layout
> soc: aspeed: Adapt to new LPC device tree layout
>
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 100 ++++---------
> arch/arm/boot/dts/aspeed-g4.dtsi | 74 ++++------
> arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++----------
> arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++----------
> drivers/char/ipmi/kcs_bmc_aspeed.c | 27 ++--
> drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 ++-
> drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++-
> drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +--
> 8 files changed, 229 insertions(+), 302 deletions(-)
>
> --
> 2.17.1
^ permalink raw reply [flat|nested] 72+ messages in thread