From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7E32C4332F for ; Thu, 23 Sep 2021 00:02:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 880F761131 for ; Thu, 23 Sep 2021 00:02:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238586AbhIWAED (ORCPT ); Wed, 22 Sep 2021 20:04:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230414AbhIWAEB (ORCPT ); Wed, 22 Sep 2021 20:04:01 -0400 Received: from mail-qv1-xf33.google.com (mail-qv1-xf33.google.com [IPv6:2607:f8b0:4864:20::f33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A28AC061574; Wed, 22 Sep 2021 17:02:30 -0700 (PDT) Received: by mail-qv1-xf33.google.com with SMTP id gs10so3112674qvb.13; Wed, 22 Sep 2021 17:02:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jms.id.au; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=6za8hvNiMknZJLAQShJVN9k8ISMwqJs16dYb7Dbhy5I=; b=axUK3TKinPUn6A14DlJ5l75sUiHUS4zA4aiWlQb2xZNI7d/ZObmdqIZAwSJF6Qcx3X Bxveue63eavt8VkKBEHVhr5BP/mpZ4LxgbBBPS+If5Unl9y8AL15Fby7WugMV7wAbGrh 53pH+8O1hJDpwkBoww1i77rp+yHIn34Ss/oGc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=6za8hvNiMknZJLAQShJVN9k8ISMwqJs16dYb7Dbhy5I=; b=b8wGX0nxwfKkdKgGGNBjnlfHNCCurM5bB91wv8zWss1CjFD6QpxPc/2vwX7iSBM+bD 4s8wSC/Lv3wjxygpF1bBwJ9XgMTJHq+DfX4GSQAEcY8PzC17NEIPsFkuOVv1tIyRVWcr xxeLZK/YCa8q1ZSL5BB4jIK95CQSc2ttnTSvirOpOxs+zhRDxVlenF6ybcMwmtzSufFj qn5Way7olLyUPy2FFia/+j8cQksIW7t5lkOUfLLjfYJPjvEDettFGu/R2HoBIVIfS2qU pCzsUiTjeCb7PqeTE2cHTT1/yOXICmlG7lp7RAMbtPiBCgqT7MWkfZjXaiPiMDd5rN7Y 7P7Q== X-Gm-Message-State: AOAM532U2LDwLKqpT3gFSgCTPe8JbT9T8SME2iqQGHpM0Max+PpA50kK xHkn2FbYuUDwGnOGgm8+p72j8V3t+bJ77XEG4/OOrTR37RMDfQ== X-Google-Smtp-Source: ABdhPJwXwTQ1XjK5fncsWgEeP1jfN7ZYA6DFOZN7Q3GRnYZd8PBPLFUInicZnO0NAukPfyU/GXMHGGR33J3eFlRlg9s= X-Received: by 2002:ad4:54c6:: with SMTP id j6mr1959081qvx.17.1632355349480; Wed, 22 Sep 2021 17:02:29 -0700 (PDT) MIME-Version: 1.0 References: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> <20210922103116.30652-2-chin-ting_kuo@aspeedtech.com> In-Reply-To: <20210922103116.30652-2-chin-ting_kuo@aspeedtech.com> From: Joel Stanley Date: Thu, 23 Sep 2021 00:02:17 +0000 Message-ID: Subject: Re: [PATCH 01/10] clk: aspeed: ast2600: Porting sdhci clock source To: Chin-Ting Kuo Cc: Rob Herring , Michael Turquette , Stephen Boyd , Adrian Hunter , linux-aspeed , OpenBMC Maillist , linux-mmc , devicetree , Linux ARM , Linux Kernel Mailing List , linux-clk@vger.kernel.org, Andrew Jeffery , BMC-SW , Steven Lee Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 22 Sept 2021 at 10:31, Chin-Ting Kuo wrote: > > - There are two clock sources used to generate > SD/SDIO clock, APLL clock and HCLK (200MHz). > User can select which clock source should be used > by configuring SCU310[8]. > - The SD/SDIO clock divider selection table SCU310[30:28] > is different between AST2600-A1 and AST2600-A2/A3. > For AST2600-A1, 200MHz SD/SDIO clock cannot be > gotten by the dividers in SCU310[30:28] if APLL > is not the multiple of 200MHz and HCLK is 200MHz. > For AST2600-A2/A3, a new divider, "1", is added and > 200MHz SD/SDIO clock can be obtained by adopting HCLK > as clock source and setting SCU310[30:28] to 3b'111. > > Signed-off-by: Chin-Ting Kuo > --- > drivers/clk/clk-ast2600.c | 69 ++++++++++++++++++++++++++++++++++----- > 1 file changed, 61 insertions(+), 8 deletions(-) > > diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c > index bc3be5f3eae1..a6778c18274a 100644 > --- a/drivers/clk/clk-ast2600.c > +++ b/drivers/clk/clk-ast2600.c > @@ -168,6 +168,30 @@ static const struct clk_div_table ast2600_div_table[] = { > { 0 } > }; > > +static const struct clk_div_table ast2600_sd_div_a1_table[] = { Let's put the revision next to the ast2600 like the other tables: ast2600_a1_sd_div_table > + { 0x0, 2 }, > + { 0x1, 4 }, > + { 0x2, 6 }, > + { 0x3, 8 }, > + { 0x4, 10 }, > + { 0x5, 12 }, > + { 0x6, 14 }, > + { 0x7, 16 }, > + { 0 } > +}; > + > +static const struct clk_div_table ast2600_sd_div_a2_table[] = { For naming; can I propose we omit the revision for the A2/A3+ case? So this one would be called: ast2600_sd_div_table > + { 0x0, 2 }, > + { 0x1, 4 }, > + { 0x2, 6 }, > + { 0x3, 8 }, > + { 0x4, 10 }, > + { 0x5, 12 }, > + { 0x6, 14 }, > + { 0x7, 1 }, > + { 0 } > +}; > + > /* For hpll/dpll/epll/mpll */ > static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) > { > @@ -424,6 +448,11 @@ static const char *const emmc_extclk_parent_names[] = { > "mpll", > }; > > +static const char *const sd_extclk_parent_names[] = { > + "hclk", > + "apll", > +}; > + > static const char * const vclk_parent_names[] = { > "dpll", > "d1pll", > @@ -523,18 +552,42 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev) > return PTR_ERR(hw); > aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw; > > - /* SD/SDIO clock divider and gate */ > - hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0, > - scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0, > - &aspeed_g6_clk_lock); > + clk_hw_register_fixed_rate(NULL, "hclk", NULL, 0, 200000000); > + > + regmap_read(map, 0x310, &val); Use the #defines for the register number. > + hw = clk_hw_register_mux(dev, "sd_extclk_mux", > + sd_extclk_parent_names, > + ARRAY_SIZE(sd_extclk_parent_names), 0, > + scu_g6_base + ASPEED_G6_CLK_SELECTION4, 8, 1, > + 0, &aspeed_g6_clk_lock); > if (IS_ERR(hw)) > return PTR_ERR(hw); > - hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", > - 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, > - ast2600_div_table, > - &aspeed_g6_clk_lock); > + > + hw = clk_hw_register_gate(dev, "sd_extclk_gate", "sd_extclk_mux", > + 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, > + 31, 0, &aspeed_g6_clk_lock); > if (IS_ERR(hw)) > return PTR_ERR(hw); > + > + regmap_read(map, 0x14, &val); > + /* AST2600-A2/A3 clock divisor is different from AST2600-A1 */ > + if (((val & GENMASK(23, 16)) >> 16) >= 2) { I've got a little patch that I recommend you base your series on (feel free to include it in your series when posting v2 to make it self-contained): https://lore.kernel.org/all/20210922235449.213631-1-joel@jms.id.au/ With this one you can do: const struct clk_div_table* table; if (soc_rev >= 2) table = ast2600_sd_div_table; else table = ast2600_a1_sd_div_table; Then you don't need to duplicate the registration for each case: hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, table, &aspeed_g6_clk_lock); if (IS_ERR(hw)) return PTR_ERR(hw); > + /* AST2600-A2/A3 */ > + hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", > + 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, > + ast2600_sd_div_a2_table, > + &aspeed_g6_clk_lock); > + if (IS_ERR(hw)) > + return PTR_ERR(hw); > + } else { > + /* AST2600-A1 */ > + hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", > + 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, > + ast2600_sd_div_a1_table, > + &aspeed_g6_clk_lock); > + if (IS_ERR(hw)) > + return PTR_ERR(hw); > + } > aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw; > > /* MAC1/2 RMII 50MHz RCLK */ > -- > 2.17.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47199C433F5 for ; Thu, 23 Sep 2021 00:03:18 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 510DD61131 for ; Thu, 23 Sep 2021 00:03:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 510DD61131 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.ozlabs.org Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4HFFjv3lfgz2yPd for ; Thu, 23 Sep 2021 10:03:15 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=jms.id.au header.i=@jms.id.au header.a=rsa-sha256 header.s=google header.b=axUK3TKi; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::f2a; helo=mail-qv1-xf2a.google.com; envelope-from=joel.stan@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (1024-bit key; secure) header.d=jms.id.au header.i=@jms.id.au header.a=rsa-sha256 header.s=google header.b=axUK3TKi; dkim-atps=neutral Received: from mail-qv1-xf2a.google.com (mail-qv1-xf2a.google.com [IPv6:2607:f8b0:4864:20::f2a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4HFFj60p4tz2xvf; Thu, 23 Sep 2021 10:02:33 +1000 (AEST) Received: by mail-qv1-xf2a.google.com with SMTP id a13so3130027qvo.9; Wed, 22 Sep 2021 17:02:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jms.id.au; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=6za8hvNiMknZJLAQShJVN9k8ISMwqJs16dYb7Dbhy5I=; b=axUK3TKinPUn6A14DlJ5l75sUiHUS4zA4aiWlQb2xZNI7d/ZObmdqIZAwSJF6Qcx3X Bxveue63eavt8VkKBEHVhr5BP/mpZ4LxgbBBPS+If5Unl9y8AL15Fby7WugMV7wAbGrh 53pH+8O1hJDpwkBoww1i77rp+yHIn34Ss/oGc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=6za8hvNiMknZJLAQShJVN9k8ISMwqJs16dYb7Dbhy5I=; b=z9CGWLTz3qeC8YyRl9LJN42TIC0neH6sAz1XMOxt8rCldmWer4X5FE3kuhwhq5n5ON OC2YaK/5JtTECAaEFSDr67TdLKl9+dEbGUKEUa6SWVU1K7omOlx/K5vuqtIGL94cNy0o 3PkTwM9i9cnVmZI0etV8l2pGAGrm+68YEI8NPRRhKJgE4nk1+q96/p1GuiXdh1SaoWS/ qz80hq4bQ/sPuRrG0Z1haAYdTr9ixDySmkkEgTkmjwfxve809g8eOAQBhSXx3aj6icBC YvGLHkBER/ACy+0GxOhDjklpJlUEAGxtoq3NSKBYOxnVm/dN0r2CSmuWgKU4Guwg6LLb kAdw== X-Gm-Message-State: AOAM531auzNPUlVRwAxWCuhOcg51zwCtn9rj5flyZSZshVTYvh8QgOGk g+6v8kUPWKNzXmdSJT/j5iW7YtpjpVM5nS/QpXs= X-Google-Smtp-Source: ABdhPJwXwTQ1XjK5fncsWgEeP1jfN7ZYA6DFOZN7Q3GRnYZd8PBPLFUInicZnO0NAukPfyU/GXMHGGR33J3eFlRlg9s= X-Received: by 2002:ad4:54c6:: with SMTP id j6mr1959081qvx.17.1632355349480; Wed, 22 Sep 2021 17:02:29 -0700 (PDT) MIME-Version: 1.0 References: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> <20210922103116.30652-2-chin-ting_kuo@aspeedtech.com> In-Reply-To: <20210922103116.30652-2-chin-ting_kuo@aspeedtech.com> From: Joel Stanley Date: Thu, 23 Sep 2021 00:02:17 +0000 Message-ID: Subject: Re: [PATCH 01/10] clk: aspeed: ast2600: Porting sdhci clock source To: Chin-Ting Kuo Content-Type: text/plain; charset="UTF-8" X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree , linux-clk@vger.kernel.org, linux-aspeed , BMC-SW , Stephen Boyd , Steven Lee , Michael Turquette , linux-mmc , Adrian Hunter , Linux Kernel Mailing List , Andrew Jeffery , Rob Herring , OpenBMC Maillist , Linux ARM Errors-To: openbmc-bounces+openbmc=archiver.kernel.org@lists.ozlabs.org Sender: "openbmc" On Wed, 22 Sept 2021 at 10:31, Chin-Ting Kuo wrote: > > - There are two clock sources used to generate > SD/SDIO clock, APLL clock and HCLK (200MHz). > User can select which clock source should be used > by configuring SCU310[8]. > - The SD/SDIO clock divider selection table SCU310[30:28] > is different between AST2600-A1 and AST2600-A2/A3. > For AST2600-A1, 200MHz SD/SDIO clock cannot be > gotten by the dividers in SCU310[30:28] if APLL > is not the multiple of 200MHz and HCLK is 200MHz. > For AST2600-A2/A3, a new divider, "1", is added and > 200MHz SD/SDIO clock can be obtained by adopting HCLK > as clock source and setting SCU310[30:28] to 3b'111. > > Signed-off-by: Chin-Ting Kuo > --- > drivers/clk/clk-ast2600.c | 69 ++++++++++++++++++++++++++++++++++----- > 1 file changed, 61 insertions(+), 8 deletions(-) > > diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c > index bc3be5f3eae1..a6778c18274a 100644 > --- a/drivers/clk/clk-ast2600.c > +++ b/drivers/clk/clk-ast2600.c > @@ -168,6 +168,30 @@ static const struct clk_div_table ast2600_div_table[] = { > { 0 } > }; > > +static const struct clk_div_table ast2600_sd_div_a1_table[] = { Let's put the revision next to the ast2600 like the other tables: ast2600_a1_sd_div_table > + { 0x0, 2 }, > + { 0x1, 4 }, > + { 0x2, 6 }, > + { 0x3, 8 }, > + { 0x4, 10 }, > + { 0x5, 12 }, > + { 0x6, 14 }, > + { 0x7, 16 }, > + { 0 } > +}; > + > +static const struct clk_div_table ast2600_sd_div_a2_table[] = { For naming; can I propose we omit the revision for the A2/A3+ case? So this one would be called: ast2600_sd_div_table > + { 0x0, 2 }, > + { 0x1, 4 }, > + { 0x2, 6 }, > + { 0x3, 8 }, > + { 0x4, 10 }, > + { 0x5, 12 }, > + { 0x6, 14 }, > + { 0x7, 1 }, > + { 0 } > +}; > + > /* For hpll/dpll/epll/mpll */ > static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) > { > @@ -424,6 +448,11 @@ static const char *const emmc_extclk_parent_names[] = { > "mpll", > }; > > +static const char *const sd_extclk_parent_names[] = { > + "hclk", > + "apll", > +}; > + > static const char * const vclk_parent_names[] = { > "dpll", > "d1pll", > @@ -523,18 +552,42 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev) > return PTR_ERR(hw); > aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw; > > - /* SD/SDIO clock divider and gate */ > - hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0, > - scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0, > - &aspeed_g6_clk_lock); > + clk_hw_register_fixed_rate(NULL, "hclk", NULL, 0, 200000000); > + > + regmap_read(map, 0x310, &val); Use the #defines for the register number. > + hw = clk_hw_register_mux(dev, "sd_extclk_mux", > + sd_extclk_parent_names, > + ARRAY_SIZE(sd_extclk_parent_names), 0, > + scu_g6_base + ASPEED_G6_CLK_SELECTION4, 8, 1, > + 0, &aspeed_g6_clk_lock); > if (IS_ERR(hw)) > return PTR_ERR(hw); > - hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", > - 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, > - ast2600_div_table, > - &aspeed_g6_clk_lock); > + > + hw = clk_hw_register_gate(dev, "sd_extclk_gate", "sd_extclk_mux", > + 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, > + 31, 0, &aspeed_g6_clk_lock); > if (IS_ERR(hw)) > return PTR_ERR(hw); > + > + regmap_read(map, 0x14, &val); > + /* AST2600-A2/A3 clock divisor is different from AST2600-A1 */ > + if (((val & GENMASK(23, 16)) >> 16) >= 2) { I've got a little patch that I recommend you base your series on (feel free to include it in your series when posting v2 to make it self-contained): https://lore.kernel.org/all/20210922235449.213631-1-joel@jms.id.au/ With this one you can do: const struct clk_div_table* table; if (soc_rev >= 2) table = ast2600_sd_div_table; else table = ast2600_a1_sd_div_table; Then you don't need to duplicate the registration for each case: hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, table, &aspeed_g6_clk_lock); if (IS_ERR(hw)) return PTR_ERR(hw); > + /* AST2600-A2/A3 */ > + hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", > + 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, > + ast2600_sd_div_a2_table, > + &aspeed_g6_clk_lock); > + if (IS_ERR(hw)) > + return PTR_ERR(hw); > + } else { > + /* AST2600-A1 */ > + hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", > + 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, > + ast2600_sd_div_a1_table, > + &aspeed_g6_clk_lock); > + if (IS_ERR(hw)) > + return PTR_ERR(hw); > + } > aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw; > > /* MAC1/2 RMII 50MHz RCLK */ > -- > 2.17.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6170C433EF for ; Thu, 23 Sep 2021 00:04:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 753EF61131 for ; Thu, 23 Sep 2021 00:04:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 753EF61131 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=h7E2OE2ENUSrOy1nc5GLXwPSqpcmSn4koVRc/PIW0yI=; b=x0FCq/fW4Xbsgk Tuu8+2T2WICEKx/I8CWKMdFx4wmeIKYNNPjVZSQ8Sofs+wYHXnZR0cjFvYFD5JkIV7wBznbOyxx5v 2dHuzlGDmT5ip82g4YFIKG0jJlXhRNG7oUprGb4MM32JKKxeCEtk+ZDIGV34f2eOeU5TLSRi32UQZ 6lh7lFeJ8f2pzNwYxr8ExLi8cxXX6Hc9LZ38dvexLZwtY6+8Trtj8RYhRyOjdrUGMMcJiv39XFz0y jCKDkv2Jj8awrqKaIHgPMYEHc7E4QqWZ85SFB2Yx/xWNYRJpMD2Sjdl4/MZK4f9zOYeGB1PTN5JuG PLdXwghtbCuLs8J8JIHQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mTCCC-009yjH-Hb; Thu, 23 Sep 2021 00:02:36 +0000 Received: from mail-qv1-xf2f.google.com ([2607:f8b0:4864:20::f2f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mTCC7-009yiL-CQ for linux-arm-kernel@lists.infradead.org; Thu, 23 Sep 2021 00:02:33 +0000 Received: by mail-qv1-xf2f.google.com with SMTP id jo30so3158292qvb.3 for ; Wed, 22 Sep 2021 17:02:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jms.id.au; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=6za8hvNiMknZJLAQShJVN9k8ISMwqJs16dYb7Dbhy5I=; b=axUK3TKinPUn6A14DlJ5l75sUiHUS4zA4aiWlQb2xZNI7d/ZObmdqIZAwSJF6Qcx3X Bxveue63eavt8VkKBEHVhr5BP/mpZ4LxgbBBPS+If5Unl9y8AL15Fby7WugMV7wAbGrh 53pH+8O1hJDpwkBoww1i77rp+yHIn34Ss/oGc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=6za8hvNiMknZJLAQShJVN9k8ISMwqJs16dYb7Dbhy5I=; b=ZUL0hWIJ13fse2mfGz1BfyVRYladS/DvquHuF8S9RItfFQz8ces13G2iE2B7n+4Y96 ZWFhPh0xN3Ygcs+RQlfGCaPycc5ypOjxTiGIBBSRDllFgmdSwdWCGOOlguWM4Nrk003c nb8ssFZHJt0Cj/LcwonzTZbjx7mKfrPseZ0DzVFKC5LPxFS9pWaWcWhAW0fJsCn2PMfb rqTBEpFuvaRDsm7f/t4noELKCHL5LRhHZFDF8Zo36MJ4TeIIt15m7HO/9zb8BB/GtrJ/ 0nwgXSwQcOj+ZHwk8pqn1RVZLyQRVlnUoXpByqMoBSxykh0RdAHtm7rXFPZR9EvqoaSy F3Qw== X-Gm-Message-State: AOAM533rUrY1LaU3Jd049mB+S+skq8iKwa11fOEks3Y2A2AxMG4d1Z3A XAQpXH0gkyaqeVWJbwJ35ZumS5PMMeug83AxQzM= X-Google-Smtp-Source: ABdhPJwXwTQ1XjK5fncsWgEeP1jfN7ZYA6DFOZN7Q3GRnYZd8PBPLFUInicZnO0NAukPfyU/GXMHGGR33J3eFlRlg9s= X-Received: by 2002:ad4:54c6:: with SMTP id j6mr1959081qvx.17.1632355349480; Wed, 22 Sep 2021 17:02:29 -0700 (PDT) MIME-Version: 1.0 References: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com> <20210922103116.30652-2-chin-ting_kuo@aspeedtech.com> In-Reply-To: <20210922103116.30652-2-chin-ting_kuo@aspeedtech.com> From: Joel Stanley Date: Thu, 23 Sep 2021 00:02:17 +0000 Message-ID: Subject: Re: [PATCH 01/10] clk: aspeed: ast2600: Porting sdhci clock source To: Chin-Ting Kuo Cc: Rob Herring , Michael Turquette , Stephen Boyd , Adrian Hunter , linux-aspeed , OpenBMC Maillist , linux-mmc , devicetree , Linux ARM , Linux Kernel Mailing List , linux-clk@vger.kernel.org, Andrew Jeffery , BMC-SW , Steven Lee X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210922_170231_678168_33BF5E95 X-CRM114-Status: GOOD ( 29.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 22 Sept 2021 at 10:31, Chin-Ting Kuo wrote: > > - There are two clock sources used to generate > SD/SDIO clock, APLL clock and HCLK (200MHz). > User can select which clock source should be used > by configuring SCU310[8]. > - The SD/SDIO clock divider selection table SCU310[30:28] > is different between AST2600-A1 and AST2600-A2/A3. > For AST2600-A1, 200MHz SD/SDIO clock cannot be > gotten by the dividers in SCU310[30:28] if APLL > is not the multiple of 200MHz and HCLK is 200MHz. > For AST2600-A2/A3, a new divider, "1", is added and > 200MHz SD/SDIO clock can be obtained by adopting HCLK > as clock source and setting SCU310[30:28] to 3b'111. > > Signed-off-by: Chin-Ting Kuo > --- > drivers/clk/clk-ast2600.c | 69 ++++++++++++++++++++++++++++++++++----- > 1 file changed, 61 insertions(+), 8 deletions(-) > > diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c > index bc3be5f3eae1..a6778c18274a 100644 > --- a/drivers/clk/clk-ast2600.c > +++ b/drivers/clk/clk-ast2600.c > @@ -168,6 +168,30 @@ static const struct clk_div_table ast2600_div_table[] = { > { 0 } > }; > > +static const struct clk_div_table ast2600_sd_div_a1_table[] = { Let's put the revision next to the ast2600 like the other tables: ast2600_a1_sd_div_table > + { 0x0, 2 }, > + { 0x1, 4 }, > + { 0x2, 6 }, > + { 0x3, 8 }, > + { 0x4, 10 }, > + { 0x5, 12 }, > + { 0x6, 14 }, > + { 0x7, 16 }, > + { 0 } > +}; > + > +static const struct clk_div_table ast2600_sd_div_a2_table[] = { For naming; can I propose we omit the revision for the A2/A3+ case? So this one would be called: ast2600_sd_div_table > + { 0x0, 2 }, > + { 0x1, 4 }, > + { 0x2, 6 }, > + { 0x3, 8 }, > + { 0x4, 10 }, > + { 0x5, 12 }, > + { 0x6, 14 }, > + { 0x7, 1 }, > + { 0 } > +}; > + > /* For hpll/dpll/epll/mpll */ > static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) > { > @@ -424,6 +448,11 @@ static const char *const emmc_extclk_parent_names[] = { > "mpll", > }; > > +static const char *const sd_extclk_parent_names[] = { > + "hclk", > + "apll", > +}; > + > static const char * const vclk_parent_names[] = { > "dpll", > "d1pll", > @@ -523,18 +552,42 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev) > return PTR_ERR(hw); > aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw; > > - /* SD/SDIO clock divider and gate */ > - hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0, > - scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0, > - &aspeed_g6_clk_lock); > + clk_hw_register_fixed_rate(NULL, "hclk", NULL, 0, 200000000); > + > + regmap_read(map, 0x310, &val); Use the #defines for the register number. > + hw = clk_hw_register_mux(dev, "sd_extclk_mux", > + sd_extclk_parent_names, > + ARRAY_SIZE(sd_extclk_parent_names), 0, > + scu_g6_base + ASPEED_G6_CLK_SELECTION4, 8, 1, > + 0, &aspeed_g6_clk_lock); > if (IS_ERR(hw)) > return PTR_ERR(hw); > - hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", > - 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, > - ast2600_div_table, > - &aspeed_g6_clk_lock); > + > + hw = clk_hw_register_gate(dev, "sd_extclk_gate", "sd_extclk_mux", > + 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, > + 31, 0, &aspeed_g6_clk_lock); > if (IS_ERR(hw)) > return PTR_ERR(hw); > + > + regmap_read(map, 0x14, &val); > + /* AST2600-A2/A3 clock divisor is different from AST2600-A1 */ > + if (((val & GENMASK(23, 16)) >> 16) >= 2) { I've got a little patch that I recommend you base your series on (feel free to include it in your series when posting v2 to make it self-contained): https://lore.kernel.org/all/20210922235449.213631-1-joel@jms.id.au/ With this one you can do: const struct clk_div_table* table; if (soc_rev >= 2) table = ast2600_sd_div_table; else table = ast2600_a1_sd_div_table; Then you don't need to duplicate the registration for each case: hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, table, &aspeed_g6_clk_lock); if (IS_ERR(hw)) return PTR_ERR(hw); > + /* AST2600-A2/A3 */ > + hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", > + 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, > + ast2600_sd_div_a2_table, > + &aspeed_g6_clk_lock); > + if (IS_ERR(hw)) > + return PTR_ERR(hw); > + } else { > + /* AST2600-A1 */ > + hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", > + 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, > + ast2600_sd_div_a1_table, > + &aspeed_g6_clk_lock); > + if (IS_ERR(hw)) > + return PTR_ERR(hw); > + } > aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw; > > /* MAC1/2 RMII 50MHz RCLK */ > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel