From: Joel Stanley <joel@jms.id.au>
To: Andrew Jeffery <andrew@aj.id.au>
Cc: "Bills, Jason M" <jason.m.bills@linux.intel.com>,
"openbmc@lists.ozlabs.org" <openbmc@lists.ozlabs.org>
Subject: Re: [PATCH 1/2] pinctrl: aspeed: Enable pass-through on GPIOE1 and GPIOE3 free
Date: Mon, 7 Feb 2022 06:45:22 +0000 [thread overview]
Message-ID: <CACPK8Xf+6cLOWNYpMH21KDxRX3w5W=EwheTwL-ZktJvbG_pGeg@mail.gmail.com> (raw)
In-Reply-To: <70fda031-ea0a-4155-81d4-74f398134bf8@www.fastmail.com>
On Wed, 2 Feb 2022 at 22:49, Andrew Jeffery <andrew@aj.id.au> wrote:
>
>
>
> On Thu, 3 Feb 2022, at 06:29, Bills, Jason M wrote:
> > This change adds a gpio_disable_free() implementation that checks
> > if the GPIO being freed is GPIOE1 (33) or GPIOE3 (35) and will
> > re-enable the pass-through mux.
>
> Okay. So trying to pull back from the implementation for a moment:
>
> Perhaps we can view pass-through as a property on a pair of GPIOs, rather than a mux state? I think it would be better if we could, for instance, annotate this in the devicetree?
>
> If we did that I don't think we're require this awkward and pin-specific implementation of the free callback for GPIOs.
>
> If pass-through is enabled it puts constraints on how the pins are used if they're requested as GPIOs, but we can add those dynamic checks in the GPIO driver.
>
> Let me think about it some more.
>
> Thanks for surfacing the patch.
This is for the kernel, I assume.
Jason, you should send the patch to the upstream lists (use
get_maintainers.pl) for review.
Cheers,
Joel
next prev parent reply other threads:[~2022-02-07 6:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-02 19:59 [PATCH 1/2] pinctrl: aspeed: Enable pass-through on GPIOE1 and GPIOE3 free Bills, Jason M
2022-02-02 22:49 ` Andrew Jeffery
2022-02-02 23:14 ` Zev Weiss
2022-02-07 6:45 ` Joel Stanley [this message]
2022-02-24 21:03 ` Bills, Jason M
2022-02-25 4:49 ` Joel Stanley
2022-02-25 15:22 ` Bills, Jason M
2022-02-28 0:04 ` Andrew Jeffery
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