From mboxrd@z Thu Jan 1 00:00:00 1970 From: Linus Walleij Subject: Re: [PATCH v2 1/9] drivers: pinctrl: add driver for Allwinner H5 SoC Date: Mon, 30 Jan 2017 16:13:50 +0100 Message-ID: References: <20170126154859.55855-1-icenowy@aosc.xyz> <20170126154859.55855-2-icenowy@aosc.xyz> Reply-To: linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20170126154859.55855-2-icenowy-ymACFijhrKM@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Icenowy Zheng Cc: Maxime Ripard , Chen-Yu Tsai , Vinod Koul , Mark Brown , Jaroslav Kysela , Andre Przywara , linux-clk , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , dmaengine-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, "alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org" , linux-sunxi List-Id: linux-gpio@vger.kernel.org On Thu, Jan 26, 2017 at 4:48 PM, Icenowy Zheng wrote: > Based on the Allwinner H5 datasheet and the pinctrl driver of the > backward-compatible H3 this introduces the pin multiplex assignments for > the H5 SoC. > > H5 introduced some more pin functions (e.g. three more groups of TS > pins, and one more groups of SIM pins) than H3. > > Signed-off-by: Icenowy Zheng > --- > Changes in v2: > - Fixed interrupt banks. (There's one more GPIO banks (PF) that can do > interrupt handling on H5) Patch applied with Maxime's ACK. Yours, Linus Walleij From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753687AbdA3POb (ORCPT ); Mon, 30 Jan 2017 10:14:31 -0500 Received: from mail-io0-f169.google.com ([209.85.223.169]:35022 "EHLO mail-io0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753638AbdA3PO0 (ORCPT ); Mon, 30 Jan 2017 10:14:26 -0500 MIME-Version: 1.0 In-Reply-To: <20170126154859.55855-2-icenowy@aosc.xyz> References: <20170126154859.55855-1-icenowy@aosc.xyz> <20170126154859.55855-2-icenowy@aosc.xyz> From: Linus Walleij Date: Mon, 30 Jan 2017 16:13:50 +0100 Message-ID: Subject: Re: [PATCH v2 1/9] drivers: pinctrl: add driver for Allwinner H5 SoC To: Icenowy Zheng Cc: Maxime Ripard , Chen-Yu Tsai , Vinod Koul , Mark Brown , Jaroslav Kysela , Andre Przywara , linux-clk , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-gpio@vger.kernel.org" , dmaengine@vger.kernel.org, "alsa-devel@alsa-project.org" , linux-sunxi Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 26, 2017 at 4:48 PM, Icenowy Zheng wrote: > Based on the Allwinner H5 datasheet and the pinctrl driver of the > backward-compatible H3 this introduces the pin multiplex assignments for > the H5 SoC. > > H5 introduced some more pin functions (e.g. three more groups of TS > pins, and one more groups of SIM pins) than H3. > > Signed-off-by: Icenowy Zheng > --- > Changes in v2: > - Fixed interrupt banks. (There's one more GPIO banks (PF) that can do > interrupt handling on H5) Patch applied with Maxime's ACK. Yours, Linus Walleij From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-Version: 1.0 In-Reply-To: <20170126154859.55855-2-icenowy@aosc.xyz> References: <20170126154859.55855-1-icenowy@aosc.xyz> <20170126154859.55855-2-icenowy@aosc.xyz> From: Linus Walleij Date: Mon, 30 Jan 2017 16:13:50 +0100 Message-ID: Subject: Re: [PATCH v2 1/9] drivers: pinctrl: add driver for Allwinner H5 SoC To: Icenowy Zheng List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , "alsa-devel@alsa-project.org" , Vinod Koul , Andre Przywara , linux-sunxi , "linux-kernel@vger.kernel.org" , Jaroslav Kysela , "linux-gpio@vger.kernel.org" , Chen-Yu Tsai , Mark Brown , dmaengine@vger.kernel.org, Maxime Ripard , linux-clk , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+mturquette=baylibre.com@lists.infradead.org List-ID: On Thu, Jan 26, 2017 at 4:48 PM, Icenowy Zheng wrote: > Based on the Allwinner H5 datasheet and the pinctrl driver of the > backward-compatible H3 this introduces the pin multiplex assignments for > the H5 SoC. > > H5 introduced some more pin functions (e.g. three more groups of TS > pins, and one more groups of SIM pins) than H3. > > Signed-off-by: Icenowy Zheng > --- > Changes in v2: > - Fixed interrupt banks. (There's one more GPIO banks (PF) that can do > interrupt handling on H5) Patch applied with Maxime's ACK. Yours, Linus Walleij _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: linus.walleij@linaro.org (Linus Walleij) Date: Mon, 30 Jan 2017 16:13:50 +0100 Subject: [PATCH v2 1/9] drivers: pinctrl: add driver for Allwinner H5 SoC In-Reply-To: <20170126154859.55855-2-icenowy@aosc.xyz> References: <20170126154859.55855-1-icenowy@aosc.xyz> <20170126154859.55855-2-icenowy@aosc.xyz> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Jan 26, 2017 at 4:48 PM, Icenowy Zheng wrote: > Based on the Allwinner H5 datasheet and the pinctrl driver of the > backward-compatible H3 this introduces the pin multiplex assignments for > the H5 SoC. > > H5 introduced some more pin functions (e.g. three more groups of TS > pins, and one more groups of SIM pins) than H3. > > Signed-off-by: Icenowy Zheng > --- > Changes in v2: > - Fixed interrupt banks. (There's one more GPIO banks (PF) that can do > interrupt handling on H5) Patch applied with Maxime's ACK. Yours, Linus Walleij