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From: Linus Walleij <linus.walleij@linaro.org>
To: Peng Zhou <peng.zhou@mediatek.com>,
	linux-block <linux-block@vger.kernel.org>,
	Eric Biggers <ebiggers@kernel.org>
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
	Chaotian Jing <chaotian.jing@mediatek.com>,
	linux-mmc <linux-mmc@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Satya Tangirala <satyat@google.com>,
	Wulin Li <wulin.li@mediatek.com>
Subject: Re: [PATCH v2 2/4] mmc: Mediatek: enable crypto hardware engine
Date: Thu, 11 Mar 2021 14:48:23 +0100	[thread overview]
Message-ID: <CACRpkdYTkW7b9SFEY6Ubq4NicgR_5ewQMjE2zHvGbgxYadhHQQ@mail.gmail.com> (raw)
In-Reply-To: <20210309015750.6283-1-peng.zhou@mediatek.com>

Hi Peng,

thanks for your patch!

On Tue, Mar 9, 2021 at 3:06 AM Peng Zhou <peng.zhou@mediatek.com> wrote:

> Use SMC call enable hardware crypto engine
> due to it only be changed in ATF(EL3).
>
> Signed-off-by: Peng Zhou <peng.zhou@mediatek.com>

Unfortunately this commit message is way to short to
understand what is going on, and has a lot of assumed
previous knowledge.

Can you expand the commit message so that anyone
who just know MMC and some SoC basics can understand
what an SMC call and and what ATF(EL3) means?

I assume this some kind of inline encryption?

I think maybe linux-block mailing list need to be involved
because there is certain a Linux standard way of setting
up inline encryption for the block layer.

For example: how is the key to be used derived?
How is the device unlocked in the first place?

If I insert a LUKS encrypted harddrive in a Linux machine
the whole system is pretty much aware of how this should
be handled and everything "just works", I enter a pass
phrase and off it goes. I can use symmetric keys as well.
How is this stuff done for this hardware?

> +       /*
> +        * 1: MSDC_AES_CTL_INIT
> +        * 4: cap_id, no-meaning now
> +        * 1: cfg_id, we choose the second cfg group
> +        */
> +       if (mmc->caps2 & MMC_CAP2_CRYPTO)
> +               arm_smccc_smc(MTK_SIP_MMC_CONTROL,
> +                             1, 4, 1, 0, 0, 0, 0, &smccc_res);

The same as above: these comments assume that everyone
already knows what is going on.

AES encryption requires a key and I don't see the driver
setting up any key. How is the code in this file:
drivers/mmc/core/crypto.c
interacting with your driver?
drivers/mmc/host/cqhci-crypto.c
is used by SDHCI and is quite readable and I see what is going on.
For example it contains functions like:
cqhci_crypto_program_key()
cqhci_crypto_keyslot_program()
cqhci_crypto_clear_keyslot()
cqhci_crypto_keyslot_evict()
cqhci_find_blk_crypto_mode()

MMC_CAP2_CRYPTO is used as a sign that the driver
can do inline encryption, then devm_blk_ksm_init() is called
to initialize a block encryption abstraction with the block layer.
Ops are registered using
struct blk_ksm_ll_ops cqhci_ksm_ops.

This is very straight forward.

But where does all the above happen for this driver?

I get the feeling that some magic is happening in outoftree
patches or in the secure world, and that is not how we do
these things, you have to use the frameworks.

Yours,
Linus Walleij

  parent reply	other threads:[~2021-03-11 13:49 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-09  1:57 [PATCH v2 2/4] mmc: Mediatek: enable crypto hardware engine Peng Zhou
2021-03-11 11:16 ` Ulf Hansson
2021-03-11 13:48 ` Linus Walleij [this message]
2021-03-11 19:08   ` Eric Biggers
2021-03-12  9:05     ` Ulf Hansson
2021-03-12 10:47       ` Arnd Bergmann
     [not found]       ` <1615884533.21508.118.camel@mbjsdccf07>
2021-03-16 10:09         ` Ulf Hansson
     [not found]           ` <1615893329.21508.128.camel@mbjsdccf07>
2021-03-16 13:55             ` Ulf Hansson
2021-03-22 13:45               ` Linus Walleij
2021-03-23 13:37                 ` Ulf Hansson
2021-03-15 13:41     ` Linus Walleij
2021-03-15 23:02       ` Eric Biggers

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