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s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=CLYJHfRhPFodZ6Fi5lSVxvreBLh68tBGDsvpRh31BmM=; b=IsrN39XVkK5/YsCiCVmH6SqfAiCeOWvsMRs5gWl5i5ubpFZQr+nJTCrFcjqh0m6K0D 0dzbJUuCRf7+qIHlHIZt6rAI6ur8VokRNXjbHSLFNItS3MXK5SCvP7rd/76sb7OZOJJg DmO/MDUVpI5Ivyij+OOcWjjUVKO8nY0uoqRHcUnko5rcGYmChaQ9fvSuXtxDDGMZlSJw k/1hwseOUaf9ckagH+3rqYWK30a6X003l3BxynelrUNKfBOOFn3HftqJroi7TnNXscY9 rVWepNrS+mmCDlYYFfqyoWlUDFbWzc0v4MPiCo5yQrDCakb2jWcQgAsprCaYA6Ye7EHf yeWw== X-Gm-Message-State: AOAM531VFWmnbeRbc6xn7PNBtqH5DGujllYf6fRCJH0Tp5taFJcGhzfO SSwEya32ttLcSuXufutsWhcVOkjIbhg28j/DxRRXug== X-Google-Smtp-Source: ABdhPJzO3vddWzlxVwbSjhs7wM8YcxZNlcu1oRXiy0c2zo5EAmXsiB3nRXD86YSembDKOGKkAzOAiGge/QieLQfl9Wk= X-Received: by 2002:a05:6512:74a:: with SMTP id c10mr9817129lfs.586.1614609506817; Mon, 01 Mar 2021 06:38:26 -0800 (PST) MIME-Version: 1.0 References: <20210210185532.8425-1-ardb@kernel.org> In-Reply-To: <20210210185532.8425-1-ardb@kernel.org> From: Linus Walleij Date: Mon, 1 Mar 2021 15:38:15 +0100 Message-ID: Subject: Re: [PATCH v2 0/3] ARM: v7: get rid of boot time mini stack To: Ard Biesheuvel X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210301_093828_345993_153B13BD X-CRM114-Status: GOOD ( 20.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , Android Kernel Team , Russell King , Linux ARM , Nicolas Pitre Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Feb 10, 2021 at 7:55 PM Ard Biesheuvel wrote: > The v7 boot code uses a small chunk of BSS to preserve some register > contents across a call to v7_invalidate_l1 that occurs with the MMU and > caches disabled. Memory accesses in such cases are tricky on v7+, given > that the architecture permits some unintuitive behaviors (it is > implementation defined whether accesses done with the MMU and caches off > may hit in the caches). Also, cache invalidation is not safe under > virtualization if the intent is to retain stores issued directly to DRAM, > as the hypervisor may upgrade invalidate operations to clean+invalidate, > resulting in DRAM contents to be overwritte by the dirty cachelines that > we were trying to evict in the first place. > > So let's address this issue, by removing the need for this stack to > exist in the first place: v7_invalidate_l1 can be rewritten to use fewer > registers, which means fewer registers need to be preserved, and we have > enough spare registers available. > > Patch #1 adds a missing ISB. This patch is included separately so it can > be backported if desired. > > Patch #2 rewrites v7_invalidate_l1 so it only uses 5 registers (not > counting lr which it must preserve as well) > > Patch #3 updates the callers to use spare registers instead of the mini > stack to stash the values that need to be preserved across the calls to > v7_invalidate_l1. > > Changes since v1: > - use correct stop condition in outer loop (cc not mi) > - bring back ENDPROC() in patch #3 > - add Nico's ack This looks good to me, so FWIW: Acked-by: Linus Walleij Yours, Linus Walleij _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel