All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH 0/2] Couple of fixes for pinctrl-armada-37xx
@ 2017-06-23 12:29 ` Gregory CLEMENT
  0 siblings, 0 replies; 12+ messages in thread
From: Gregory CLEMENT @ 2017-06-23 12:29 UTC (permalink / raw)
  To: Linus Walleij, linux-gpio, linux-kernel
  Cc: Ken Ma, Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
	Gregory CLEMENT, Thomas Petazzoni, linux-arm-kernel,
	Stefan Roese, Nadav Haklai, Victor Gu, Marcin Wojtas,
	Wilson Ding, Hua Jing, Neta Zur Hershkovits

Hi,

Ken Ma found few issues in the driver. I wrote the first fix is based
on his report and the second one was written for U-Boot but as they
use the same driver it can be applied on linux too.

thanks,

Gregory

Gregory CLEMENT (1):
  pinctrl: armada-37xx: Fix number of pin in sdio_sb

Ken Ma (1):
  pinctrl: armada-37xx: Fix uart2 group selection register mask

 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

-- 
2.11.0


^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH 0/2] Couple of fixes for pinctrl-armada-37xx
@ 2017-06-23 12:29 ` Gregory CLEMENT
  0 siblings, 0 replies; 12+ messages in thread
From: Gregory CLEMENT @ 2017-06-23 12:29 UTC (permalink / raw)
  To: linux-arm-kernel

Hi,

Ken Ma found few issues in the driver. I wrote the first fix is based
on his report and the second one was written for U-Boot but as they
use the same driver it can be applied on linux too.

thanks,

Gregory

Gregory CLEMENT (1):
  pinctrl: armada-37xx: Fix number of pin in sdio_sb

Ken Ma (1):
  pinctrl: armada-37xx: Fix uart2 group selection register mask

 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

-- 
2.11.0

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH 1/2] pinctrl: armada-37xx: Fix uart2 group selection register mask
  2017-06-23 12:29 ` Gregory CLEMENT
@ 2017-06-23 12:29   ` Gregory CLEMENT
  -1 siblings, 0 replies; 12+ messages in thread
From: Gregory CLEMENT @ 2017-06-23 12:29 UTC (permalink / raw)
  To: Linus Walleij, linux-gpio, linux-kernel
  Cc: Ken Ma, Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
	Gregory CLEMENT, Thomas Petazzoni, linux-arm-kernel,
	Stefan Roese, Nadav Haklai, Victor Gu, Marcin Wojtas,
	Wilson Ding, Hua Jing, Neta Zur Hershkovits

From: Ken Ma <make@marvell.com>

If north bridge selection register bit1 is clear, pins [10:8] are for
SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
and CTSn, so bit1 should be added to uart2 group and it must be set
for both "gpio" and "uart" functions of uart2 group.

Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 5c96f5558310..2fb1c67886fc 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -147,8 +147,9 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
 	PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
 	PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
 	PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
-	PIN_GRP_EXTRA("uart2", 9, 2, BIT(13) | BIT(14) | BIT(19),
-		      BIT(13) | BIT(14), BIT(19), 18, 2, "gpio", "uart"),
+	PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
+		      BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
+		      18, 2, "gpio", "uart"),
 	PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
 	PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
 	PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
-- 
2.11.0

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 1/2] pinctrl: armada-37xx: Fix uart2 group selection register mask
@ 2017-06-23 12:29   ` Gregory CLEMENT
  0 siblings, 0 replies; 12+ messages in thread
From: Gregory CLEMENT @ 2017-06-23 12:29 UTC (permalink / raw)
  To: linux-arm-kernel

From: Ken Ma <make@marvell.com>

If north bridge selection register bit1 is clear, pins [10:8] are for
SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
and CTSn, so bit1 should be added to uart2 group and it must be set
for both "gpio" and "uart" functions of uart2 group.

Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 5c96f5558310..2fb1c67886fc 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -147,8 +147,9 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
 	PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
 	PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
 	PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
-	PIN_GRP_EXTRA("uart2", 9, 2, BIT(13) | BIT(14) | BIT(19),
-		      BIT(13) | BIT(14), BIT(19), 18, 2, "gpio", "uart"),
+	PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
+		      BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
+		      18, 2, "gpio", "uart"),
 	PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
 	PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
 	PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
-- 
2.11.0

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 2/2] pinctrl: armada-37xx: Fix number of pin in sdio_sb
  2017-06-23 12:29 ` Gregory CLEMENT
@ 2017-06-23 12:29   ` Gregory CLEMENT
  -1 siblings, 0 replies; 12+ messages in thread
From: Gregory CLEMENT @ 2017-06-23 12:29 UTC (permalink / raw)
  To: Linus Walleij, linux-gpio, linux-kernel
  Cc: Ken Ma, Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
	Gregory CLEMENT, Thomas Petazzoni, linux-arm-kernel,
	Stefan Roese, Nadav Haklai, Victor Gu, Marcin Wojtas,
	Wilson Ding, Hua Jing, Neta Zur Hershkovits

The sdio_sb group is composed of 6 pins and not 5.

Reported-by: Ken Ma <make@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 2fb1c67886fc..addc130159fc 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -160,8 +160,8 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
 	PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
 	PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
-	PIN_GRP_GPIO("sdio_sb", 24, 5, BIT(2), "sdio"),
-	PIN_GRP_EXTRA("rgmii", 6, 14, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"),
+	PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
+	PIN_GRP_EXTRA("rgmii", 6, 12, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"),
 	PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
 	PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
 	PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
-- 
2.11.0


^ permalink raw reply related	[flat|nested] 12+ messages in thread
* [PATCH 2/2] pinctrl: armada-37xx: Fix number of pin in sdio_sb
@ 2017-06-23 12:29   ` Gregory CLEMENT
  0 siblings, 0 replies; 12+ messages in thread
From: Gregory CLEMENT @ 2017-06-23 12:29 UTC (permalink / raw)
  To: linux-arm-kernel

The sdio_sb group is composed of 6 pins and not 5.

Reported-by: Ken Ma <make@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 2fb1c67886fc..addc130159fc 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -160,8 +160,8 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
 	PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
 	PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
-	PIN_GRP_GPIO("sdio_sb", 24, 5, BIT(2), "sdio"),
-	PIN_GRP_EXTRA("rgmii", 6, 14, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"),
+	PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
+	PIN_GRP_EXTRA("rgmii", 6, 12, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"),
 	PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
 	PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
 	PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
-- 
2.11.0

^ permalink raw reply related	[flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] pinctrl: armada-37xx: Fix uart2 group selection register mask
  2017-06-23 12:29   ` Gregory CLEMENT
  (?)
@ 2017-06-29  9:44     ` Linus Walleij
  -1 siblings, 0 replies; 12+ messages in thread
From: Linus Walleij @ 2017-06-29  9:44 UTC (permalink / raw)
  To: Gregory CLEMENT
  Cc: linux-gpio, linux-kernel, Ken Ma, Jason Cooper, Andrew Lunn,
	Sebastian Hesselbarth, Thomas Petazzoni, linux-arm-kernel,
	Stefan Roese, Nadav Haklai, Victor Gu, Marcin Wojtas,
	Wilson Ding, Hua Jing, Neta Zur Hershkovits

On Fri, Jun 23, 2017 at 2:29 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:

> From: Ken Ma <make@marvell.com>
>
> If north bridge selection register bit1 is clear, pins [10:8] are for
> SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
> GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
> and CTSn, so bit1 should be added to uart2 group and it must be set
> for both "gpio" and "uart" functions of uart2 group.
>
> Signed-off-by: Ken Ma <make@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Patch applied.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] pinctrl: armada-37xx: Fix uart2 group selection register mask
@ 2017-06-29  9:44     ` Linus Walleij
  0 siblings, 0 replies; 12+ messages in thread
From: Linus Walleij @ 2017-06-29  9:44 UTC (permalink / raw)
  To: Gregory CLEMENT
  Cc: linux-gpio, linux-kernel, Ken Ma, Jason Cooper, Andrew Lunn,
	Sebastian Hesselbarth, Thomas Petazzoni, linux-arm-kernel,
	Stefan Roese, Nadav Haklai, Victor Gu, Marcin Wojtas,
	Wilson Ding, Hua Jing, Neta Zur Hershkovits

On Fri, Jun 23, 2017 at 2:29 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:

> From: Ken Ma <make@marvell.com>
>
> If north bridge selection register bit1 is clear, pins [10:8] are for
> SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
> GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
> and CTSn, so bit1 should be added to uart2 group and it must be set
> for both "gpio" and "uart" functions of uart2 group.
>
> Signed-off-by: Ken Ma <make@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Patch applied.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH 1/2] pinctrl: armada-37xx: Fix uart2 group selection register mask
@ 2017-06-29  9:44     ` Linus Walleij
  0 siblings, 0 replies; 12+ messages in thread
From: Linus Walleij @ 2017-06-29  9:44 UTC (permalink / raw)
  To: linux-arm-kernel

On Fri, Jun 23, 2017 at 2:29 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:

> From: Ken Ma <make@marvell.com>
>
> If north bridge selection register bit1 is clear, pins [10:8] are for
> SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
> GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
> and CTSn, so bit1 should be added to uart2 group and it must be set
> for both "gpio" and "uart" functions of uart2 group.
>
> Signed-off-by: Ken Ma <make@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Patch applied.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] pinctrl: armada-37xx: Fix number of pin in sdio_sb
  2017-06-23 12:29   ` Gregory CLEMENT
  (?)
@ 2017-06-29  9:45     ` Linus Walleij
  -1 siblings, 0 replies; 12+ messages in thread
From: Linus Walleij @ 2017-06-29  9:45 UTC (permalink / raw)
  To: Gregory CLEMENT
  Cc: linux-gpio, linux-kernel, Ken Ma, Jason Cooper, Andrew Lunn,
	Sebastian Hesselbarth, Thomas Petazzoni, linux-arm-kernel,
	Stefan Roese, Nadav Haklai, Victor Gu, Marcin Wojtas,
	Wilson Ding, Hua Jing, Neta Zur Hershkovits

On Fri, Jun 23, 2017 at 2:29 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:

> The sdio_sb group is composed of 6 pins and not 5.
>
> Reported-by: Ken Ma <make@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Patch applied.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 12+ messages in thread
* Re: [PATCH 2/2] pinctrl: armada-37xx: Fix number of pin in sdio_sb
@ 2017-06-29  9:45     ` Linus Walleij
  0 siblings, 0 replies; 12+ messages in thread
From: Linus Walleij @ 2017-06-29  9:45 UTC (permalink / raw)
  To: Gregory CLEMENT
  Cc: linux-gpio, linux-kernel, Ken Ma, Jason Cooper, Andrew Lunn,
	Sebastian Hesselbarth, Thomas Petazzoni, linux-arm-kernel,
	Stefan Roese, Nadav Haklai, Victor Gu, Marcin Wojtas,
	Wilson Ding, Hua Jing, Neta Zur Hershkovits

On Fri, Jun 23, 2017 at 2:29 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:

> The sdio_sb group is composed of 6 pins and not 5.
>
> Reported-by: Ken Ma <make@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Patch applied.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 12+ messages in thread
* [PATCH 2/2] pinctrl: armada-37xx: Fix number of pin in sdio_sb
@ 2017-06-29  9:45     ` Linus Walleij
  0 siblings, 0 replies; 12+ messages in thread
From: Linus Walleij @ 2017-06-29  9:45 UTC (permalink / raw)
  To: linux-arm-kernel

On Fri, Jun 23, 2017 at 2:29 PM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:

> The sdio_sb group is composed of 6 pins and not 5.
>
> Reported-by: Ken Ma <make@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Patch applied.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 12+ messages in thread
end of thread, other threads:[~2017-06-29  9:45 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-23 12:29 [PATCH 0/2] Couple of fixes for pinctrl-armada-37xx Gregory CLEMENT
2017-06-23 12:29 ` Gregory CLEMENT
2017-06-23 12:29 ` [PATCH 1/2] pinctrl: armada-37xx: Fix uart2 group selection register mask Gregory CLEMENT
2017-06-23 12:29   ` Gregory CLEMENT
2017-06-29  9:44   ` Linus Walleij
2017-06-29  9:44     ` Linus Walleij
2017-06-29  9:44     ` Linus Walleij
2017-06-23 12:29 ` [PATCH 2/2] pinctrl: armada-37xx: Fix number of pin in sdio_sb Gregory CLEMENT
2017-06-23 12:29   ` Gregory CLEMENT
2017-06-29  9:45   ` Linus Walleij
2017-06-29  9:45     ` Linus Walleij
2017-06-29  9:45     ` Linus Walleij

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.