From mboxrd@z Thu Jan 1 00:00:00 1970 From: Linus Walleij Subject: Re: [PATCH v4 6/9] pinctrl: Add IRQ support to STM32 gpios Date: Wed, 7 Sep 2016 23:06:12 +0200 Message-ID: References: <1473180341-1999-1-git-send-email-alexandre.torgue@st.com> <1473180341-1999-7-git-send-email-alexandre.torgue@st.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: Received: from mail-oi0-f45.google.com ([209.85.218.45]:33205 "EHLO mail-oi0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751304AbcIGVGN (ORCPT ); Wed, 7 Sep 2016 17:06:13 -0400 Received: by mail-oi0-f45.google.com with SMTP id y2so44273571oie.0 for ; Wed, 07 Sep 2016 14:06:13 -0700 (PDT) In-Reply-To: <1473180341-1999-7-git-send-email-alexandre.torgue@st.com> Sender: linux-gpio-owner@vger.kernel.org List-Id: linux-gpio@vger.kernel.org To: Alexandre TORGUE Cc: Maxime Coquelin , Thomas Gleixner , Jason Cooper , Marc Zyngier , Mark Rutland , Rob Herring , "linux-gpio@vger.kernel.org" , Arnd Bergmann , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , Daniel Thompson , Bruno Herrera , Lee Jones On Tue, Sep 6, 2016 at 6:45 PM, Alexandre TORGUE wrote: > This patch adds IRQ support to STM32 gpios. > > The EXTI controller has 16 lines dedicated to GPIOs. > EXTI line n can be connected to only line n of one of the GPIO ports, for > example EXTI0 can be connected to either PA0, or PB0, or PC0... > This port selection is done by specifying the port number into System > Config registers. > > Signed-off-by: Maxime Coquelin > Signed-off-by: Alexandre TORGUE > +++ b/drivers/pinctrl/stm32/Kconfig > @@ -6,6 +6,8 @@ config PINCTRL_STM32 > select PINMUX > select GENERIC_PINCONF > select GPIOLIB > + select GPIOLIB_IRQCHIP But you're not really using GPIOLIB_IRQCHIP. You have a different, super-complex irqchip in use. So just don't select this. > + bank->gpio_chip.irqdomain = irq_domain_create_hierarchy(pctl->domain, > + 0, STM32_GPIO_IRQ_LINE, bank->fwnode, > + &stm32_gpio_domain_ops, bank); Don't use that irqdomain pointer inside the gpio_chip. Instead declare the irqdomain pointer inside struct stm32_gpio_bank or something like that. Yours, Linus Walleij From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754646AbcIGVGY (ORCPT ); Wed, 7 Sep 2016 17:06:24 -0400 Received: from mail-oi0-f54.google.com ([209.85.218.54]:33205 "EHLO mail-oi0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752418AbcIGVGN (ORCPT ); Wed, 7 Sep 2016 17:06:13 -0400 MIME-Version: 1.0 In-Reply-To: <1473180341-1999-7-git-send-email-alexandre.torgue@st.com> References: <1473180341-1999-1-git-send-email-alexandre.torgue@st.com> <1473180341-1999-7-git-send-email-alexandre.torgue@st.com> From: Linus Walleij Date: Wed, 7 Sep 2016 23:06:12 +0200 Message-ID: Subject: Re: [PATCH v4 6/9] pinctrl: Add IRQ support to STM32 gpios To: Alexandre TORGUE Cc: Maxime Coquelin , Thomas Gleixner , Jason Cooper , Marc Zyngier , Mark Rutland , Rob Herring , "linux-gpio@vger.kernel.org" , Arnd Bergmann , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , Daniel Thompson , Bruno Herrera , Lee Jones Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 6, 2016 at 6:45 PM, Alexandre TORGUE wrote: > This patch adds IRQ support to STM32 gpios. > > The EXTI controller has 16 lines dedicated to GPIOs. > EXTI line n can be connected to only line n of one of the GPIO ports, for > example EXTI0 can be connected to either PA0, or PB0, or PC0... > This port selection is done by specifying the port number into System > Config registers. > > Signed-off-by: Maxime Coquelin > Signed-off-by: Alexandre TORGUE > +++ b/drivers/pinctrl/stm32/Kconfig > @@ -6,6 +6,8 @@ config PINCTRL_STM32 > select PINMUX > select GENERIC_PINCONF > select GPIOLIB > + select GPIOLIB_IRQCHIP But you're not really using GPIOLIB_IRQCHIP. You have a different, super-complex irqchip in use. So just don't select this. > + bank->gpio_chip.irqdomain = irq_domain_create_hierarchy(pctl->domain, > + 0, STM32_GPIO_IRQ_LINE, bank->fwnode, > + &stm32_gpio_domain_ops, bank); Don't use that irqdomain pointer inside the gpio_chip. Instead declare the irqdomain pointer inside struct stm32_gpio_bank or something like that. Yours, Linus Walleij From mboxrd@z Thu Jan 1 00:00:00 1970 From: linus.walleij@linaro.org (Linus Walleij) Date: Wed, 7 Sep 2016 23:06:12 +0200 Subject: [PATCH v4 6/9] pinctrl: Add IRQ support to STM32 gpios In-Reply-To: <1473180341-1999-7-git-send-email-alexandre.torgue@st.com> References: <1473180341-1999-1-git-send-email-alexandre.torgue@st.com> <1473180341-1999-7-git-send-email-alexandre.torgue@st.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Sep 6, 2016 at 6:45 PM, Alexandre TORGUE wrote: > This patch adds IRQ support to STM32 gpios. > > The EXTI controller has 16 lines dedicated to GPIOs. > EXTI line n can be connected to only line n of one of the GPIO ports, for > example EXTI0 can be connected to either PA0, or PB0, or PC0... > This port selection is done by specifying the port number into System > Config registers. > > Signed-off-by: Maxime Coquelin > Signed-off-by: Alexandre TORGUE > +++ b/drivers/pinctrl/stm32/Kconfig > @@ -6,6 +6,8 @@ config PINCTRL_STM32 > select PINMUX > select GENERIC_PINCONF > select GPIOLIB > + select GPIOLIB_IRQCHIP But you're not really using GPIOLIB_IRQCHIP. You have a different, super-complex irqchip in use. So just don't select this. > + bank->gpio_chip.irqdomain = irq_domain_create_hierarchy(pctl->domain, > + 0, STM32_GPIO_IRQ_LINE, bank->fwnode, > + &stm32_gpio_domain_ops, bank); Don't use that irqdomain pointer inside the gpio_chip. Instead declare the irqdomain pointer inside struct stm32_gpio_bank or something like that. Yours, Linus Walleij