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From: Linus Walleij <linus.walleij@linaro.org>
To: "thierry.reding@gmail.com" <thierry.reding@gmail.com>,
	"open list:DRM PANEL DRIVERS" <dri-devel@lists.freedesktop.org>,
	Andrzej Hajda <a.hajda@samsung.com>
Subject: Re: [PATCH v2] drm: dsi: Add lane clock rate fields to DSI device
Date: Mon, 22 Oct 2018 08:50:31 +0200	[thread overview]
Message-ID: <CACRpkdZgQFHw_GSPikF=sz+4zMpb3hNKCBaFkx_FPPG_=19=Rw@mail.gmail.com> (raw)
In-Reply-To: <20181018111902.31738-1-linus.walleij@linaro.org>

On Thu, Oct 18, 2018 at 1:19 PM Linus Walleij <linus.walleij@linaro.org> wrote:

> The DSI devices have a maximum operating frequency specified
> in their data sheet per the MIPI specification, and DSI hosts
> that can scale their frequency need this information to set
> their clock dividers right.
>
> As current panel drivers often lack this information, specify
> that setting it to zero will make the DSI host use some
> reasonable default.
>
> Cc: Andrzej Hajda <a.hajda@samsung.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ChangeLog v1->v2:
> - s/*_rate_hz/*_rate/g
> - s/operation/mode/g
> - Clarify that zero is only allowed for legacy drivers

Andrzej are you fine with this version (Acked-by) so I can apply it?

Yours,
Linus Walleij
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  reply	other threads:[~2018-10-22  6:50 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-18 11:19 [PATCH v2] drm: dsi: Add lane clock rate fields to DSI device Linus Walleij
2018-10-22  6:50 ` Linus Walleij [this message]
2018-10-23  5:03 ` A H

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