[PATCH 0/4] pinctrl: Add USB support for Aspeed SoCs

[PATCH 0/4] pinctrl: Add USB support for Aspeed SoCs

[Andrew Jeffery]

Hello,

With recent interest in the USB virtual hub in the Aspeed SoCs[1] it is a good
time to add pinmux support for the USB ports and controllers. The earlier
series of pinmux patches for the Aspeed SoCs focussed on supporting pins which
were capable of GPIO. This is not the case for the USB pins, hence they have
been unsupported until now.

Rob: I know you've mentioned previously you desired complete bindings to be
provided up front, so apologies for continuing to add functionality. This looks
to be the last of it.

Cheers,

Andrew

[1] https://www.spinics.net/lists/linux-usb/msg158506.html

Andrew Jeffery (4):
  ARM: aspeed: g4: Add USB functions to pinctrl bindings
  ARM: aspeed: g5: Add USB functions to pinctrl bindings
  pinctrl: aspeed: g4: Add USB device and host support
  pinctrl: aspeed: g5: Add USB device and host support

 .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt |  8 ++-
 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c         | 66 +++++++++++++++++++---
 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c         | 58 ++++++++++++++++++-
 3 files changed, 121 insertions(+), 11 deletions(-)

-- 
2.11.0

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[PATCH 0/4] pinctrl: Add USB support for Aspeed SoCs

[Andrew Jeffery]

Hello,

With recent interest in the USB virtual hub in the Aspeed SoCs[1] it is a good
time to add pinmux support for the USB ports and controllers. The earlier
series of pinmux patches for the Aspeed SoCs focussed on supporting pins which
were capable of GPIO. This is not the case for the USB pins, hence they have
been unsupported until now.

Rob: I know you've mentioned previously you desired complete bindings to be
provided up front, so apologies for continuing to add functionality. This looks
to be the last of it.

Cheers,

Andrew

[1] https://www.spinics.net/lists/linux-usb/msg158506.html

Andrew Jeffery (4):
  ARM: aspeed: g4: Add USB functions to pinctrl bindings
  ARM: aspeed: g5: Add USB functions to pinctrl bindings
  pinctrl: aspeed: g4: Add USB device and host support
  pinctrl: aspeed: g5: Add USB device and host support

 .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt |  8 ++-
 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c         | 66 +++++++++++++++++++---
 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c         | 58 ++++++++++++++++++-
 3 files changed, 121 insertions(+), 11 deletions(-)

-- 
2.11.0

[PATCH 1/4] ARM: aspeed: g4: Add USB functions to pinctrl bindings

[Andrew Jeffery]

The AST2400 contains several USB controllers:

* USB 1.1 Host Controller
* USB 2.0 Host Controller
* Combined USB 2.0 Virtual Hub and USB 1.1 HID Controller

Pins for three ports are routed to the three controllers such that:

* Port 1 is a dedicated USB 1.1 host port
* Port 2 is shared between the USB 1.1 host and HID controllers
* Port 3 is shared between the USB 2.0 host and Hub controllers

As the pins for port 1 are fixed function there is no associated mux
function or group described in the bindings. Ports 2 and 3 are muxed as
above, and the table below describes the mapping between pinmux function
names and ports:

Port  | USB Version  | USB Mode  | Mux Function
------|--------------|-----------|-------------
1     | 1.1          | Host      | -
2     | 1.1          | Host      | USB11H2
2     | 1.1          | Device    | USB11D1
3     | 2.0          | Host      | USB2H1
3     | 2.0          | Device    | USB2D1

Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
---
 Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
index ca01710ee29a..09142dab47db 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
@@ -69,8 +69,9 @@ PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
 ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
 SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
 SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
-TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS
-VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
+TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1
+USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1
+WDTRST2
 
 aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
 
-- 
2.11.0

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[PATCH 1/4] ARM: aspeed: g4: Add USB functions to pinctrl bindings

[Andrew Jeffery]

The AST2400 contains several USB controllers:

* USB 1.1 Host Controller
* USB 2.0 Host Controller
* Combined USB 2.0 Virtual Hub and USB 1.1 HID Controller

Pins for three ports are routed to the three controllers such that:

* Port 1 is a dedicated USB 1.1 host port
* Port 2 is shared between the USB 1.1 host and HID controllers
* Port 3 is shared between the USB 2.0 host and Hub controllers

As the pins for port 1 are fixed function there is no associated mux
function or group described in the bindings. Ports 2 and 3 are muxed as
above, and the table below describes the mapping between pinmux function
names and ports:

Port  | USB Version  | USB Mode  | Mux Function
------|--------------|-----------|-------------
1     | 1.1          | Host      | -
2     | 1.1          | Host      | USB11H2
2     | 1.1          | Device    | USB11D1
3     | 2.0          | Host      | USB2H1
3     | 2.0          | Device    | USB2D1

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
index ca01710ee29a..09142dab47db 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
@@ -69,8 +69,9 @@ PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
 ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
 SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
 SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
-TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS
-VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
+TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1
+USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1
+WDTRST2
 
 aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
 
-- 
2.11.0

[PATCH 2/4] ARM: aspeed: g5: Add USB functions to pinctrl bindings

[Andrew Jeffery]

The Aspeed AST2500 SoC contains a number of USB controllers:

* USB 1.1 Host Controller
* USB 2.0 Host Controller (x2)
* Combined USB 2.0 Virtual Hub and USB 1.1 HID Controller

The controllers are exposed via two USB ports with functionality muxed
as required. The following table illustrates the relationships between
the ports and the controllers via the mux function names:

Port  | USB Version  | USB Mode     | Mux Function
------|--------------|--------------|-------------
A     | 2.0          | Virtual Hub  | USB2AD
A     | 2.0          | Host         | USB2AH
B     | 1.1          | HID          | USB11BHID
B     | 2.0          | Device       | USB2BD
B     | 2.0          | Host         | USB2BH

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
index 09142dab47db..3b7266c7c438 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
@@ -87,7 +87,8 @@ SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9
 SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ
 SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0
 SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2
-TXD3 TXD4 UART6 USBCKI VGABIOSROM VGAHS VGAVS VPI24 VPO WDTRST1 WDTRST2
+TXD3 TXD4 UART6 USB11BHID USB2AD USB2AH USB2BD USB2BH USBCKI VGABIOSROM VGAHS
+VGAVS VPI24 VPO WDTRST1 WDTRST2
 
 Examples
 ========
-- 
2.11.0

[PATCH 3/4] pinctrl: aspeed: g4: Add USB device and host support

[Andrew Jeffery]

Implement the AST2400 USB functions as described by the devicetree
bindings. Three ports are fully documented in the datasheet and exposed
through the bindings and pinctrl, though there are remnants of
documentation for a fourth port muxed with GPIO pins GPIOQ6 and GPIOQ7.
The implementation is updated to reflect this but the function and
group are not exposed.

Disregarding the mostly undocumented fourth port, the USB functions are
an outlier with respect to the rest of the muxed functionality on the
AST2400 as GPIO is not supported on these pins.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 66 ++++++++++++++++++++++++++----
 1 file changed, 59 insertions(+), 7 deletions(-)

diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
index cf3106cec048..df56e58b05c1 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
@@ -1006,15 +1006,23 @@ SS_PIN_DECL(H3, GPIOQ5, SDA14);
 
 FUNC_GROUP_DECL(I2C14, H4, H3);
 
-#define DASH9028_DESC	SIG_DESC_SET(SCU90, 28)
+/*
+ * There are several opportunities to document USB port 4 in the datasheet, but
+ * it is only mentioned in one location. Particularly, the Multi-function Pins
+ * Mapping and Control table in the datasheet elides the signal names,
+ * suggesting that port 4 may not actually be functional. As such we define the
+ * signal names and control bit, but don't export the capability's function or
+ * group.
+ */
+#define USB11H3_DESC	SIG_DESC_SET(SCU90, 28)
 
 #define H2 134
-SIG_EXPR_LIST_DECL_SINGLE(DASHH2, DASHH2, DASH9028_DESC);
-SS_PIN_DECL(H2, GPIOQ6, DASHH2);
+SIG_EXPR_LIST_DECL_SINGLE(USB11HDP3, USB11H3, USB11H3_DESC);
+SS_PIN_DECL(H2, GPIOQ6, USB11HDP3);
 
 #define H1 135
-SIG_EXPR_LIST_DECL_SINGLE(DASHH1, DASHH1, DASH9028_DESC);
-SS_PIN_DECL(H1, GPIOQ7, DASHH1);
+SIG_EXPR_LIST_DECL_SINGLE(USB11HDN3, USB11H3, USB11H3_DESC);
+SS_PIN_DECL(H1, GPIOQ7, USB11HDN3);
 
 #define V20 136
 SSSF_PIN_DECL(V20, GPIOR0, ROMCS1, SIG_DESC_SET(SCU88, 24));
@@ -1706,10 +1714,42 @@ FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20, R22, P18, P19, P20, P21, P22, M19,
 FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19,
 		P20, P21, P22, M19, M20, M21, M22, L18, L19);
 
+#define USB11H2_DESC	SIG_DESC_SET(SCU90, 3)
+#define USB11D1_DESC	SIG_DESC_BIT(SCU90, 3, 0)
+
+#define K4 220
+SIG_EXPR_LIST_DECL_SINGLE(USB11HDP2, USB11H2, USB11H2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(USB11DP1, USB11D1, USB11D1_DESC);
+MS_PIN_DECL_(K4, SIG_EXPR_LIST_PTR(USB11HDP2), SIG_EXPR_LIST_PTR(USB11DP1));
+
+#define K3 221
+SIG_EXPR_LIST_DECL_SINGLE(USB11HDN1, USB11H2, USB11H2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(USB11DDN1, USB11D1, USB11D1_DESC);
+MS_PIN_DECL_(K3, SIG_EXPR_LIST_PTR(USB11HDN1), SIG_EXPR_LIST_PTR(USB11DDN1));
+
+FUNC_GROUP_DECL(USB11H2, K4, K3);
+FUNC_GROUP_DECL(USB11D1, K4, K3);
+
+#define USB2H1_DESC	SIG_DESC_SET(SCU90, 29)
+#define USB2D1_DESC	SIG_DESC_BIT(SCU90, 29, 0)
+
+#define AB21 222
+SIG_EXPR_LIST_DECL_SINGLE(USB2HDP1, USB2H1, USB2H1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(USB2DDP1, USB2D1, USB2D1_DESC);
+MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(USB2HDP1), SIG_EXPR_LIST_PTR(USB2DDP1));
+
+#define AB20 223
+SIG_EXPR_LIST_DECL_SINGLE(USB2HDN1, USB2H1, USB2H1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(USB2DDN1, USB2D1, USB2D1_DESC);
+MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(USB2HDN1), SIG_EXPR_LIST_PTR(USB2DDN1));
+
+FUNC_GROUP_DECL(USB2H1, AB21, AB20);
+FUNC_GROUP_DECL(USB2D1, AB21, AB20);
+
 /* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216
- * pins becomes 220.
+ * pins becomes 220. Four additional non-GPIO-capable pins are present for USB.
  */
-#define ASPEED_G4_NR_PINS 220
+#define ASPEED_G4_NR_PINS 224
 
 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */
 
@@ -1749,6 +1789,8 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
 	ASPEED_PINCTRL_PIN(AB5),
 	ASPEED_PINCTRL_PIN(AB6),
 	ASPEED_PINCTRL_PIN(AB7),
+	ASPEED_PINCTRL_PIN(AB20),
+	ASPEED_PINCTRL_PIN(AB21),
 	ASPEED_PINCTRL_PIN(B1),
 	ASPEED_PINCTRL_PIN(B10),
 	ASPEED_PINCTRL_PIN(B11),
@@ -1848,6 +1890,8 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
 	ASPEED_PINCTRL_PIN(J5),
 	ASPEED_PINCTRL_PIN(K18),
 	ASPEED_PINCTRL_PIN(K20),
+	ASPEED_PINCTRL_PIN(K3),
+	ASPEED_PINCTRL_PIN(K4),
 	ASPEED_PINCTRL_PIN(K5),
 	ASPEED_PINCTRL_PIN(L1),
 	ASPEED_PINCTRL_PIN(L18),
@@ -2070,6 +2114,10 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = {
 	ASPEED_PINCTRL_GROUP(TXD3),
 	ASPEED_PINCTRL_GROUP(TXD4),
 	ASPEED_PINCTRL_GROUP(UART6),
+	ASPEED_PINCTRL_GROUP(USB11D1),
+	ASPEED_PINCTRL_GROUP(USB11H2),
+	ASPEED_PINCTRL_GROUP(USB2D1),
+	ASPEED_PINCTRL_GROUP(USB2H1),
 	ASPEED_PINCTRL_GROUP(USBCKI),
 	ASPEED_PINCTRL_GROUP(VGABIOS_ROM),
 	ASPEED_PINCTRL_GROUP(VGAHS),
@@ -2221,6 +2269,10 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
 	ASPEED_PINCTRL_FUNC(TXD3),
 	ASPEED_PINCTRL_FUNC(TXD4),
 	ASPEED_PINCTRL_FUNC(UART6),
+	ASPEED_PINCTRL_FUNC(USB11D1),
+	ASPEED_PINCTRL_FUNC(USB11H2),
+	ASPEED_PINCTRL_FUNC(USB2D1),
+	ASPEED_PINCTRL_FUNC(USB2H1),
 	ASPEED_PINCTRL_FUNC(USBCKI),
 	ASPEED_PINCTRL_FUNC(VGABIOS_ROM),
 	ASPEED_PINCTRL_FUNC(VGAHS),
-- 
2.11.0

[PATCH 4/4] pinctrl: aspeed: g5: Add USB device and host support

[Andrew Jeffery]

Implement the AST2500 USB functions as described by the devicetree
bindings. The AST2500 exposes five USB controllers through two USB
ports. Similar to the AST2400, the pins exposing USB are outliers with
respect to the rest of the pinmux as they not capable of GPIO.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
 drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 58 +++++++++++++++++++++++++++++-
 1 file changed, 57 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index 68aa04664a62..634b371da43a 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -25,7 +25,7 @@
 #include "../pinctrl-utils.h"
 #include "pinctrl-aspeed.h"
 
-#define ASPEED_G5_NR_PINS 232
+#define ASPEED_G5_NR_PINS 236
 
 #define COND1		{ ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 }
 #define COND2		{ ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
@@ -1724,6 +1724,48 @@ FUNC_GROUP_DECL(LPCRST, G22);
 
 FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22);
 
+#define A7 232
+SIG_EXPR_LIST_DECL_SINGLE(USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29));
+SIG_EXPR_LIST_DECL_SINGLE(USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
+MS_PIN_DECL_(A7, SIG_EXPR_LIST_PTR(USB2AHDP), SIG_EXPR_LIST_PTR(USB2ADDP));
+
+#define A8 233
+SIG_EXPR_LIST_DECL_SINGLE(USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29));
+SIG_EXPR_LIST_DECL_SINGLE(USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
+MS_PIN_DECL_(A8, SIG_EXPR_LIST_PTR(USB2AHDN), SIG_EXPR_LIST_PTR(USB2ADDN));
+
+FUNC_GROUP_DECL(USB2AH, A7, A8);
+FUNC_GROUP_DECL(USB2AD, A7, A8);
+
+#define USB11BHID_DESC  { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 }
+#define USB2BD_DESC   { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 }
+#define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 }
+#define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 }
+
+#define B6 234
+SIG_EXPR_LIST_DECL_SINGLE(USB11BDP, USB11BHID, USB11BHID_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(USB2BDDP, USB2BD, USB2BD_DESC);
+SIG_EXPR_DECL(USB2BHDP1, USB2BH, USB2BH1_DESC);
+SIG_EXPR_DECL(USB2BHDP2, USB2BH, USB2BH2_DESC);
+SIG_EXPR_LIST_DECL(USB2BHDP, SIG_EXPR_PTR(USB2BHDP1, USB2BH),
+		SIG_EXPR_PTR(USB2BHDP2, USB2BH));
+MS_PIN_DECL_(B6, SIG_EXPR_LIST_PTR(USB11BDP), SIG_EXPR_LIST_PTR(USB2BDDP),
+		SIG_EXPR_LIST_PTR(USB2BHDP));
+
+#define A6 235
+SIG_EXPR_LIST_DECL_SINGLE(USB11BDN, USB11BHID, USB11BHID_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(USB2BDN, USB2BD, USB2BD_DESC);
+SIG_EXPR_DECL(USB2BHDN1, USB2BH, USB2BH1_DESC);
+SIG_EXPR_DECL(USB2BHDN2, USB2BH, USB2BH2_DESC);
+SIG_EXPR_LIST_DECL(USB2BHDN, SIG_EXPR_PTR(USB2BHDN1, USB2BH),
+		SIG_EXPR_PTR(USB2BHDN2, USB2BH));
+MS_PIN_DECL_(A6, SIG_EXPR_LIST_PTR(USB11BDN), SIG_EXPR_LIST_PTR(USB2BDN),
+		SIG_EXPR_LIST_PTR(USB2BHDN));
+
+FUNC_GROUP_DECL(USB11BHID, B6, A6);
+FUNC_GROUP_DECL(USB2BD, B6, A6);
+FUNC_GROUP_DECL(USB2BH, B6, A6);
+
 /* Pins, groups and functions are sort(1):ed alphabetically for sanity */
 
 static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
@@ -1743,6 +1785,9 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
 	ASPEED_PINCTRL_PIN(A3),
 	ASPEED_PINCTRL_PIN(A4),
 	ASPEED_PINCTRL_PIN(A5),
+	ASPEED_PINCTRL_PIN(A6),
+	ASPEED_PINCTRL_PIN(A7),
+	ASPEED_PINCTRL_PIN(A8),
 	ASPEED_PINCTRL_PIN(A9),
 	ASPEED_PINCTRL_PIN(AA1),
 	ASPEED_PINCTRL_PIN(AA19),
@@ -1777,6 +1822,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
 	ASPEED_PINCTRL_PIN(B3),
 	ASPEED_PINCTRL_PIN(B4),
 	ASPEED_PINCTRL_PIN(B5),
+	ASPEED_PINCTRL_PIN(B6),
 	ASPEED_PINCTRL_PIN(B9),
 	ASPEED_PINCTRL_PIN(C1),
 	ASPEED_PINCTRL_PIN(C11),
@@ -2111,6 +2157,11 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
 	ASPEED_PINCTRL_GROUP(TXD3),
 	ASPEED_PINCTRL_GROUP(TXD4),
 	ASPEED_PINCTRL_GROUP(UART6),
+	ASPEED_PINCTRL_GROUP(USB11BHID),
+	ASPEED_PINCTRL_GROUP(USB2AD),
+	ASPEED_PINCTRL_GROUP(USB2AH),
+	ASPEED_PINCTRL_GROUP(USB2BD),
+	ASPEED_PINCTRL_GROUP(USB2BH),
 	ASPEED_PINCTRL_GROUP(USBCKI),
 	ASPEED_PINCTRL_GROUP(VGABIOSROM),
 	ASPEED_PINCTRL_GROUP(VGAHS),
@@ -2275,6 +2326,11 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
 	ASPEED_PINCTRL_FUNC(TXD3),
 	ASPEED_PINCTRL_FUNC(TXD4),
 	ASPEED_PINCTRL_FUNC(UART6),
+	ASPEED_PINCTRL_FUNC(USB11BHID),
+	ASPEED_PINCTRL_FUNC(USB2AD),
+	ASPEED_PINCTRL_FUNC(USB2AH),
+	ASPEED_PINCTRL_FUNC(USB2BD),
+	ASPEED_PINCTRL_FUNC(USB2BH),
 	ASPEED_PINCTRL_FUNC(USBCKI),
 	ASPEED_PINCTRL_FUNC(VGABIOSROM),
 	ASPEED_PINCTRL_FUNC(VGAHS),
-- 
2.11.0

Re: [PATCH 1/4] ARM: aspeed: g4: Add USB functions to pinctrl bindings

[Benjamin Herrenschmidt]

On Tue, 2017-06-27 at 11:42 +0930, Andrew Jeffery wrote:
> The AST2400 contains several USB controllers:
> 
> * USB 1.1 Host Controller
> * USB 2.0 Host Controller
> * Combined USB 2.0 Virtual Hub and USB 1.1 HID Controller

There's also a USB1.1 HID-only device-controller, but it's a legacy
piece of IP that we may never support. It might be worth mentioning its
existence and Ryan might want it supported in the bindings at least no
?

> Pins for three ports are routed to the three controllers such that:
> 
> * Port 1 is a dedicated USB 1.1 host port
> * Port 2 is shared between the USB 1.1 host and HID controllers
> * Port 3 is shared between the USB 2.0 host and Hub controllers
> 
> As the pins for port 1 are fixed function there is no associated mux
> function or group described in the bindings. Ports 2 and 3 are muxed as
> above, and the table below describes the mapping between pinmux function
> names and ports:
> 
> Port  | USB Version  | USB Mode  | Mux Function
> ------|--------------|-----------|-------------
> 1     | 1.1          | Host      | -
> 2     | 1.1          | Host      | USB11H2
> 2     | 1.1          | Device    | USB11D1
> 3     | 2.0          | Host      | USB2H1
> 3     | 2.0          | Device    | USB2D1
> 
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
>  Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> index ca01710ee29a..09142dab47db 100644
> --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> @@ -69,8 +69,9 @@ PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
>  ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
>  SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
>  SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
> -TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS
> -VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
> +TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1
> +USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1
> +WDTRST2
>  
>  aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
>  

Re: [PATCH 0/4] pinctrl: Add USB support for Aspeed SoCs

[Linus Walleij]

On Tue, Jun 27, 2017 at 4:12 AM, Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org> wrote:

> With recent interest in the USB virtual hub in the Aspeed SoCs[1] it is a good
> time to add pinmux support for the USB ports and controllers. The earlier
> series of pinmux patches for the Aspeed SoCs focussed on supporting pins which
> were capable of GPIO. This is not the case for the USB pins, hence they have
> been unsupported until now.
>
> Rob: I know you've mentioned previously you desired complete bindings to be
> provided up front, so apologies for continuing to add functionality. This looks
> to be the last of it.

Waiting for DT review and addressing of Beji's comment for these.

Please resend after the merge window.

Yours,
Linus Walleij
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Re: [PATCH 0/4] pinctrl: Add USB support for Aspeed SoCs

[Linus Walleij]

On Tue, Jun 27, 2017 at 4:12 AM, Andrew Jeffery <andrew@aj.id.au> wrote:

> With recent interest in the USB virtual hub in the Aspeed SoCs[1] it is a good
> time to add pinmux support for the USB ports and controllers. The earlier
> series of pinmux patches for the Aspeed SoCs focussed on supporting pins which
> were capable of GPIO. This is not the case for the USB pins, hence they have
> been unsupported until now.
>
> Rob: I know you've mentioned previously you desired complete bindings to be
> provided up front, so apologies for continuing to add functionality. This looks
> to be the last of it.

Waiting for DT review and addressing of Beji's comment for these.

Please resend after the merge window.

Yours,
Linus Walleij

Re: [PATCH 1/4] ARM: aspeed: g4: Add USB functions to pinctrl bindings

[Rob Herring]

On Tue, Jun 27, 2017 at 11:42:11AM +0930, Andrew Jeffery wrote:
> The AST2400 contains several USB controllers:
> 
> * USB 1.1 Host Controller
> * USB 2.0 Host Controller
> * Combined USB 2.0 Virtual Hub and USB 1.1 HID Controller
> 
> Pins for three ports are routed to the three controllers such that:
> 
> * Port 1 is a dedicated USB 1.1 host port
> * Port 2 is shared between the USB 1.1 host and HID controllers
> * Port 3 is shared between the USB 2.0 host and Hub controllers
> 
> As the pins for port 1 are fixed function there is no associated mux
> function or group described in the bindings. Ports 2 and 3 are muxed as
> above, and the table below describes the mapping between pinmux function
> names and ports:
> 
> Port  | USB Version  | USB Mode  | Mux Function
> ------|--------------|-----------|-------------
> 1     | 1.1          | Host      | -
> 2     | 1.1          | Host      | USB11H2
> 2     | 1.1          | Device    | USB11D1
> 3     | 2.0          | Host      | USB2H1
> 3     | 2.0          | Device    | USB2D1
> 
> Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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Re: [PATCH 1/4] ARM: aspeed: g4: Add USB functions to pinctrl bindings

[Rob Herring]

On Tue, Jun 27, 2017 at 11:42:11AM +0930, Andrew Jeffery wrote:
> The AST2400 contains several USB controllers:
> 
> * USB 1.1 Host Controller
> * USB 2.0 Host Controller
> * Combined USB 2.0 Virtual Hub and USB 1.1 HID Controller
> 
> Pins for three ports are routed to the three controllers such that:
> 
> * Port 1 is a dedicated USB 1.1 host port
> * Port 2 is shared between the USB 1.1 host and HID controllers
> * Port 3 is shared between the USB 2.0 host and Hub controllers
> 
> As the pins for port 1 are fixed function there is no associated mux
> function or group described in the bindings. Ports 2 and 3 are muxed as
> above, and the table below describes the mapping between pinmux function
> names and ports:
> 
> Port  | USB Version  | USB Mode  | Mux Function
> ------|--------------|-----------|-------------
> 1     | 1.1          | Host      | -
> 2     | 1.1          | Host      | USB11H2
> 2     | 1.1          | Device    | USB11D1
> 3     | 2.0          | Host      | USB2H1
> 3     | 2.0          | Device    | USB2D1
> 
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
>  Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 2/4] ARM: aspeed: g5: Add USB functions to pinctrl bindings

[Rob Herring]

On Tue, Jun 27, 2017 at 11:42:12AM +0930, Andrew Jeffery wrote:
> The Aspeed AST2500 SoC contains a number of USB controllers:
> 
> * USB 1.1 Host Controller
> * USB 2.0 Host Controller (x2)
> * Combined USB 2.0 Virtual Hub and USB 1.1 HID Controller
> 
> The controllers are exposed via two USB ports with functionality muxed
> as required. The following table illustrates the relationships between
> the ports and the controllers via the mux function names:
> 
> Port  | USB Version  | USB Mode     | Mux Function
> ------|--------------|--------------|-------------
> A     | 2.0          | Virtual Hub  | USB2AD
> A     | 2.0          | Host         | USB2AH
> B     | 1.1          | HID          | USB11BHID
> B     | 2.0          | Device       | USB2BD
> B     | 2.0          | Host         | USB2BH
> 
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
>  Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 2/4] ARM: aspeed: g5: Add USB functions to pinctrl bindings

[Rob Herring]

On Thu, Jun 29, 2017 at 03:13:24PM -0500, Rob Herring wrote:
> On Tue, Jun 27, 2017 at 11:42:12AM +0930, Andrew Jeffery wrote:
> > The Aspeed AST2500 SoC contains a number of USB controllers:
> > 
> > * USB 1.1 Host Controller
> > * USB 2.0 Host Controller (x2)
> > * Combined USB 2.0 Virtual Hub and USB 1.1 HID Controller
> > 
> > The controllers are exposed via two USB ports with functionality muxed
> > as required. The following table illustrates the relationships between
> > the ports and the controllers via the mux function names:
> > 
> > Port  | USB Version  | USB Mode     | Mux Function
> > ------|--------------|--------------|-------------
> > A     | 2.0          | Virtual Hub  | USB2AD
> > A     | 2.0          | Host         | USB2AH
> > B     | 1.1          | HID          | USB11BHID
> > B     | 2.0          | Device       | USB2BD
> > B     | 2.0          | Host         | USB2BH
> > 
> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > ---
> >  Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> Acked-by: Rob Herring <robh@kernel.org>

Also, when you resend, use "dt-bindings: pinctrl: ..." for the subjects 
of binding patches in this series.

Rob

Re: [PATCH 1/4] ARM: aspeed: g4: Add USB functions to pinctrl bindings

[Andrew Jeffery]

[-- Attachment #1: Type: text/plain, Size: 3487 bytes --]

On Mon, 2017-06-26 at 22:53 -0500, Benjamin Herrenschmidt wrote:
> On Tue, 2017-06-27 at 11:42 +0930, Andrew Jeffery wrote:
> > The AST2400 contains several USB controllers:
> > 
> > * USB 1.1 Host Controller
> > * USB 2.0 Host Controller
> > * Combined USB 2.0 Virtual Hub and USB 1.1 HID Controller
> 
> There's also a USB1.1 HID-only device-controller, but it's a legacy
> piece of IP that we may never support.

Yes, I'll fix that - there's a block diagram in the datasheet that
suggests they're combined, but the memory map says otherwise. I'll
separate them out in the commit message.

>  It might be worth mentioning its
> existence and Ryan might want it supported in the bindings at least no
> ?

Unless I've missed something this just amounts to a change in the
commit message, both above to split the Hub/HID description and below
in the table to say "HID" instead of just "Device". The bindings as
they stand in this patch completely describe the mux behaviour for USB
as documented in the datasheet's Multifunction Pins Mapping and Control
table.

> 
> > Pins for three ports are routed to the three controllers such that:
> > 
> > * Port 1 is a dedicated USB 1.1 host port
> > * Port 2 is shared between the USB 1.1 host and HID controllers
> > * Port 3 is shared between the USB 2.0 host and Hub controllers
> > 
> > As the pins for port 1 are fixed function there is no associated mux
> > function or group described in the bindings. Ports 2 and 3 are muxed as
> > above, and the table below describes the mapping between pinmux function
> > names and ports:
> > 
> > Port  | USB Version  | USB Mode  | Mux Function
> > ------|--------------|-----------|-------------
> > 1     | 1.1          | Host      | -
> > 2     | 1.1          | Host      | USB11H2
> > 2     | 1.1          | Device    | USB11D1

                           ^~~~~~
                           Should be "HID" for clarity

Cheers,

Andrew

> > 3     | 2.0          | Host      | USB2H1
> > 3     | 2.0          | Device    | USB2D1
> > 
> > > > Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
> > ---
> >  Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> > index ca01710ee29a..09142dab47db 100644
> > --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> > +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> > @@ -69,8 +69,9 @@ PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
> >  ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
> >  SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
> >  SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
> > -TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS
> > -VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
> > +TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1
> > +USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1
> > +WDTRST2
> >  
> >  aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
> >  

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Re: [PATCH 1/4] ARM: aspeed: g4: Add USB functions to pinctrl bindings

[Andrew Jeffery]

[-- Attachment #1: Type: text/plain, Size: 3467 bytes --]

On Mon, 2017-06-26 at 22:53 -0500, Benjamin Herrenschmidt wrote:
> On Tue, 2017-06-27 at 11:42 +0930, Andrew Jeffery wrote:
> > The AST2400 contains several USB controllers:
> > 
> > * USB 1.1 Host Controller
> > * USB 2.0 Host Controller
> > * Combined USB 2.0 Virtual Hub and USB 1.1 HID Controller
> 
> There's also a USB1.1 HID-only device-controller, but it's a legacy
> piece of IP that we may never support.

Yes, I'll fix that - there's a block diagram in the datasheet that
suggests they're combined, but the memory map says otherwise. I'll
separate them out in the commit message.

>  It might be worth mentioning its
> existence and Ryan might want it supported in the bindings at least no
> ?

Unless I've missed something this just amounts to a change in the
commit message, both above to split the Hub/HID description and below
in the table to say "HID" instead of just "Device". The bindings as
they stand in this patch completely describe the mux behaviour for USB
as documented in the datasheet's Multifunction Pins Mapping and Control
table.

> 
> > Pins for three ports are routed to the three controllers such that:
> > 
> > * Port 1 is a dedicated USB 1.1 host port
> > * Port 2 is shared between the USB 1.1 host and HID controllers
> > * Port 3 is shared between the USB 2.0 host and Hub controllers
> > 
> > As the pins for port 1 are fixed function there is no associated mux
> > function or group described in the bindings. Ports 2 and 3 are muxed as
> > above, and the table below describes the mapping between pinmux function
> > names and ports:
> > 
> > Port  | USB Version  | USB Mode  | Mux Function
> > ------|--------------|-----------|-------------
> > 1     | 1.1          | Host      | -
> > 2     | 1.1          | Host      | USB11H2
> > 2     | 1.1          | Device    | USB11D1

                           ^~~~~~
                           Should be "HID" for clarity

Cheers,

Andrew

> > 3     | 2.0          | Host      | USB2H1
> > 3     | 2.0          | Device    | USB2D1
> > 
> > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > ---
> >  Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> > index ca01710ee29a..09142dab47db 100644
> > --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> > +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> > @@ -69,8 +69,9 @@ PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
> >  ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
> >  SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
> >  SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
> > -TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS
> > -VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
> > +TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1
> > +USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1
> > +WDTRST2
> >  
> >  aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
> >  

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Re: [PATCH 2/4] ARM: aspeed: g5: Add USB functions to pinctrl bindings

[Andrew Jeffery]

[-- Attachment #1: Type: text/plain, Size: 1565 bytes --]

On Thu, 2017-06-29 at 15:32 -0500, Rob Herring wrote:
> On Thu, Jun 29, 2017 at 03:13:24PM -0500, Rob Herring wrote:
> > On Tue, Jun 27, 2017 at 11:42:12AM +0930, Andrew Jeffery wrote:
> > > The Aspeed AST2500 SoC contains a number of USB controllers:
> > > 
> > > * USB 1.1 Host Controller
> > > * USB 2.0 Host Controller (x2)
> > > * Combined USB 2.0 Virtual Hub and USB 1.1 HID Controller
> > > 
> > > The controllers are exposed via two USB ports with functionality muxed
> > > as required. The following table illustrates the relationships between
> > > the ports and the controllers via the mux function names:
> > > 
> > > Port  | USB Version  | USB Mode     | Mux Function
> > > ------|--------------|--------------|-------------
> > > A     | 2.0          | Virtual Hub  | USB2AD
> > > A     | 2.0          | Host         | USB2AH
> > > B     | 1.1          | HID          | USB11BHID
> > > B     | 2.0          | Device       | USB2BD
> > > B     | 2.0          | Host         | USB2BH
> > > 
> > > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > > ---
> > >  Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 3 ++-
> > >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > Acked-by: Rob Herring <robh@kernel.org>
> 
> Also, when you resend, use "dt-bindings: pinctrl: ..." for the subjects 
> of binding patches in this series.

Will do.

Cheers,

Andrew

> 
> Rob

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Re: [PATCH 0/4] pinctrl: Add USB support for Aspeed SoCs

[Andrew Jeffery]

[-- Attachment #1: Type: text/plain, Size: 1003 bytes --]

On Thu, 2017-06-29 at 14:53 +0200, Linus Walleij wrote:
> > On Tue, Jun 27, 2017 at 4:12 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> 
> > With recent interest in the USB virtual hub in the Aspeed SoCs[1] it is a good
> > time to add pinmux support for the USB ports and controllers. The earlier
> > series of pinmux patches for the Aspeed SoCs focussed on supporting pins which
> > were capable of GPIO. This is not the case for the USB pins, hence they have
> > been unsupported until now.
> > 
> > Rob: I know you've mentioned previously you desired complete bindings to be
> > provided up front, so apologies for continuing to add functionality. This looks
> > to be the last of it.
> 
> Waiting for DT review and addressing of Beji's comment for these.

Okay, Rob's now ack'ed the bindings and Ben's comments should amount to
a commit message change. I've reworked it.

> 
> Please resend after the merge window.

Will do.

Thanks,

Andrew

> 
> Yours,
> Linus Walleij

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