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* [PATCH 1/4 v5] drivers: create a pin control subsystem v5
@ 2011-08-29  9:10 ` Linus Walleij
  0 siblings, 0 replies; 16+ messages in thread
From: Linus Walleij @ 2011-08-29  9:10 UTC (permalink / raw)
  To: linux-kernel, linux-arm-kernel, Grant Likely, Stephen Warren
  Cc: Lee Jones, Joe Perches, Russell King, Linaro Dev, Sascha Hauer,
	David Brown, Barry Song, Linus Walleij, Grant Likely,
	Stephen Warren

From: Linus Walleij <linus.walleij@linaro.org>

This creates a subsystem for handling of pin control devices.
These are devices that control different aspects of package
pins.

Currently it handled pinmuxing, i.e. assign electronic functions
to groups of pins of pins on primarily PGA and BGA type of chip
packages and common in embedded systems.

The plan is to also handle other I/O pin control aspects such as
biasing, driving, input properties such as schmitt-triggering,
load capacitance etc within this subsystem.

This is being done to depopulate the arch/arm/* directory of such
custom drivers and try to abstract the infrastructure they all
need. See the Documentation/pinmux.txt file that is part of this
patch for more details.

Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Joe Perches <joe@perches.com>
Cc: Russell King <linux@arm.linux.org.uk>
Tested-by: Barry Song <21cnbao@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v4->v5:

- Defined a "position" for each function, so the pin controller now
  tracks a function in a certain position, and the pinmux maps define
  what position you want the function in. (Feedback from Stephen
  Warren and Sascha Hauer).

- Since we now need to request a combined function+position from
  the machine mapping table that connect mux settings to drivers,
  it was extended with a position field and a name field. The
  name field is now used if you e.g. need to switch between two
  mux map settings at runtime.

- Switched from a class device to using struct bus_type for this
  subsystem. Verified sysfs functionality: seems to work fine.
  (Feedback from Arnd Bergmann and Greg Kroah-Hartman)

- Define a per pincontroller list of GPIO ranges from the GPIO
  pin space that can be handled by the pin controller. These can
  be added one by one at runtime. (Feedback from Barry Song)

- Expanded documentation of regulator_[get|enable|disable|put]
  semantics.

- Fixed a number of review comments from Barry Song. (Thanks!)
---
 Documentation/ABI/testing/sysfs-class-pinmux |   11 +
 Documentation/pinctrl.txt                    |  714 +++++++++++++++++++++++
 MAINTAINERS                                  |    5 +
 drivers/Kconfig                              |    4 +
 drivers/Makefile                             |    2 +
 drivers/pinctrl/Kconfig                      |   29 +
 drivers/pinctrl/Makefile                     |    6 +
 drivers/pinctrl/core.c                       |  539 +++++++++++++++++
 drivers/pinctrl/core.h                       |   24 +
 drivers/pinctrl/pinmux.c                     |  811 ++++++++++++++++++++++++++
 drivers/pinctrl/pinmux.h                     |    4 +
 include/linux/pinctrl/machine.h              |   74 +++
 include/linux/pinctrl/pinctrl.h              |  143 +++++
 include/linux/pinctrl/pinmux.h               |  135 +++++
 14 files changed, 2501 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/ABI/testing/sysfs-class-pinmux
 create mode 100644 Documentation/pinctrl.txt
 create mode 100644 drivers/pinctrl/Kconfig
 create mode 100644 drivers/pinctrl/Makefile
 create mode 100644 drivers/pinctrl/core.c
 create mode 100644 drivers/pinctrl/core.h
 create mode 100644 drivers/pinctrl/pinmux.c
 create mode 100644 drivers/pinctrl/pinmux.h
 create mode 100644 include/linux/pinctrl/machine.h
 create mode 100644 include/linux/pinctrl/pinctrl.h
 create mode 100644 include/linux/pinctrl/pinmux.h

diff --git a/Documentation/ABI/testing/sysfs-class-pinmux b/Documentation/ABI/testing/sysfs-class-pinmux
new file mode 100644
index 0000000..c2ea843
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-class-pinmux
@@ -0,0 +1,11 @@
+What:		/sys/class/pinmux/.../name
+Date:		May 2011
+KernelVersion:	3.1
+Contact:	Linus Walleij <linus.walleij@linaro.org>
+Description:
+		Each pinmux directory will contain a field called
+		name. This holds a string identifying the pinmux for
+		display purposes.
+
+		NOTE: this will be empty if no suitable name is provided
+		by platform or pinmux drivers.
diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
new file mode 100644
index 0000000..76c003a
--- /dev/null
+++ b/Documentation/pinctrl.txt
@@ -0,0 +1,714 @@
+PINCTRL (PIN CONTROL) subsystem
+This document outlines the pin control subsystem in Linux
+
+This subsystem deals with:
+
+- Enumerating and naming controllable pins
+
+- Multiplexing of pins, pads, fingers (etc) see below for details
+
+The intention is to also deal with:
+
+- Software-controlled biasing and driving mode specific pins, such as
+  pull-up/down, open drain etc, load capacitance configuration when controlled
+  by software, etc.
+
+
+Top-level interface
+===================
+
+Definition of PIN CONTROLLER:
+
+- A pin controller is a piece of hardware, usually a set of registers, that
+  can control PINs. It may be able to multiplex, bias, set load capacitance,
+  set drive strength etc for individual pins or groups of pins.
+
+Definition of PIN:
+
+- PINS are equal to pads, fingers, balls or whatever packaging input or
+  output line you want to control and these are denoted by unsigned integers
+  in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
+  there may be several such number spaces in a system. This pin space may
+  be sparse - i.e. there may be gaps in the space with numbers where no
+  pin exists.
+
+When a PIN CONTROLLER is instatiated, it will register a descriptor to the
+pin control framework, and this descriptor contains an array of pin descriptors
+describing the pins handled by this specific pin controller.
+
+Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
+
+        A   B   C   D   E   F   G   H
+
+   8    o   o   o   o   o   o   o   o
+
+   7    o   o   o   o   o   o   o   o
+
+   6    o   o   o   o   o   o   o   o
+
+   5    o   o   o   o   o   o   o   o
+
+   4    o   o   o   o   o   o   o   o
+
+   3    o   o   o   o   o   o   o   o
+
+   2    o   o   o   o   o   o   o   o
+
+   1    o   o   o   o   o   o   o   o
+
+To register a pin controller and name all the pins on this package we can do
+this in our driver:
+
+#include <linux/pinctrl/pinctrl.h>
+
+const struct pinctrl_pin_desc __refdata foo_pins[] = {
+      PINCTRL_PIN(0, "A1"),
+      PINCTRL_PIN(1, "A2"),
+      PINCTRL_PIN(2, "A3"),
+      ...
+      PINCTRL_PIN(61, "H6"),
+      PINCTRL_PIN(62, "H7"),
+      PINCTRL_PIN(63, "H8"),
+};
+
+static struct pinctrl_desc foo_desc = {
+	.name = "foo",
+	.pins = foo_pins,
+	.npins = ARRAY_SIZE(foo_pins),
+	.maxpin = 63,
+	.owner = THIS_MODULE,
+};
+
+int __init foo_probe(void)
+{
+	struct pinctrl_dev *pctl;
+
+	pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
+	if (IS_ERR(pctl))
+		pr_err("could not register foo pin driver\n");
+}
+
+Pins usually have fancier names than this. You can find these in the dataheet
+for your chip. Notice that the core pinctrl.h file provides a fancy macro
+called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
+the pins from 0 in the upper left corner to 63 in the lower right corner,
+this enumeration was arbitrarily chosen, in practice you need to think
+through your numbering system so that it matches the layout of registers
+and such things in your driver, or the code may become complicated. You must
+also consider matching of offsets to the GPIO ranges that may be handled by
+the pin controller.
+
+For a padring with 467 pads, as opposed to actual pins, I used an enumeration
+like this, walking around the edge of the chip, which seems to be industry
+standard too (all these pads had names, too):
+
+
+     0 ..... 104
+   466        105
+     .        .
+     .        .
+   358        224
+    357 .... 225
+
+
+Interaction with the GPIO subsystem
+===================================
+
+The GPIO drivers may want to perform operations of various types on the same
+physical pins that are also registered as GPIO pins.
+
+Since the pin controller subsystem have its pinspace local to the pin
+controller we need a mapping so that the pin control subsystem can figure out
+which pin controller handles control of a certain GPIO pin. Since a single
+pin controller may be muxing several GPIO ranges (typically SoCs that have
+one set of pins but internally several GPIO silicon blocks, each modeled as
+a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
+instance like this:
+
+struct gpio_chip chip_a;
+struct gpio_chip chip_b;
+
+static struct pinctrl_gpio_range gpio_range_a = {
+	.name = "chip a",
+	.id = 0,
+	.base = 32,
+	.npins = 16,
+	.gc = &chip_a;
+};
+
+static struct pinctrl_gpio_range gpio_range_a = {
+	.name = "chip b",
+	.id = 0,
+	.base = 48,
+	.npins = 8,
+	.gc = &chip_b;
+};
+
+
+{
+	struct pinctrl_dev *pctl;
+	...
+	pinctrl_add_gpio_range(pctl, &gpio_range_a);
+	pinctrl_add_gpio_range(pctl, &gpio_range_b);
+}
+
+So this complex system has one pin controller handling two different
+GPIO chips. Chip a has 16 pins and chip b has 8 pins. They are mapped in
+the global GPIO pin space at:
+
+chip a: [32 .. 47]
+chip b: [48 .. 55]
+
+When GPIO-specific functions in the pin control subsystem are called, these
+ranges will be used to look up the apropriate pin controller by inspecting
+and matching the pin to the pin ranges across all controllers. When a
+pin controller handling the matching range is found, GPIO-specific functions
+will be called on that specific pin controller.
+
+For all functionalities dealing with pin biasing, pin muxing etc, the pin
+controller subsystem will subtract the range's .base offset from the passed
+in gpio pin number, and pass that on to the pin control driver, so the driver
+will get an offset into its handled number range. Further it is also passed
+the range ID value, so that the pin controller knows which range it should
+deal with.
+
+For example: if a user issues pinctrl_gpio_set_foo(50), the pin control
+subsystem will find that the second range on this pin controller matches,
+subtract the base 48 and call the
+pinctrl_driver_gpio_set_foo(pinctrl, range, 2) where the latter function has
+this signature:
+
+int pinctrl_driver_gpio_set_foo(struct pinctrl_dev *pctldev,
+    struct pinctrl_gpio_range *rangeid,
+    unsigned offset);
+
+Now the driver knows that we want to do some GPIO-specific operation on the
+second GPIO range handled by "chip b", at offset 2 in that specific range.
+
+(If the GPIO subsystem is ever refactored to use a local per-GPIO controller
+pin space, this mapping will need to be augmented accordingly.)
+
+
+PINMUX interfaces
+=================
+
+These calls use the pinmux_* naming prefix.  No other calls should use that
+prefix.
+
+
+What is pinmuxing?
+==================
+
+PINMUX, also known as padmux, ballmux, alternate functions or mission modes
+is a way for chip vendors producing some kind of electrical packages to use
+a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
+functions, depending on the application. By "application" in this context
+we usually mean a way of soldering or wiring the package into an electronic
+system, even though the framework makes it possible to also change the function
+at runtime.
+
+Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
+
+        A   B   C   D   E   F   G   H
+      +---+
+   8  | o | o   o   o   o   o   o   o
+      |   |
+   7  | o | o   o   o   o   o   o   o
+      |   |
+   6  | o | o   o   o   o   o   o   o
+      +---+---+
+   5  | o | o | o   o   o   o   o   o
+      +---+---+               +---+
+   4    o   o   o   o   o   o | o | o
+                              |   |
+   3    o   o   o   o   o   o | o | o
+                              |   |
+   2    o   o   o   o   o   o | o | o
+      +-------+-------+-------+---+---+
+   1  | o   o | o   o | o   o | o | o |
+      +-------+-------+-------+---+---+
+
+This is not tetris. The game to think of is chess. Not all PGA/BGA packages
+are chessboard-like, big ones have "holes" in some arrangement according to
+different design patterns, but we're using this as a simple example. Of the
+pins you see some will be taken by things like a few VCC and GND to feed power
+to the chip, and quite a few will be taken by large ports like an external
+memory interface. The remaining pins will often be subject to pin multiplexing.
+
+The example 8x8 PGA package above will have pin numbers 0 thru 63 assigned to
+its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
+pinctrl_register_pins_[sparse|dense]() and a suitable data set as shown
+earlier.
+
+In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
+(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
+some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
+be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
+we cannot use the SPI port and I2C port at the same time. However in the inside
+of the package the silicon performing the SPI logic can alternatively be routed
+out on pins { G4, G3, G2, G1 }.
+
+On the botton row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
+special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
+consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
+{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
+port on pins { G4, G3, G2, G1 } of course.
+
+This way the silicon blocks present inside the chip can be multiplexed "muxed"
+out on different pin ranges. Often contemporary SoC (systems on chip) will
+contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
+different pins by pinmux settings.
+
+Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
+common to be able to use almost any pin as a GPIO pin if it is not currently
+in use by some other I/O port.
+
+
+Pinmux conventions
+==================
+
+The purpose of the pinmux functionality in the pin controller subsystem is to
+abstract and provide pinmux settings to the devices you choose to instantiate
+in your machine configuration. It is inspired by the clk, GPIO and regulator
+subsystems, so devices will request their mux setting, but it's also possible
+to request a single pin for e.g. GPIO.
+
+Definitions:
+
+- FUNCTIONS can be switched in and out by a driver residing with the pin
+  control subsystem in the drivers/pinctrl/* directory of the kernel. The
+  pin control driver knows the possible functions. In the example above you can
+  identify three pinmux functions, two for spi and one for i2c.
+
+- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
+  In this case the array could be something like: { spi0, i2c0, mmc0 }
+  for the three available functions.
+
+- POSITIONS are applicable to each function, so if spi0 can appear on three
+  different sets of pins, say {0, 1}, {4, 5} and {12, 13} these three
+  positions are numbered 0, 1, 2.
+
+- FUNCTIONS + POSITION determine a certain function for a certain set of pins.
+  The knowledge of the functions and positions and it's machine-specific
+  particulars is kept inside the pinmux driver, from the outside only the
+  enumerators are known, and the driver core can request the name of a function
+  with a certain selector (>= 0) or the list of pins belonging to a certain
+  function selector + position.
+
+- FUNCTIONS with POSITIONs on a certain PIN CONTROLLER are MAPPED to a certain
+  device by the board file, device tree or similar machine setup configuration
+  mechanism, similar to how regulators are connected to devices, usually by
+  name. Defining a pin controller, function and position thus uniquely identify
+  the set of pins to be used by a certain device.
+
+  In the example case we can define that this particular machine shall
+  use device spi0 with pinmux function fspi0 position 0 and i2c0 on function
+  fi2c0  position 1, on the primary pin controller, we get quadruple mappings
+  like these:
+  { {spi0, pinctrl0, fspi0, 0}, {i2c0, pinctrl0, fi2c0, 1} }
+
+- FUNCTIONS on a certain POSITION on a certain PIN CONTROLLER are provided
+  on a first-come first-serve basis, so if some other device mux setting or
+  GPIO pin request has already taken your physical pin, you will be denied the
+  use of it. To get (activate) a new setting, the old one has to be put
+  (deactivated) first.
+
+Sometimes the documentation and hardware registers will be oriented around
+pads (or "fingers") rather than pins - these are the soldering surfaces on the
+silicon inside the package, and may or may not match the actual number of
+pins/balls underneath the capsule. Pick some enumeration that makes sense to
+you. Define enumerators only for the pins you can control if that makes sense.
+
+Assumptions:
+
+We assume that the number possible function maps to pins is limited by the
+hardware. I.e. we assume that there is no system where any function can be
+mapped to any pin, like in a phone exchange. So the available pins groups for
+a certain function will be limited to a few choices (say up to eight or so),
+not hundreds or any amount of choices. This is the characteristic we have found
+by inspecting available pinmux hardware.
+
+
+Pinmux drivers
+==============
+
+It is the responsibility of the pinmux driver to determine whether or not
+the requested function can actually be enabled, and in that case poke the
+hardware so that this happens.
+
+The driver will for all calls be provided an offset pin number into its own
+pin range. If you have 2 chips with 8x8 pins, the first chips pins will have
+numbers 0 thru 63 and the second one pins 64 thru 127, but the driver for the
+second chip will be passed numbers in the range 0 thru 63 anyway, base offset
+subtracted.
+
+Pinmux drivers are required to supply a few callback functions, some are
+optional. Usually the enable() and disable() functions are implemented,
+writing values into some certain registers to activate a certain mux setting
+for a certain pin.
+
+A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
+into some register named MUX to select a certain function on a certain position
+would works something like this:
+
+#include <linux/pinctrl/pinmux.h>
+
+struct foo_pmx_position {
+	unsigned pos;
+	const unsigned int *pins;
+	const unsigned num_pins;
+	u8 regbit;
+}
+
+struct foo_pmx_func {
+	char *name;
+	struct positions*;
+	unsigned num_positions;
+};
+
+static unsigned int spi0_0_pins[] = { 0, 8, 16, 24 };
+static unsigned int spi0_1_pins[] = { 38, 46, 54, 62 };
+
+static struct foo_pmx_position spi0_positions[] = {
+       {
+		.pos = 0,
+		.pins = spi0_0_pins,
+		.num_pins = ARRAY_SIZE(spi0_1_pins),
+		.regbit = 0x01,
+       },
+       {
+		.pos = 1,
+		.pins = spi0_1_pins,
+		.num_pins = ARRAY_SIZE(spi0_1_pins),
+		.regbit = 0x02,
+       },
+};
+
+static unsigned int i2c0_pins[] = { 24, 25 };
+
+static struct foo_pmx_position i2c0_positions[] = {
+       {
+		.pos = 0,
+		.pins = i2c0_pins,
+		.num_pins = ARRAY_SIZE(spi0_1_pins),
+		.regbit = 0x04,
+       },
+};
+
+static unsigned int mmc0_1_pins[] = { 56, 57 };
+static unsigned int mmc0_2_pins[] = { 56, 57, 58, 59 };
+static unsigned int mmc0_3_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63 };
+
+static struct foo_pmx_position mmc0_positions[] = {
+       {
+		.pos = 0,
+		.pins = mmc0_1_pins,
+		.num_pins = ARRAY_SIZE(mmc0_1_pins),
+		.regbit = 0x08,
+       },
+       {
+		.pos = 1,
+		.pins = mmc0_2_pins,
+		.num_pins = ARRAY_SIZE(mmc0_2_pins),
+		.regbit = 0x10,
+       },
+       {
+		.pos = 2,
+		.pins = mmc0_3_pins,
+		.num_pins = ARRAY_SIZE(mmc0_3_pins),
+		.regbit = 0x20,
+       },
+};
+
+static struct foo_pmx_func myfuncs[] = {
+	{
+		.name = "spi0",
+		.positions = spi0_positions,
+		.num_positions = ARRAY_SIZE(spi0_positions),
+	},
+	{
+		.name = "i2c0",
+		.positions = i2c0_positions,
+		.num_positions = ARRAY_SIZE(i2c0_positions),
+	},
+	{
+		.name = "mmc0",
+		.positions = mmc0_positions,
+		.num_positions = ARRAY_SIZE(mmc0_positions),
+	},
+};
+
+int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
+{
+	if (selector >= ARRAY_SIZE(myfuncs))
+		return -EINVAL;
+	return 0;
+}
+
+int foo_list_positions(struct pinctrl_dev *pctldev, unsigned selector,
+    			unsigned position)
+{
+	if (selector >= ARRAY_SIZE(myfuncs))
+		return -EINVAL;
+	if (position >= myfuncs[selector].num_positions)
+		return -EINVAL;
+	return 0;
+}
+
+const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
+{
+	return myfuncs[selector].name;
+}
+
+static int foo_get_pins(struct pinctrl_dev *pctldev, unsigned selector,
+       	   		unsigned position, unsigned ** const pins,
+			unsigned * const num_pins)
+{
+	*pins = myfuncs[selector].positions[position].pins;
+	*num_pins = myfuncs[selector].positions[position].num_pins;
+	return 0;
+}
+
+int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
+    		unsigned position)
+{
+	u8 regbit = myfuncs[selector].positions[position].regbit;
+
+	writeb((readb(MUX)|regbit), MUX)
+	return 0;
+}
+
+int foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
+    		unsigned position)
+{
+	u8 regbit = myfuncs[selector].positions[position].regbit;
+
+	writeb((readb(MUX) & ~(regbit)), MUX)
+	return 0;
+}
+
+struct pinmux_ops pmxops = {
+	.list_functions = foo_list_funcs,
+	.list_positions = foo_list_positions,
+	.get_function_name = foo_get_fname,
+	.get_function_pins = foo_get_pins,
+	.enable = foo_enable,
+	.disable = foo_disable,
+};
+
+/* Pinmux operations are handled by some pin controller */
+static struct pinctrl_desc foo_desc = {
+	...
+	.pmxops = pmxops,
+};
+
+Now the able reader will say: "wait - the driver needs to make sure it
+can set this and that bit at the same time, because else it will collide
+and wreak havoc in my electronics, and make sure noone else is using the
+other setting that it's incompatible with".
+
+In the example activating muxing 0 and 1 at the same time setting bits
+0 and 1, uses one pin in common so they would collide.
+
+The beauty of the pinmux subsystem is that since it keeps track of all
+pins and who is using them, it will already have denied an impossible
+request like that, so the driver does not need to worry about such
+things - when it gets a selector passed in, the pinmux subsystem makes
+sure no other device or GPIO assignment is already using the selected
+pins.
+
+The above functions except .list_positions are mandatory to implement for
+a pinmux driver. For hardware where each function can only exist in one
+position, you can omit this functions, and position 0 will be passed to all
+calls.
+
+
+Pinmux interaction with the GPIO subsystem
+==========================================
+
+The function list could become long, especially if you can convert every
+individual pin into a GPIO pin independent of any other pins, then your
+function array can become 64 entries for each GPIO setting and then the
+device functions. For this reason there is an additional function you
+can implement to enable only GPIO on an individual pin: pinmux_request_gpio()
+and pinmux_free_gpio().
+
+These functions use the .gpio_base and .gpio_pins members of the pin
+controller as described above for the pin controller, to look up the target
+pin controller.
+
+
+Pinmux board/machine configuration
+==================================
+
+Boards and machines define how a certain complete running system is put
+together, including how GPIOs and devices are muxed, how regulators are
+constrained and how the clock tree looks. Of course pinmux settings are also
+part of this.
+
+A pinmux config for a machine looks pretty much like a simple regulator
+configuration, so for the example array above we want to enable i2c and
+spi on the second function mapping:
+
+#include <linux/pinctrl/machine.h>
+
+static struct pinmux_map pmx_mapping[] = {
+	{
+		.ctrl_dev_name = "pinctrl.0",
+		.function = "spi0",
+		.position = 1,
+		.dev_name = "foo-spi.0",
+	},
+	{
+		.ctrl_dev_name = "pinctrl.0",
+		.function = "i2c0",
+		.position = 0,
+		.dev_name = "foo-i2c.0",
+	},
+	{
+		.ctrl_dev_name = "pinctrl.0",
+		.function = "mmc0",
+		.position = 1,
+		.dev_name = "foo-mmc.0",
+	},
+};
+
+As you can see we may have several pin controllers on the system and thus
+we need to specify which one of them that contain the functions we wish
+to map. The map can also use struct device * directly, so there is no
+inherent need to use strings to specify .dev_name or .ctrl_dev_name, these
+are for the situation where you do not have a handle to the struct device *,
+for example if they are not yet instantiated or cumbersome to obtain.
+
+Since the above construct is pretty common there is a helper macro to make
+it even more compact which assumes you want to use pinctrl.0 and position
+0 for mapping, for example:
+
+static struct pinmux_map pmx_mapping[] = {
+       PINMUX_MAP_PRIMARY("i2c0", "foo-i2c.0"),
+};
+
+The dev_name here matches to the unique device name that can be used to look
+up the device struct (just like with clockdev or regulators). The function name
+must match a function provided by the pinmux driver handling this pin range.
+You register this pinmux mapping to the pinmux subsystem by simply:
+
+       ret = pinmux_register_mappings(&pmx_mapping, ARRAY_SIZE(pmx_mapping));
+
+
+Pinmux requests from drivers
+============================
+
+A driver may request a certain mux to be activated, usually just the default
+mux like this:
+
+#include <linux/pinctrl/pinmux.h>
+
+struct foo_state {
+       struct pinmux *pmx;
+       ...
+};
+
+foo_probe()
+{
+	/* Allocate a state holder named "state" etc */
+	struct pinmux pmx;
+
+	pmx = pinmux_get(&device, NULL);
+	if IS_ERR(pmx)
+		return PTR_ERR(pmx);
+	pinmux_enable(pmx);
+
+	state->pmx = pmx;
+}
+
+foo_remove()
+{
+	pinmux_disable(state->pmx);
+	pinmux_put(state->pmx);
+}
+
+If you want to grab a specific mux mapping and not just the first one found for
+this device you can specify a specific mapping name, for example in the above
+example the second i2c0 setting: pinmux_get(&device, "spi0-pos-B");
+
+This get/enable/disable/put sequence can just as well be handled by bus drivers
+if you don't want each and every driver to handle it and you know the
+arrangement on your bus.
+
+The semantics of the get/enable respective disable/put is as follows:
+
+- pinmux_get() is called in process context to reserve the pins affected with
+  a certain mapping and set up the pinmux core and the driver. It will allocate
+  a struct from the kernel memory to hold the pinmux state.
+
+- pinmux_enable()/pinmux_disable() is quick and can be called from fastpath
+  (irq context) when you quickly want to set up/tear down the hardware muxing
+  when running a device driver. Usually it will just poke some values into a
+  register.
+
+- pinmux_disable() is called in process context to tear down the pin requests
+  and release the state holder struct for the mux setting.
+
+Usually the pinmux core handled the get/put pair and call out to the device
+drivers bookkeeping operations, like checking available functions and the
+associated pins, whereas the enable/disable pass on to the pin controller
+driver which takes care of activating and/or deactivating the mux setting by
+quickly poking some registers.
+
+The pins are allocated for your device when you issue the pinmux_get() call,
+after this you should be able to see this in the debugfs listing of all pins.
+
+
+Runtime pinmuxing
+=================
+
+It is possible to mux a certain function in and out at runtime, say to move
+an SPI port from one set of pins to another set of pins. Say for example for
+spi0 in the example above, we expose two different positions in the mapping
+to achieve this:
+
+static struct pinmux_map pmx_mapping[] = {
+	{
+		.name = "spi0-pos-A",
+		.ctrl_dev_name = "pinctrl.0",
+		.function = "spi0",
+		.position = 0,
+		.dev_name = "foo-spi.0",
+	},
+	{
+		.name = "spi0-pos-B",
+		.ctrl_dev_name = "pinctrl.0",
+		.function = "spi0",
+		.position = 1,
+		.dev_name = "foo-spi.0",
+	},
+	...
+};
+
+This snippet first muxes the function in position A, enables it, disables
+and releases it, and muxes it in on position B:
+
+foo_switch()
+{
+	struct pinmux pmx;
+
+	/* Enable on position A */
+	pmx = pinmux_get(&device, "spi0-pos-A");
+	if IS_ERR(pmx)
+		return PTR_ERR(pmx);
+	pinmux_enable(pmx);
+
+	/* This releases the pins again */
+	pinmux_disable(pmx);
+	pinmux_put(pmx);
+
+	/* Enable on position B */
+	pmx = pinmux_get(&device, "spi0-pos-B");
+	if IS_ERR(pmx)
+		return PTR_ERR(pmx);
+	pinmux_enable(pmx);
+	...
+}
+
+The above has to be done from process context.
diff --git a/MAINTAINERS b/MAINTAINERS
index 1d445f5..8c422d6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5001,6 +5001,11 @@ L:	linux-mtd@lists.infradead.org
 S:	Maintained
 F:	drivers/mtd/devices/phram.c
 
+PINMUX SUBSYSTEM
+M:	Linus Walleij <linus.walleij@linaro.org>
+S:	Maintained
+F:	drivers/pinmux/
+
 PKTCDVD DRIVER
 M:	Peter Osterlund <petero2@telia.com>
 S:	Maintained
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 95b9e7e..40d3e16 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -56,6 +56,10 @@ source "drivers/pps/Kconfig"
 
 source "drivers/ptp/Kconfig"
 
+# pinctrl before gpio - gpio drivers may need it
+
+source "drivers/pinctrl/Kconfig"
+
 source "drivers/gpio/Kconfig"
 
 source "drivers/w1/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 7fa433a..e7afb3a 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -5,6 +5,8 @@
 # Rewritten to use lists instead of if-statements.
 #
 
+# GPIO must come after pinctrl as gpios may need to mux pins etc
+obj-y				+= pinctrl/
 obj-y				+= gpio/
 obj-$(CONFIG_PCI)		+= pci/
 obj-$(CONFIG_PARISC)		+= parisc/
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
new file mode 100644
index 0000000..adb0be0
--- /dev/null
+++ b/drivers/pinctrl/Kconfig
@@ -0,0 +1,29 @@
+#
+# PINCTRL infrastructure and drivers
+#
+
+menuconfig PINCTRL
+	bool "PINCTRL Support"
+	depends on SYSFS && EXPERIMENTAL
+	help
+	  This enables the PINCTRL subsystem for controlling pins
+	  on chip packages, for example multiplexing pins on primarily
+	  PGA and BGA packages for systems on chip.
+
+	  If unsure, say N.
+
+if PINCTRL
+
+config PINMUX
+	bool "Support pinmux controllers"
+	help
+	  Say Y here if you want the pincontrol subsystem to handle pin
+	  multiplexing.
+
+config DEBUG_PINCTRL
+	bool "Debug PINCTRL calls"
+	depends on DEBUG_KERNEL
+	help
+	  Say Y here to add some extra checks and diagnostics to PINCTRL calls.
+
+endif
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
new file mode 100644
index 0000000..596ce9f
--- /dev/null
+++ b/drivers/pinctrl/Makefile
@@ -0,0 +1,6 @@
+# generic pinmux support
+
+ccflags-$(CONFIG_DEBUG_PINMUX)	+= -DDEBUG
+
+obj-$(CONFIG_PINCTRL)		+= core.o
+obj-$(CONFIG_PINMUX)		+= pinmux.o
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
new file mode 100644
index 0000000..762e9e8
--- /dev/null
+++ b/drivers/pinctrl/core.c
@@ -0,0 +1,539 @@
+/*
+ * Core driver for the pin control subsystem
+ *
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ * Based on bits of regulator core, gpio core and clk core
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#define pr_fmt(fmt) "pinctrl core: " fmt
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/radix-tree.h>
+#include <linux/err.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/sysfs.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/machine.h>
+#include "core.h"
+#include "pinmux.h"
+
+/* Global list of pin control devices */
+static DEFINE_MUTEX(pinctrldev_list_mutex);
+static LIST_HEAD(pinctrldev_list);
+
+/* sysfs interaction */
+static ssize_t pinctrl_name_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct pinctrl_dev *pctldev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%s\n", pctldev_get_name(pctldev));
+}
+
+static void pinctrl_dev_release(struct device *dev)
+{
+	struct pinctrl_dev *pctldev = dev_get_drvdata(dev);
+	kfree(pctldev);
+}
+
+static DEVICE_ATTR(name, S_IRUGO, pinctrl_name_show, NULL);
+
+static struct attribute *pinctrl_dev_attrs[] = {
+	&dev_attr_name.attr,
+	NULL
+};
+
+static struct attribute_group pinctrl_dev_attr_group = {
+	.attrs = pinctrl_dev_attrs,
+};
+
+static const struct attribute_group *pinctrl_dev_attr_groups[] = {
+	&pinctrl_dev_attr_group,
+	NULL
+};
+
+static struct bus_type pinctrl_bus = {
+	.name = "pinctrl",
+};
+
+static struct device_type pinctrl_type = {
+	.groups = pinctrl_dev_attr_groups,
+	.release = pinctrl_dev_release,
+};
+
+/**
+ * Looks up a pin control device matching a certain pinmux map
+ */
+struct pinctrl_dev *get_pctrldev_for_pinmux_map(struct pinmux_map const *map)
+{
+	struct pinctrl_dev *pctldev = NULL;
+	bool found = false;
+
+	mutex_lock(&pinctrldev_list_mutex);
+	list_for_each_entry(pctldev, &pinctrldev_list, node) {
+		if (map->ctrl_dev &&  &pctldev->dev == map->ctrl_dev) {
+			/* Matched on device */
+			found = true;
+			break;
+		}
+
+		if (map->ctrl_dev_name &&
+		    !strcmp(dev_name(&pctldev->dev), map->ctrl_dev_name)) {
+			/* Matched on device name */
+			found = true;
+			break;
+		}
+	}
+	mutex_unlock(&pinctrldev_list_mutex);
+
+	if (found)
+		return pctldev;
+
+	return NULL;
+}
+
+struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev, int pin)
+{
+	struct pin_desc *pindesc;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pctldev->pin_desc_tree_lock, flags);
+	pindesc = radix_tree_lookup(&pctldev->pin_desc_tree, pin);
+	spin_unlock_irqrestore(&pctldev->pin_desc_tree_lock, flags);
+
+	return pindesc;
+}
+
+/**
+ * Tell us whether a certain pin exist on a certain pin controller
+ * or not. Pin lists may be sparse, so some pins may not exist.
+ * @pctldev: the pin control device to check the pin on
+ * @pin: pin to check, use the local pin controller index number
+ */
+bool pin_is_valid(struct pinctrl_dev *pctldev, int pin)
+{
+	struct pin_desc *pindesc;
+
+	if (pin < 0)
+		return false;
+
+	pindesc = pin_desc_get(pctldev, pin);
+	if (pindesc == NULL)
+		return false;
+
+	return true;
+}
+EXPORT_SYMBOL_GPL(pin_is_valid);
+
+/* Deletes a range of pin descriptors */
+static void pinctrl_free_pindescs(struct pinctrl_dev *pctldev,
+				  const struct pinctrl_pin_desc *pins,
+				  unsigned num_pins)
+{
+	int i;
+
+	spin_lock(&pctldev->pin_desc_tree_lock);
+	for (i = 0; i < num_pins; i++) {
+		struct pin_desc *pindesc;
+
+		pindesc = radix_tree_lookup(&pctldev->pin_desc_tree,
+					    pins[i].number);
+		if (pindesc != NULL) {
+			radix_tree_delete(&pctldev->pin_desc_tree,
+					  pins[i].number);
+		}
+		kfree(pindesc);
+	}
+	spin_unlock(&pctldev->pin_desc_tree_lock);
+}
+
+static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev,
+				    unsigned number, const char *name)
+{
+	struct pin_desc *pindesc;
+
+	pindesc = pin_desc_get(pctldev, number);
+	if (pindesc != NULL) {
+		pr_err("pin %d already registered on %s\n", number,
+		       pctldev->desc->name);
+		return -EINVAL;
+	}
+
+	pindesc = kzalloc(sizeof(*pindesc), GFP_KERNEL);
+	if (pindesc == NULL)
+		return -ENOMEM;
+
+	/* Set owner */
+	pindesc->pctldev = pctldev;
+
+	/* Copy optional basic pin info */
+	if (name)
+		strlcpy(pindesc->name, name, sizeof(pindesc->name));
+
+	spin_lock(&pctldev->pin_desc_tree_lock);
+	radix_tree_insert(&pctldev->pin_desc_tree, number, pindesc);
+	spin_unlock(&pctldev->pin_desc_tree_lock);
+	pr_debug("registered pin %d (%s) on %s\n",
+		 number, name ? name : "(unnamed)", pctldev->desc->name);
+	return 0;
+}
+
+static int pinctrl_register_pins(struct pinctrl_dev *pctldev,
+				 struct pinctrl_pin_desc const *pins,
+				 unsigned num_descs)
+{
+	unsigned i;
+	int ret = 0;
+
+	for (i = 0; i < num_descs; i++) {
+		ret = pinctrl_register_one_pin(pctldev,
+					       pins[i].number, pins[i].name);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * pinctrl_match_gpio_range() - check if a certain GPIO pin is in the range of
+ * a certain pin controller, return the range or NULL
+ */
+static struct pinctrl_gpio_range *
+pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
+{
+	struct pinctrl_gpio_range *range = NULL;
+
+	/* Loop over the ranges */
+	spin_lock(&pctldev->gpio_ranges_lock);
+	list_for_each_entry(range, &pctldev->gpio_ranges, node) {
+		/* Check if we're in the valid range */
+		if (gpio >= range->base &&
+		    gpio < range->base + range->npins) {
+			spin_unlock(&pctldev->gpio_ranges_lock);
+			return range;
+		}
+	}
+	spin_unlock(&pctldev->gpio_ranges_lock);
+
+	return NULL;
+}
+
+/**
+ * pinctrl_get_device_gpio_range() - find the pin controller handling a certain
+ * pin from the pinspace in the GPIO subsystem, return the device and the
+ * matching GPIO range. Returns negative if the GPIO range could not be found
+ * in any device
+ * @gpio: the pin to locate the pin controller for
+ * @outdev: the pin control device if found
+ * @outrange: the GPIO range if found
+ */
+int pinctrl_get_device_gpio_range(unsigned gpio,
+				struct pinctrl_dev **outdev,
+				struct pinctrl_gpio_range **outrange)
+{
+	struct pinctrl_dev *pctldev = NULL;
+
+	/* Loop over the pin controllers */
+	mutex_lock(&pinctrldev_list_mutex);
+	list_for_each_entry(pctldev, &pinctrldev_list, node) {
+		struct pinctrl_gpio_range *range;
+
+		range = pinctrl_match_gpio_range(pctldev, gpio);
+		if (range != NULL) {
+			*outdev = pctldev;
+			*outrange = range;
+			return 0;
+		}
+	}
+	mutex_unlock(&pinctrldev_list_mutex);
+
+	return -EINVAL;
+}
+
+/**
+ * pinctrl_add_gpio_range() - this adds a range of GPIOs to be handled
+ * by a certain pin controller. Call this to register handled ranges after
+ * registering your pin controller.
+ * @pctldev: pin controller device to add the range to
+ * @range: the GPIO range to add
+ */
+void pinctrl_add_gpio_range(struct pinctrl_dev *pctldev,
+			    struct pinctrl_gpio_range *range)
+{
+	spin_lock(&pctldev->gpio_ranges_lock);
+	list_add(&range->node, &pctldev->gpio_ranges);
+	spin_unlock(&pctldev->gpio_ranges_lock);
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+static int pinctrl_pins_show(struct seq_file *s, void *what)
+{
+	struct pinctrl_dev *pctldev = s->private;
+	unsigned pin;
+
+	seq_printf(s, "registered pins: %d\n", pctldev->desc->npins);
+	seq_printf(s, "max pin number: %d\n", pctldev->desc->maxpin);
+
+	/* The highest pin number need to be included in the loop, thus <= */
+	for (pin = 0; pin <= pctldev->desc->maxpin; pin++) {
+		struct pin_desc *desc;
+
+		desc = pin_desc_get(pctldev, pin);
+		/* Pin space may be sparse */
+		if (desc == NULL)
+			continue;
+
+		seq_printf(s, "pin %d (%s)\n", pin,
+			   desc->name ? desc->name : "unnamed");
+	}
+
+	return 0;
+}
+
+static int pinctrl_gpioranges_show(struct seq_file *s, void *what)
+{
+	struct pinctrl_dev *pctldev = s->private;
+	struct pinctrl_gpio_range *range = NULL;
+
+	seq_puts(s, "GPIO ranges handled:\n");
+
+	/* Loop over the ranges */
+	spin_lock(&pctldev->gpio_ranges_lock);
+	list_for_each_entry(range, &pctldev->gpio_ranges, node) {
+		seq_printf(s, "%u: %s [%u - %u]\n", range->id, range->name,
+			   range->base, (range->base + range->npins - 1));
+	}
+	spin_unlock(&pctldev->gpio_ranges_lock);
+
+	return 0;
+}
+
+static int pinctrl_devices_show(struct seq_file *s, void *what)
+{
+	struct pinctrl_dev *pctldev;
+
+	seq_puts(s, "name [pinmux]\n");
+	mutex_lock(&pinctrldev_list_mutex);
+	list_for_each_entry(pctldev, &pinctrldev_list, node) {
+		seq_printf(s, "%s ", pctldev->desc->name);
+		if (pctldev->desc->pmxops)
+			seq_puts(s, "yes");
+		else
+			seq_puts(s, "no");
+		seq_puts(s, "\n");
+	}
+	mutex_unlock(&pinctrldev_list_mutex);
+
+	return 0;
+}
+
+static int pinctrl_pins_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, pinctrl_pins_show, inode->i_private);
+}
+
+static int pinctrl_gpioranges_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, pinctrl_gpioranges_show, inode->i_private);
+}
+
+static int pinctrl_devices_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, pinctrl_devices_show, NULL);
+}
+
+static const struct file_operations pinctrl_pins_ops = {
+	.open		= pinctrl_pins_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static const struct file_operations pinctrl_gpioranges_ops = {
+	.open		= pinctrl_gpioranges_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static const struct file_operations pinctrl_devices_ops = {
+	.open		= pinctrl_devices_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static struct dentry *debugfs_root;
+
+static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
+{
+	static struct dentry *device_root;
+
+	device_root = debugfs_create_dir(dev_name(&pctldev->dev),
+					 debugfs_root);
+	if (IS_ERR(device_root) || !device_root) {
+		pr_warn("failed to create debugfs directory for %s\n",
+			dev_name(&pctldev->dev));
+		return;
+	}
+	debugfs_create_file("pins", S_IFREG | S_IRUGO,
+			    device_root, pctldev, &pinctrl_pins_ops);
+	debugfs_create_file("gpio-ranges", S_IFREG | S_IRUGO,
+			    device_root, pctldev, &pinctrl_gpioranges_ops);
+	pinmux_init_device_debugfs(device_root, pctldev);
+}
+
+static void pinctrl_init_debugfs(void)
+{
+	debugfs_root = debugfs_create_dir("pinctrl", NULL);
+	if (IS_ERR(debugfs_root) || !debugfs_root) {
+		pr_warn("failed to create debugfs directory\n");
+		debugfs_root = NULL;
+		return;
+	}
+
+	debugfs_create_file("pinctrl-devices", S_IFREG | S_IRUGO,
+			    debugfs_root, NULL, &pinctrl_devices_ops);
+	pinmux_init_debugfs(debugfs_root);
+}
+
+#else /* CONFIG_DEBUG_FS */
+
+static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
+{
+}
+
+static void pinctrl_init_debugfs(void)
+{
+}
+
+#endif
+
+/**
+ * pinctrl_register() - register a pin controller device
+ * @pctldesc: descriptor for this pin controller
+ * @dev: parent device for this pin controller
+ * @driver_data: private pin controller data for this pin controller
+ */
+struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
+				    struct device *dev, void *driver_data)
+{
+	static atomic_t pinmux_no = ATOMIC_INIT(0);
+	struct pinctrl_dev *pctldev;
+	int ret;
+
+	if (pctldesc == NULL)
+		return ERR_PTR(-EINVAL);
+	if (pctldesc->name == NULL)
+		return ERR_PTR(-EINVAL);
+
+	/* If we're implementing pinmuxing, check the ops for sanity */
+	if (pctldesc->pmxops) {
+		ret = pinmux_check_ops(pctldesc->pmxops);
+		if (ret)
+			return ERR_PTR(ret);
+	}
+
+	pctldev = kzalloc(sizeof(struct pinctrl_dev), GFP_KERNEL);
+	if (pctldev == NULL)
+		return ERR_PTR(-ENOMEM);
+
+	/* Initialize pin control device struct */
+	pctldev->owner = pctldesc->owner;
+	pctldev->desc = pctldesc;
+	pctldev->driver_data = driver_data;
+	INIT_RADIX_TREE(&pctldev->pin_desc_tree, GFP_KERNEL);
+	spin_lock_init(&pctldev->pin_desc_tree_lock);
+	INIT_LIST_HEAD(&pctldev->gpio_ranges);
+	spin_lock_init(&pctldev->gpio_ranges_lock);
+
+	/* Register device with sysfs */
+	pctldev->dev.parent = dev;
+	pctldev->dev.bus = &pinctrl_bus;
+	pctldev->dev.type = &pinctrl_type;
+	dev_set_name(&pctldev->dev, "pinctrl.%d",
+		     atomic_inc_return(&pinmux_no) - 1);
+	ret = device_register(&pctldev->dev);
+	if (ret != 0) {
+		pr_err("error in device registration\n");
+		put_device(&pctldev->dev);
+		kfree(pctldev);
+		goto out_err;
+	}
+	dev_set_drvdata(&pctldev->dev, pctldev);
+
+	/* Register all the pins */
+	pr_debug("try to register %d pins on %s...\n",
+		 pctldesc->npins, pctldesc->name);
+	ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins);
+	if (ret) {
+		pr_err("error during pin registration\n");
+		pinctrl_free_pindescs(pctldev, pctldesc->pins,
+				      pctldesc->npins);
+		goto out_err;
+	}
+
+	pinctrl_init_device_debugfs(pctldev);
+	mutex_lock(&pinctrldev_list_mutex);
+	list_add(&pctldev->node, &pinctrldev_list);
+	mutex_unlock(&pinctrldev_list_mutex);
+	return pctldev;
+
+out_err:
+	put_device(&pctldev->dev);
+	kfree(pctldev);
+	return ERR_PTR(ret);
+}
+EXPORT_SYMBOL_GPL(pinctrl_register);
+
+/**
+ * pinctrl_unregister() - unregister pinmux
+ * @pctldev: pin controller to unregister
+ *
+ * Called by pinmux drivers to unregister a pinmux.
+ */
+void pinctrl_unregister(struct pinctrl_dev *pctldev)
+{
+	if (pctldev == NULL)
+		return;
+
+	mutex_lock(&pinctrldev_list_mutex);
+	list_del(&pctldev->node);
+	device_unregister(&pctldev->dev);
+	mutex_unlock(&pinctrldev_list_mutex);
+	/* Destroy descriptor tree */
+	pinctrl_free_pindescs(pctldev, pctldev->desc->pins,
+			      pctldev->desc->npins);
+}
+EXPORT_SYMBOL_GPL(pinctrl_unregister);
+
+static int __init pinctrl_init(void)
+{
+	int ret;
+
+	ret = bus_register(&pinctrl_bus);
+	if (ret) {
+		pr_crit("could not register pinctrl bus\n");
+		return ret;
+	}
+
+	pr_info("initialized pinctrl subsystem\n");
+	pinctrl_init_debugfs();
+	return 0;
+}
+
+/* init early since many drivers really need to initialized pinmux early */
+core_initcall(pinctrl_init);
diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
new file mode 100644
index 0000000..283007c
--- /dev/null
+++ b/drivers/pinctrl/core.h
@@ -0,0 +1,24 @@
+/**
+ * struct pin_desc - pin descriptor for each physical pin in the arch
+ * @pctldev: corresponding pin control device
+ * @name: a name for the pin, e.g. the name of the pin/pad/finger on a
+ *	datasheet or such
+ * @mux_requested: whether the pin is already requested by pinmux or not
+ * @mux_function: a named muxing function for the pin that will be passed to
+ *	subdrivers and shown in debugfs etc
+ */
+struct pin_desc {
+	struct pinctrl_dev *pctldev;
+	char	name[16];
+	/* These fields only added when supporting pinmux drivers */
+#ifdef CONFIG_PINMUX
+	bool	mux_requested;
+	char	mux_function[16];
+#endif
+};
+
+struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev, int pin);
+struct pinctrl_dev *get_pctrldev_for_pinmux_map(struct pinmux_map const *map);
+int pinctrl_get_device_gpio_range(unsigned gpio,
+				  struct pinctrl_dev **outdev,
+				  struct pinctrl_gpio_range **outrange);
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
new file mode 100644
index 0000000..310d344
--- /dev/null
+++ b/drivers/pinctrl/pinmux.c
@@ -0,0 +1,811 @@
+/*
+ * Core driver for the pin muxing portions of the pin control subsystem
+ *
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ * Based on bits of regulator core, gpio core and clk core
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#define pr_fmt(fmt) "pinmux core: " fmt
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/radix-tree.h>
+#include <linux/err.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/sysfs.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinmux.h>
+#include "core.h"
+
+/* Global list of pinmuxes */
+static DEFINE_MUTEX(pinmux_list_mutex);
+static LIST_HEAD(pinmux_list);
+
+/**
+ * struct pinmux - per-device pinmux state holder
+ * @node: global list node - only for internal use
+ * @dev: the device using this pinmux
+ * @map: corresponding pinmux map active for this pinmux setting
+ * @usecount: the number of active users of this mux setting, used to keep
+ *	track of nested use cases
+ * @pins: an array of discrete physical pins used in this mapping, taken
+ *	from the global pin enumeration space (copied from pinmux map)
+ * @num_pins: the number of pins in this mapping array, i.e. the number of
+ *	elements in .pins so we can iterate over that array (copied from
+ *	pinmux map)
+ * @pctldev: pin control device handling this pinmux
+ * @pmxdev_selector: the function selector for the pinmux device handling
+ *	this pinmux
+ * @pmxdev_position: the function position for the pinmux device and
+ *	selector handling this pinmux
+ * @mutex: a lock for the pinmux state holder
+ */
+struct pinmux {
+	struct list_head node;
+	struct device *dev;
+	struct pinmux_map const *map;
+	unsigned usecount;
+	struct pinctrl_dev *pctldev;
+	unsigned pmxdev_selector;
+	unsigned pmxdev_position;
+	struct mutex mutex;
+};
+
+/**
+ * pin_request() - request a single pin to be muxed in, typically for GPIO
+ * @pin: the pin number in the global pin space
+ * @function: a functional name to give to this pin, passed to the driver
+ *	so it knows what function to mux in, e.g. the string "gpioNN"
+ *	means that you want to mux in the pin for use as GPIO number NN
+ * @gpio: if this request concerns a single GPIO pin
+ * @gpio_range: the range matching the GPIO pin if this is a request for a
+ *	single GPIO pin
+ */
+static int pin_request(struct pinctrl_dev *pctldev,
+		       int pin, const char *function, bool gpio,
+		       struct pinctrl_gpio_range *gpio_range)
+{
+	struct pin_desc *desc;
+	const struct pinmux_ops *ops;
+	int status = -EINVAL;
+
+	pr_debug("request pin %d for %s\n", pin, function);
+
+	if (!pin_is_valid(pctldev, pin)) {
+		pr_err("pin is invalid\n");
+		return -EINVAL;
+	}
+
+	if (!function) {
+		pr_err("no function name given\n");
+		return -EINVAL;
+	}
+
+	desc = pin_desc_get(pctldev, pin);
+	if (desc == NULL) {
+		pr_err("pin is not registered so it cannot be requested\n");
+		goto out;
+	}
+	if (desc->mux_requested) {
+		pr_err("pin already requested\n");
+		goto out;
+	}
+	ops = pctldev->desc->pmxops;
+
+	/* Let each pin increase references to this module */
+	if (!try_module_get(pctldev->owner)) {
+		pr_err("could not increase module refcount for pin %d\n", pin);
+		status = -EINVAL;
+		goto out;
+	}
+
+	/*
+	 * If there is no kind of request function for the pin we just assume
+	 * we got it by default and proceed.
+	 */
+	if (gpio && ops->gpio_request_enable)
+		/* This requests and enables a single GPIO pin */
+		status = ops->gpio_request_enable(pctldev, gpio_range, pin);
+	else if (ops->request)
+		status = ops->request(pctldev, pin);
+	else
+		status = 0;
+
+	if (status) {
+		pr_err("->request on device %s failed "
+		       "for pin %d\n",
+		       pctldev->desc->name, pin);
+		goto out;
+	}
+
+	desc->mux_requested = true;
+	strncpy(desc->mux_function, function, sizeof(desc->mux_function));
+
+out:
+	if (status)
+		pr_err("pin-%d (%s) status %d\n",
+		       pin, function ? : "?", status);
+
+	return status;
+}
+
+/**
+ * pin_free() - release a single muxed in pin so something else can be muxed in
+ *	instead
+ * @pin: the pin to free
+ */
+static void pin_free(struct pinctrl_dev *pctldev, int pin)
+{
+	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+	struct pin_desc *desc;
+
+	desc = pin_desc_get(pctldev, pin);
+	if (desc == NULL) {
+		pr_err("pin is not registered so it cannot be freed\n");
+		return;
+	}
+
+	if (ops->free)
+		ops->free(pctldev, pin);
+
+	desc->mux_requested = false;
+	desc->mux_function[0] = '\0';
+	module_put(pctldev->owner);
+}
+
+/**
+ * pinmux_request_gpio() - request a single pin to be muxed in to be used
+ *	as a GPIO pin
+ * @gpio: the GPIO pin number from the GPIO subsystem number space
+ */
+int pinmux_request_gpio(unsigned gpio)
+{
+	char gpiostr[16];
+	struct pinctrl_dev *pctldev;
+	struct pinctrl_gpio_range *range;
+	int ret;
+	int pin;
+
+	ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
+	if (ret)
+		return -EINVAL;
+
+	/* Convert to the pin controllers number space */
+	pin = gpio - range->base;
+
+	/* Conjure some name stating what chip and pin this is taken by */
+	snprintf(gpiostr, 15, "%s:%d", range->name, gpio);
+
+	return pin_request(pctldev, pin, gpiostr, true, range);
+}
+EXPORT_SYMBOL_GPL(pinmux_request_gpio);
+
+/**
+ * pinmux_free_gpio() - free a single pin, currently muxed in to be used
+ *	as a GPIO pin
+ * @gpio: the GPIO pin number from the GPIO subsystem number space
+ */
+void pinmux_free_gpio(unsigned gpio)
+{
+	struct pinctrl_dev *pctldev;
+	struct pinctrl_gpio_range *range;
+	int ret;
+	int pin;
+
+	ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
+	if (ret)
+		return;
+
+	/* Convert to the pin controllers number space */
+	pin = gpio - range->base;
+
+	pin_free(pctldev, pin);
+}
+EXPORT_SYMBOL_GPL(pinmux_free_gpio);
+
+int pinmux_register_mappings(struct pinmux_map const *maps, unsigned num_maps)
+{
+	int ret = 0;
+	int i;
+
+	pr_debug("add %d functions\n", num_maps);
+	for (i = 0; i < num_maps; i++) {
+		struct pinmux *pmx;
+
+		/* Sanity check the mapping */
+		if (!maps[i].function) {
+			pr_err("failed to register map %d - no function ID given\n", i);
+			ret = -EINVAL;
+			goto out;
+		}
+
+		if (!maps[i].dev && !maps[i].dev_name)
+			pr_debug("add anonymous function %s with no device\n",
+				 maps[i].function);
+
+		/*
+		 * create the state cookie holder struct pinmux for each
+		 * mapping, this is what consumers will get when requesting
+		 * a pinmux handle with pinmux_get()
+		 */
+		pmx = kzalloc(sizeof(struct pinmux), GFP_KERNEL);
+		if (pmx == NULL) {
+			ret = -ENOMEM;
+			goto out;
+		}
+		mutex_init(&pmx->mutex);
+		pmx->map = &maps[i];
+
+		/* Add the pinmux */
+		mutex_lock(&pinmux_list_mutex);
+		list_add(&pmx->node, &pinmux_list);
+		mutex_unlock(&pinmux_list_mutex);
+		pr_debug("add function %s\n", maps[i].function);
+	}
+
+out:
+	return ret;
+}
+
+/**
+ * acquire_pins() - acquire all the pins for a certain funcion on a certain
+ *	pinmux device
+ * @pctldev: the device to take the pins on
+ * @selector: the function selector to acquire the pins for
+ * @position: the function position to acquire the pins for
+ */
+static int acquire_pins(struct pinctrl_dev *pctldev, unsigned selector,
+			unsigned position)
+{
+	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+	unsigned *pins;
+	unsigned num_pins;
+	const char *func = ops->get_function_name(pctldev, selector);
+	int ret;
+	int i;
+
+	ret = ops->get_function_pins(pctldev, selector, position,
+				     &pins, &num_pins);
+	if (ret)
+		return ret;
+
+	/* Try to allocate all pins in this pinmux map, one by one */
+	for (i = 0; i < num_pins; i++) {
+		ret = pin_request(pctldev, pins[i], func, false, NULL);
+		if (ret) {
+			pr_err("could not get pin %d for function %s "
+			       "on device %s - conflicting mux mappings?\n",
+			       pins[i], func ? : "(undefined)",
+			       pctldev->desc->name);
+			/* On error release all taken pins */
+			i--; /* this pin just failed */
+			for (; i >= 0; i--)
+				pin_free(pctldev, pins[i]);
+			return -ENODEV;
+		}
+	}
+	return 0;
+}
+
+/**
+ * release_pins() - release pins taken by earlier acquirement
+ * @pctldev: the device to free the pinx on
+ * @selector: the function selector to free the pins for
+ * @position: the function position to release the pins for
+ */
+static void release_pins(struct pinctrl_dev *pctldev, unsigned selector,
+			 unsigned position)
+{
+	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+	unsigned *pins;
+	unsigned num_pins;
+	int ret;
+	int i;
+
+	ret = ops->get_function_pins(pctldev, selector, position,
+				     &pins, &num_pins);
+	if (ret) {
+		dev_err(&pctldev->dev, "could not get pins to release for "
+			"selector %d, position %d\n",
+			selector, position);
+		return;
+	}
+	for (i = 0; i < num_pins; i++)
+		pin_free(pctldev, pins[i]);
+}
+
+/**
+ * pinmux_check_position() - check that the pinmux driver can supply the
+ * function in a certain position
+ * @pctldev: device to check the position for
+ * @selector: the selector to check the position for
+ * @position: the position to check
+ */
+static int pinmux_check_position(struct pinctrl_dev *pctldev,
+				 unsigned selector, unsigned position)
+{
+	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+	unsigned posit = 0;
+
+	/*
+	 * If the driver does not support different positions for the
+	 * functions, we only support position 0.
+	 */
+	if (!ops->list_positions) {
+		if (position != 0)
+			return -EINVAL;
+		return 0;
+	}
+
+	/* Else check that we support this position */
+	while (ops->list_positions(pctldev, selector, posit) >= 0) {
+		if (posit == position)
+			return 0;
+		posit++;
+	}
+
+	pr_err("%s does not support pinmux position %d for function %s\n",
+	       pctldev_get_name(pctldev), position,
+	       ops->get_function_name(pctldev, selector));
+	return -EINVAL;
+}
+
+/**
+ * pinmux_search_function() - search the pinmux driver for an applicable
+ * function in a specific position, returns the applicable selector if
+ * found
+ * @pctldev: device to check for function and position
+ * @map: function map containing the function and position to look for
+ */
+static int pinmux_search_function(struct pinctrl_dev *pctldev,
+				  struct pinmux_map const *map)
+{
+	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+	unsigned selector = 0;
+
+	/* See if this pctldev has this function */
+	while (ops->list_functions(pctldev, selector) >= 0) {
+		const char *fname = ops->get_function_name(pctldev,
+							   selector);
+		int ret;
+
+		if (!strcmp(map->function, fname)) {
+			/* Found the function, check position */
+			ret = pinmux_check_position(pctldev, selector,
+						    map->position);
+			if (ret < 0)
+				return ret;
+			return selector;
+		}
+		selector++;
+	}
+
+	pr_err("%s does not support function %s\n",
+	       pctldev_get_name(pctldev), map->function);
+	return -EINVAL;
+}
+
+
+/**
+ * pinmux_get() - retrieves the pinmux for a certain device
+ * @dev: the device to get the pinmux for
+ * @name: an optional specific mux mapping name or NULL, the name is only
+ *	needed if you want to have more than one mapping per device, or if you
+ *	need an anonymous pinmux (not tied to any specific device)
+ */
+struct pinmux *pinmux_get(struct device *dev, const char *name)
+{
+
+	struct pinmux_map const *map = NULL;
+	struct pinctrl_dev *pctldev = NULL;
+	const char *devname = NULL;
+	struct pinmux *pmx;
+	bool found_map = false;
+	int ret = -ENODEV;
+
+	/* We must have dev or ID or both */
+	if (!dev && !name)
+		return ERR_PTR(-EINVAL);
+
+	mutex_lock(&pinmux_list_mutex);
+
+	if (dev)
+		devname = dev_name(dev);
+
+	/* Iterate over the pinmux maps to locate the right one */
+	list_for_each_entry(pmx, &pinmux_list, node) {
+		map = pmx->map;
+
+		/*
+		 * First, try to find the pctldev given in the map
+		 */
+		pctldev = get_pctrldev_for_pinmux_map(map);
+		if (!pctldev) {
+			const char *devname = NULL;
+
+			if (map->ctrl_dev)
+				devname = dev_name(map->ctrl_dev);
+			else if (map->ctrl_dev_name)
+				devname = map->ctrl_dev_name;
+
+			pr_warning("could not find a pinctrl device for pinmux "
+				   "function %s, fishy, they shall all have one\n",
+				   map->function);
+			pr_warning("given pinctrl device name: %s",
+				   devname ? devname : "UNDEFINED");
+
+			/* Continue to check the other mappings anyway... */
+			continue;
+		}
+
+		pr_debug("found pctldev %s to handle function %s",
+			 dev_name(&pctldev->dev), map->function);
+
+
+		/*
+		 * If we're looking for a specific named map, this must match,
+		 * else we loop and look for the next.
+		 */
+		if (name != NULL) {
+			if (map->name == NULL)
+				continue;
+			if (strcmp(map->name, name))
+				continue;
+		}
+
+		/*
+		 * This is for the case where no device name is given, we
+		 * already know that the function name matches from above
+		 * code.
+		 */
+		if (!map->dev_name && (name != NULL)) {
+			found_map = true;
+			break;
+		}
+
+		/* If the mapping has a device set up it must match */
+		if (map->dev_name &&
+		    (!devname || !strcmp(map->dev_name, devname))) {
+			/* MATCH! */
+			found_map = true;
+			break;
+		}
+	}
+
+	mutex_unlock(&pinmux_list_mutex);
+
+	if (!found_map) {
+		pr_err("could not find mux map for device %s, ID %s\n",
+		       devname ? devname : "(anonymous)",
+		       name ? name : "(undefined)");
+		goto out;
+	}
+
+	/* Make sure that noone else is using this pinmux */
+	mutex_lock(&pmx->mutex);
+	if (pmx->dev) {
+		if (pmx->dev != dev) {
+			mutex_unlock(&pmx->mutex);
+			pr_err("mapping already in use device %s, ID %s\n",
+			       devname ? devname : "(anonymous)",
+			       name ? name : "(undefined)");
+			goto out;
+		} else {
+			/* We already fetched this and requested pins */
+			mutex_unlock(&pmx->mutex);
+			ret = 0;
+			goto out;
+		}
+	}
+	mutex_unlock(&pmx->mutex);
+
+	/* Now go into the driver and try to locate function @position */
+	ret = pinmux_search_function(pctldev, map);
+	if (ret < 0)
+		goto out;
+	else {
+		/* Found function @position */
+		unsigned selector = ret;
+
+		ret = acquire_pins(pctldev, selector, map->position);
+		if (ret)
+			goto out;
+		/* Found it! */
+		mutex_lock(&pmx->mutex);
+		pmx->dev = dev;
+		pmx->pctldev = pctldev;
+		pmx->pmxdev_selector = selector;
+		pmx->pmxdev_position = map->position;
+		mutex_unlock(&pmx->mutex);
+		ret = 0;
+		goto out;
+	}
+
+	/* We couldn't find the driver for this pinmux */
+	ret = -ENODEV;
+
+out:
+	if (ret)
+		pmx = ERR_PTR(ret);
+
+	return pmx;
+}
+EXPORT_SYMBOL_GPL(pinmux_get);
+
+/**
+ * pinmux_put() - release a previously claimed pinmux
+ * @pmx: a pinmux previously claimed by pinmux_get()
+ */
+void pinmux_put(struct pinmux *pmx)
+{
+	if (pmx == NULL)
+		return;
+	mutex_lock(&pmx->mutex);
+	if (pmx->usecount)
+		pr_warn("releasing pinmux with active users!\n");
+	/* Release all pins taken on pinmux_get() */
+	release_pins(pmx->pctldev, pmx->pmxdev_selector, pmx->pmxdev_position);
+	pmx->dev = NULL;
+	pmx->pctldev = NULL;
+	pmx->pmxdev_selector = 0;
+	mutex_unlock(&pmx->mutex);
+}
+EXPORT_SYMBOL_GPL(pinmux_put);
+
+/**
+ * pinmux_enable() - enable a certain pinmux setting
+ * @pmx: the pinmux to enable, previously claimed by pinmux_get()
+ */
+int pinmux_enable(struct pinmux *pmx)
+{
+	int ret = 0;
+
+	if (pmx == NULL)
+		return -EINVAL;
+	mutex_lock(&pmx->mutex);
+	if (pmx->usecount++ == 0) {
+		struct pinctrl_dev *pctldev = pmx->pctldev;
+		const struct pinmux_ops *ops = pctldev->desc->pmxops;
+
+		ret = ops->enable(pctldev, pmx->pmxdev_selector,
+				  pmx->pmxdev_position);
+		if (ret)
+			pmx->usecount--;
+	}
+	mutex_unlock(&pmx->mutex);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(pinmux_enable);
+
+/**
+ * pinmux_disable() - disable a certain pinmux setting
+ * @pmx: the pinmux to disable, previously claimed by pinmux_get()
+ */
+void pinmux_disable(struct pinmux *pmx)
+{
+	if (pmx == NULL)
+		return;
+
+	mutex_lock(&pmx->mutex);
+	if (--pmx->usecount == 0) {
+		struct pinctrl_dev *pctldev = pmx->pctldev;
+		const struct pinmux_ops *ops = pctldev->desc->pmxops;
+
+		ops->disable(pctldev, pmx->pmxdev_selector,
+			     pmx->pmxdev_position);
+	}
+	mutex_unlock(&pmx->mutex);
+}
+EXPORT_SYMBOL_GPL(pinmux_disable);
+
+/**
+ * pinmux_config() - configure a certain pinmux setting
+ * @pmx: the pinmux setting to configure
+ * @param: the parameter to configure
+ * @data: extra data to be passed to the configuration, also works as a
+ *	pointer to data returned from the function on success
+ */
+int pinmux_config(struct pinmux *pmx, u16 param, unsigned long *data)
+{
+	struct pinctrl_dev *pctldev;
+	const struct pinmux_ops *ops;
+	int ret = 0;
+
+	if (pmx == NULL)
+		return -ENODEV;
+
+	pctldev = pmx->pctldev;
+	ops = pctldev->desc->pmxops;
+
+	/* This operation is not mandatory to implement */
+	if (ops->config) {
+		mutex_lock(&pmx->mutex);
+		ret = ops->config(pctldev, pmx->pmxdev_selector, param, data);
+		mutex_unlock(&pmx->mutex);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(pinmux_config);
+
+int pinmux_check_ops(const struct pinmux_ops *ops)
+{
+	/* Check that we implement required operations */
+	if (!ops->list_functions ||
+	    !ops->get_function_name ||
+	    !ops->enable ||
+	    !ops->disable)
+		return -EINVAL;
+
+	return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+/* Called from pincontrol core */
+static int pinmux_functions_show(struct seq_file *s, void *what)
+{
+	struct pinctrl_dev *pctldev = s->private;
+	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+	unsigned selector = 0;
+
+	while (ops->list_functions(pctldev, selector) >= 0) {
+		unsigned *pins;
+		unsigned num_pins;
+		const char *func = ops->get_function_name(pctldev, selector);
+		unsigned position = 0;
+		int ret;
+		int i;
+
+		while (ops->list_positions(pctldev, selector, position) >= 0) {
+			ret = ops->get_function_pins(pctldev, selector,
+						     position,
+						     &pins, &num_pins);
+
+			if (ret)
+				seq_printf(s, "%s [ERROR GETTING PINS]\n",
+					   func);
+
+			else {
+				seq_printf(s, "function: %s, position: %d pins = [ ",
+					   func, position);
+				for (i = 0; i < num_pins; i++)
+					seq_printf(s, "%d ", pins[i]);
+				seq_puts(s, "]\n");
+			}
+			position++;
+		}
+
+		selector++;
+
+	}
+
+	return 0;
+}
+
+static int pinmux_show(struct seq_file *s, void *what)
+{
+	struct pinmux *pmx;
+	const struct pinmux_map *map;
+
+	seq_puts(s, "System pinmuxes and their maps:\n");
+	list_for_each_entry(pmx, &pinmux_list, node) {
+		map = pmx->map;
+
+		seq_printf(s, "device: %s function: %s (%u), "
+			   "pos %u users: %u map-> %s\n",
+			   pmx->pctldev ? pctldev_get_name(pmx->pctldev) : "(no controller)",
+			   map->function,
+			   pmx->pmxdev_selector,
+			   map->position,
+			   pmx->usecount,
+			   pmx->dev ? dev_name(pmx->dev) : "(no device)");
+	}
+
+	return 0;
+}
+
+static int pinmux_pins_show(struct seq_file *s, void *what)
+{
+	struct pinctrl_dev *pctldev = s->private;
+	unsigned pin;
+
+	if (pctldev == NULL) {
+		seq_puts(s, "device is gone\n");
+		return 0;
+	}
+
+	if (pctldev->desc == NULL) {
+		seq_puts(s, "device is lacking descriptor\n");
+		return 0;
+	}
+
+	seq_puts(s, "Pinmux settings per pin\n");
+	seq_puts(s, "Format: pin (name): pinmuxfunction [driver specifics]\n");
+
+	/* The highest pin number need to be included in the loop, thus <= */
+	for (pin = 0; pin <= pctldev->desc->maxpin; pin++) {
+
+		struct pin_desc *desc;
+
+		desc = pin_desc_get(pctldev, pin);
+		/* Pin space may be sparse */
+		if (desc == NULL)
+			continue;
+
+		else {
+			seq_printf(s, "pin %d (%s): %s", pin,
+				   desc->name ? desc->name : "unnamed",
+				   desc->mux_requested ? desc->mux_function : "UNCLAIMED");
+
+			if (pctldev->desc->pmxops->dbg_show)
+				pctldev->desc->pmxops->dbg_show(pctldev, s, pin);
+		}
+		seq_puts(s, "\n");
+	}
+
+	return 0;
+}
+
+static int pinmux_functions_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, pinmux_functions_show, inode->i_private);
+}
+
+static int pinmux_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, pinmux_show, NULL);
+}
+
+static int pinmux_pins_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, pinmux_pins_show, inode->i_private);
+}
+
+static const struct file_operations pinmux_functions_ops = {
+	.open		= pinmux_functions_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static const struct file_operations pinmux_ops = {
+	.open		= pinmux_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static const struct file_operations pinmux_pins_ops = {
+	.open		= pinmux_pins_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+void pinmux_init_device_debugfs(struct dentry *devroot,
+			 struct pinctrl_dev *pctldev)
+{
+	debugfs_create_file("pinmux-functions", S_IFREG | S_IRUGO,
+			    devroot, pctldev, &pinmux_functions_ops);
+	debugfs_create_file("pinmux-pins", S_IFREG | S_IRUGO,
+			    devroot, pctldev, &pinmux_pins_ops);
+}
+
+void pinmux_init_debugfs(struct dentry *subsys_root)
+{
+	debugfs_create_file("pinmuxes", S_IFREG | S_IRUGO,
+			    subsys_root, NULL, &pinmux_ops);
+}
+
+#endif /* CONFIG_DEBUG_FS */
diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h
new file mode 100644
index 0000000..ab672ef
--- /dev/null
+++ b/drivers/pinctrl/pinmux.h
@@ -0,0 +1,4 @@
+int pinmux_check_ops(const struct pinmux_ops *ops);
+void pinmux_init_device_debugfs(struct dentry *devroot,
+				struct pinctrl_dev *pctldev);
+void pinmux_init_debugfs(struct dentry *subsys_root);
diff --git a/include/linux/pinctrl/machine.h b/include/linux/pinctrl/machine.h
new file mode 100644
index 0000000..6da2471
--- /dev/null
+++ b/include/linux/pinctrl/machine.h
@@ -0,0 +1,74 @@
+/*
+ * Machine interface for the pinctrl subsystem.
+ *
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ * Based on bits of regulator core, gpio core and clk core
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef __LINUX_PINMUX_MACHINE_H
+#define __LINUX_PINMUX_MACHINE_H
+
+/**
+ * struct pinmux_map - boards/machines shall provide this map for devices
+ * @name: the name of this specific map entry for the particular machine.
+ *	This is the second parameter passed to pinmux_get() when you want
+ *	to have several mappings to the same device
+ * @ctrl_dev: the pin control device to be used by this mapping, may be NULL
+ *	if you provide .ctrl_dev_name instead (this is more common)
+ * @ctrl_dev_name: the name of the device controlling this specific mapping,
+ *	the name must be the same as in your struct device*
+ * @function: a function in the driver to use for this mapping, the driver
+ *	will lookup the function referenced by this ID on the specified
+ *	pin control device
+ * @position: sometimes a function has several possible positions in the
+ *	pin space, so this parameter accepts a certain position enumerator.
+ *	If for example a certain port can be mapped in three different
+ *	locations this could be 0, 1 or 2
+ * @dev: the device using this specific mapping, may be NULL if you provide
+ *	.dev_name instead (this is more common)
+ * @dev_name: the name of the device using this specific mapping, the name
+ *	must be the same as in your struct device*
+ */
+struct pinmux_map {
+	const char *name;
+	struct device *ctrl_dev;
+	const char *ctrl_dev_name;
+	const char *function;
+	unsigned position;
+	struct device *dev;
+	const char *dev_name;
+};
+
+/*
+ * Convenience macro to set a simple map from a certain pin controller and a
+ * certain function to a named device
+ */
+#define PINMUX_MAP(a, b, c) \
+	{ .ctrl_dev_name = a, .function = b, .dev_name = c }
+/*
+ * Convenience macro to map a function onto the primary device pinctrl device
+ * this is especially helpful on systems that have only one pin controller
+ * or need to set up a lot of mappings on the primary controller.
+ */
+#define PINMUX_MAP_PRIMARY(a, b) \
+	{ .ctrl_dev_name = "pinctrl.0", .function = a, .dev_name = b }
+
+#ifdef CONFIG_PINMUX
+
+extern int pinmux_register_mappings(struct pinmux_map const *map,
+				unsigned num_maps);
+
+#else
+
+static inline int pinmux_register_mappings(struct pinmux_map const *map,
+					   unsigned num_maps)
+{
+	return 0;
+}
+
+#endif /* !CONFIG_PINCTRL */
+#endif
diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h
new file mode 100644
index 0000000..0294e39
--- /dev/null
+++ b/include/linux/pinctrl/pinctrl.h
@@ -0,0 +1,143 @@
+/*
+ * Interface the pinctrl subsystem
+ *
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ * This interface is used in the core to keep track of pins.
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef __LINUX_PINCTRL_PINCTRL_H
+#define __LINUX_PINCTRL_PINCTRL_H
+
+#ifdef CONFIG_PINCTRL
+
+#include <linux/radix-tree.h>
+#include <linux/spinlock.h>
+#include <linux/list.h>
+
+struct pinmux_ops;
+struct gpio_chip;
+
+/**
+ * struct pinctrl_pin_desc - boards/machines provide information on their
+ * pins, pads or other muxable units in this struct
+ * @number: unique pin number from the global pin number space
+ * @name: a name for this pin
+ */
+struct pinctrl_pin_desc {
+	unsigned number;
+	const char *name;
+};
+
+/* Convenience macro to define a single named or anonymous pin descriptor */
+#define PINCTRL_PIN(a, b) { .number = a, .name = b }
+#define PINCTRL_PIN_ANON(a) { .number = a }
+
+/**
+ * struct pinctrl_gpio_range - each pin controller can provide subranges of
+ * the GPIO number space to be handled by the controller
+ * @name: a name for the chip in this range
+ * @id: an ID number for the chip in this range
+ * @base: base offset of the GPIO range
+ * @npins: number of pins in the GPIO range, including the base number
+ * @gc: an optional pointer to a gpio_chip
+ * @node: list node for internal use
+ */
+struct pinctrl_gpio_range {
+	const char name[16];
+	unsigned int id;
+	unsigned int base;
+	unsigned int npins;
+	struct gpio_chip *gc;
+	struct list_head node;
+};
+
+/**
+ * struct pinctrl_desc - pin controller descriptor, register this to pin
+ * control subsystem
+ * @name: name for the pin controller
+ * @pins: an array of pin descriptors describing all the pins handled by
+ *	this pin controller
+ * @npins: number of descriptors in the array, usually just ARRAY_SIZE()
+ *	of the pins field above
+ * @maxpin: since pin spaces may be sparse, there can he "holes" in the
+ *	pin range, this attribute gives the maximum pin number in the
+ *	total range. This should not be lower than npins for example,
+ *	but may be equal to npins if you have no holes in the pin range.
+ * @pmxops: pinmux operation vtable, if you support pinmuxing in your driver
+ * @owner: module providing the pin controller, used for refcounting
+ */
+struct pinctrl_desc {
+	const char *name;
+	struct pinctrl_pin_desc const *pins;
+	unsigned int npins;
+	unsigned int maxpin;
+	struct pinmux_ops *pmxops;
+	struct module *owner;
+};
+
+/**
+ * struct pinctrl_dev - pin control class device
+ * @desc: the pin controller descriptor supplied when initializing this pin
+ *	controller
+ * @pin_desc_tree: each pin descriptor for this pin controller is stored in
+ *	this radix tree
+ * @pin_desc_tree_lock: lock for the descriptor tree
+ * @gpio_ranges: a list of GPIO ranges that is handled by this pin controller,
+ *	ranges are added to this list at runtime
+ * @gpio_ranges_lock: lock for the GPIO ranges list
+ * @dev: the device entry for this pin controller
+ * @owner: module providing the pin controller, used for refcounting
+ * @driver_data: driver data for drivers registering to the pin controller
+ *	subsystem
+ * @node: node to include this pin controller in the global pin controller list
+ *
+ * This should be dereferenced and used by the pin controller core ONLY
+ */
+struct pinctrl_dev {
+	struct pinctrl_desc *desc;
+	struct radix_tree_root pin_desc_tree;
+	spinlock_t pin_desc_tree_lock;
+	struct list_head gpio_ranges;
+	spinlock_t gpio_ranges_lock;
+	struct device dev;
+	struct module *owner;
+	void *driver_data;
+	struct list_head node;
+};
+
+/* These should only be used from drivers */
+static inline const char *pctldev_get_name(struct pinctrl_dev *pctldev)
+{
+	/* We're not allowed to register devices without name */
+	return pctldev->desc->name;
+}
+
+static inline void *pctldev_get_drvdata(struct pinctrl_dev *pctldev)
+{
+	return pctldev->driver_data;
+}
+
+/* External interface to pin controller */
+extern struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
+				struct device *dev, void *driver_data);
+extern void pinctrl_unregister(struct pinctrl_dev *pctldev);
+extern bool pin_is_valid(struct pinctrl_dev *pctldev, int pin);
+extern void pinctrl_add_gpio_range(struct pinctrl_dev *pctldev,
+				   struct pinctrl_gpio_range *range);
+#else
+
+struct pinctrl_dev;
+
+/* Sufficiently stupid default function when pinctrl is not in use */
+static inline bool pin_is_valid(struct pinctrl_dev *pctldev, int pin)
+{
+	return pin >= 0;
+}
+
+#endif /* !CONFIG_PINCTRL */
+
+#endif /* __LINUX_PINCTRL_PINCTRL_H */
diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h
new file mode 100644
index 0000000..2583cc7
--- /dev/null
+++ b/include/linux/pinctrl/pinmux.h
@@ -0,0 +1,135 @@
+/*
+ * Interface the pinmux subsystem
+ *
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ * Based on bits of regulator core, gpio core and clk core
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef __LINUX_PINCTRL_PINMUX_H
+#define __LINUX_PINCTRL_PINMUX_H
+
+#include <linux/list.h>
+#include <linux/seq_file.h>
+#include "pinctrl.h"
+
+/* This struct is private to the core and should be regarded as a cookie */
+struct pinmux;
+
+#ifdef CONFIG_PINMUX
+
+struct pinctrl_dev;
+
+/**
+ * struct pinmux_ops - pinmux operations, to be implemented by pin controller
+ * drivers that support pinmuxing
+ * @request: called by the core to see if a certain pin can be made available
+ *	available for muxing. This is called by the core to acquire the pins
+ *	before selecting any actual mux setting across a function. The driver
+ *	is allowed to answer "no" by returning a negative error code
+ * @free: the reverse function of the request() callback, frees a pin after
+ *	being requested
+ * @list_functions: list the number of selectable named functions available
+ *	in this pinmux driver, the core will begin on 0 and call this
+ *	repeatedly as long as it returns >= 0 to enumerate mux settings
+ * @list_positions: list the number of selectable positions for a certain
+ *	function selector, the core will begin on 0 and call this repeatedly
+ *	as long as it returns >= 0 to enumerate positions
+ * @get_function_name: return the function name of the muxing selector,
+ *	called by the core to figure out which mux setting it shall map a
+ *	certain device to
+ * @get_function_pins: return an array of pins corresponding to a certain
+ *	function selector and position in @pins, and the size of the array
+ *	in @num_pins
+ * @enable: enable a certain muxing function on a certain position. The driver
+ *	does not need to figure out whether enabling this function conflicts
+ *	some other use of the pins, such collisions are handled by the pinmux
+ *	subsystem
+ * @disable: disable a certain muxing selector on a certain position.
+ * @config: custom configuration function for a certain muxing selector -
+ *	this works a bit like an ioctl() and can pass in and return arbitrary
+ *	configuration data to the pinmux. Currently we do not pass in the
+ *	position to this call, refactor if need be
+ * @gpio_request_enable: requests and enables GPIO on a certain pin.
+ *	Implement this only if you can mux every pin individually as GPIO. The
+ *	affected GPIO range is passed along with an offset into that
+ *	specific GPIO range - function selectors and positions are orthogonal
+ *	to this, the core will however make sure the pins do not collide
+ * @dbg_show: optional debugfs display hook that will provide per-device
+ *	info for a certain pin in debugfs
+ */
+struct pinmux_ops {
+	int (*request) (struct pinctrl_dev *pctldev, unsigned offset);
+	int (*free) (struct pinctrl_dev *pctldev, unsigned offset);
+	int (*list_functions) (struct pinctrl_dev *pctldev, unsigned selector);
+	int (*list_positions) (struct pinctrl_dev *pctldev, unsigned selector,
+			       unsigned position);
+	const char *(*get_function_name) (struct pinctrl_dev *pctldev,
+					  unsigned selector);
+	int (*get_function_pins) (struct pinctrl_dev *pctldev,
+				  unsigned selector, unsigned position,
+				  unsigned ** const pins,
+				  unsigned * const num_pins);
+	int (*enable) (struct pinctrl_dev *pctldev, unsigned selector,
+		       unsigned position);
+	void (*disable) (struct pinctrl_dev *pctldev, unsigned selector,
+			 unsigned position);
+	int (*config) (struct pinctrl_dev *pctldev, unsigned selector,
+		       u16 param, unsigned long *data);
+	int (*gpio_request_enable) (struct pinctrl_dev *pctldev,
+				    struct pinctrl_gpio_range *range,
+				    unsigned offset);
+	void (*dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s,
+			  unsigned offset);
+};
+
+/* External interface to pinmux */
+extern int pinmux_request_gpio(unsigned gpio);
+extern void pinmux_free_gpio(unsigned gpio);
+extern struct pinmux *pinmux_get(struct device *dev, const char *name);
+extern void pinmux_put(struct pinmux *pmx);
+extern int pinmux_enable(struct pinmux *pmx);
+extern void pinmux_disable(struct pinmux *pmx);
+extern int pinmux_config(struct pinmux *pmx, u16 param, unsigned long *data);
+
+#else /* !CONFIG_PINMUX */
+
+static inline int pinmux_request_gpio(unsigned gpio)
+{
+	return 0;
+}
+
+static inline void pinmux_free_gpio(unsigned gpio)
+{
+}
+
+static inline struct pinmux *pinmux_get(struct device *dev, const char *name)
+{
+	return NULL;
+}
+
+static inline void pinmux_put(struct pinmux *pmx)
+{
+}
+
+static inline int pinmux_enable(struct pinmux *pmx)
+{
+	return 0;
+}
+
+static inline void pinmux_disable(struct pinmux *pmx)
+{
+}
+
+static inline int pinmux_config(struct pinmux *pmx, u16 param,
+				unsigned long *data)
+{
+	return 0;
+}
+
+#endif /* CONFIG_PINMUX */
+
+#endif /* __LINUX_PINCTRL_PINMUX_H */
-- 
1.7.3.2


^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [PATCH 1/4 v5] drivers: create a pin control subsystem v5
@ 2011-08-29  9:10 ` Linus Walleij
  0 siblings, 0 replies; 16+ messages in thread
From: Linus Walleij @ 2011-08-29  9:10 UTC (permalink / raw)
  To: linux-arm-kernel

From: Linus Walleij <linus.walleij@linaro.org>

This creates a subsystem for handling of pin control devices.
These are devices that control different aspects of package
pins.

Currently it handled pinmuxing, i.e. assign electronic functions
to groups of pins of pins on primarily PGA and BGA type of chip
packages and common in embedded systems.

The plan is to also handle other I/O pin control aspects such as
biasing, driving, input properties such as schmitt-triggering,
load capacitance etc within this subsystem.

This is being done to depopulate the arch/arm/* directory of such
custom drivers and try to abstract the infrastructure they all
need. See the Documentation/pinmux.txt file that is part of this
patch for more details.

Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Joe Perches <joe@perches.com>
Cc: Russell King <linux@arm.linux.org.uk>
Tested-by: Barry Song <21cnbao@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v4->v5:

- Defined a "position" for each function, so the pin controller now
  tracks a function in a certain position, and the pinmux maps define
  what position you want the function in. (Feedback from Stephen
  Warren and Sascha Hauer).

- Since we now need to request a combined function+position from
  the machine mapping table that connect mux settings to drivers,
  it was extended with a position field and a name field. The
  name field is now used if you e.g. need to switch between two
  mux map settings at runtime.

- Switched from a class device to using struct bus_type for this
  subsystem. Verified sysfs functionality: seems to work fine.
  (Feedback from Arnd Bergmann and Greg Kroah-Hartman)

- Define a per pincontroller list of GPIO ranges from the GPIO
  pin space that can be handled by the pin controller. These can
  be added one by one at runtime. (Feedback from Barry Song)

- Expanded documentation of regulator_[get|enable|disable|put]
  semantics.

- Fixed a number of review comments from Barry Song. (Thanks!)
---
 Documentation/ABI/testing/sysfs-class-pinmux |   11 +
 Documentation/pinctrl.txt                    |  714 +++++++++++++++++++++++
 MAINTAINERS                                  |    5 +
 drivers/Kconfig                              |    4 +
 drivers/Makefile                             |    2 +
 drivers/pinctrl/Kconfig                      |   29 +
 drivers/pinctrl/Makefile                     |    6 +
 drivers/pinctrl/core.c                       |  539 +++++++++++++++++
 drivers/pinctrl/core.h                       |   24 +
 drivers/pinctrl/pinmux.c                     |  811 ++++++++++++++++++++++++++
 drivers/pinctrl/pinmux.h                     |    4 +
 include/linux/pinctrl/machine.h              |   74 +++
 include/linux/pinctrl/pinctrl.h              |  143 +++++
 include/linux/pinctrl/pinmux.h               |  135 +++++
 14 files changed, 2501 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/ABI/testing/sysfs-class-pinmux
 create mode 100644 Documentation/pinctrl.txt
 create mode 100644 drivers/pinctrl/Kconfig
 create mode 100644 drivers/pinctrl/Makefile
 create mode 100644 drivers/pinctrl/core.c
 create mode 100644 drivers/pinctrl/core.h
 create mode 100644 drivers/pinctrl/pinmux.c
 create mode 100644 drivers/pinctrl/pinmux.h
 create mode 100644 include/linux/pinctrl/machine.h
 create mode 100644 include/linux/pinctrl/pinctrl.h
 create mode 100644 include/linux/pinctrl/pinmux.h

diff --git a/Documentation/ABI/testing/sysfs-class-pinmux b/Documentation/ABI/testing/sysfs-class-pinmux
new file mode 100644
index 0000000..c2ea843
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-class-pinmux
@@ -0,0 +1,11 @@
+What:		/sys/class/pinmux/.../name
+Date:		May 2011
+KernelVersion:	3.1
+Contact:	Linus Walleij <linus.walleij@linaro.org>
+Description:
+		Each pinmux directory will contain a field called
+		name. This holds a string identifying the pinmux for
+		display purposes.
+
+		NOTE: this will be empty if no suitable name is provided
+		by platform or pinmux drivers.
diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
new file mode 100644
index 0000000..76c003a
--- /dev/null
+++ b/Documentation/pinctrl.txt
@@ -0,0 +1,714 @@
+PINCTRL (PIN CONTROL) subsystem
+This document outlines the pin control subsystem in Linux
+
+This subsystem deals with:
+
+- Enumerating and naming controllable pins
+
+- Multiplexing of pins, pads, fingers (etc) see below for details
+
+The intention is to also deal with:
+
+- Software-controlled biasing and driving mode specific pins, such as
+  pull-up/down, open drain etc, load capacitance configuration when controlled
+  by software, etc.
+
+
+Top-level interface
+===================
+
+Definition of PIN CONTROLLER:
+
+- A pin controller is a piece of hardware, usually a set of registers, that
+  can control PINs. It may be able to multiplex, bias, set load capacitance,
+  set drive strength etc for individual pins or groups of pins.
+
+Definition of PIN:
+
+- PINS are equal to pads, fingers, balls or whatever packaging input or
+  output line you want to control and these are denoted by unsigned integers
+  in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
+  there may be several such number spaces in a system. This pin space may
+  be sparse - i.e. there may be gaps in the space with numbers where no
+  pin exists.
+
+When a PIN CONTROLLER is instatiated, it will register a descriptor to the
+pin control framework, and this descriptor contains an array of pin descriptors
+describing the pins handled by this specific pin controller.
+
+Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
+
+        A   B   C   D   E   F   G   H
+
+   8    o   o   o   o   o   o   o   o
+
+   7    o   o   o   o   o   o   o   o
+
+   6    o   o   o   o   o   o   o   o
+
+   5    o   o   o   o   o   o   o   o
+
+   4    o   o   o   o   o   o   o   o
+
+   3    o   o   o   o   o   o   o   o
+
+   2    o   o   o   o   o   o   o   o
+
+   1    o   o   o   o   o   o   o   o
+
+To register a pin controller and name all the pins on this package we can do
+this in our driver:
+
+#include <linux/pinctrl/pinctrl.h>
+
+const struct pinctrl_pin_desc __refdata foo_pins[] = {
+      PINCTRL_PIN(0, "A1"),
+      PINCTRL_PIN(1, "A2"),
+      PINCTRL_PIN(2, "A3"),
+      ...
+      PINCTRL_PIN(61, "H6"),
+      PINCTRL_PIN(62, "H7"),
+      PINCTRL_PIN(63, "H8"),
+};
+
+static struct pinctrl_desc foo_desc = {
+	.name = "foo",
+	.pins = foo_pins,
+	.npins = ARRAY_SIZE(foo_pins),
+	.maxpin = 63,
+	.owner = THIS_MODULE,
+};
+
+int __init foo_probe(void)
+{
+	struct pinctrl_dev *pctl;
+
+	pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
+	if (IS_ERR(pctl))
+		pr_err("could not register foo pin driver\n");
+}
+
+Pins usually have fancier names than this. You can find these in the dataheet
+for your chip. Notice that the core pinctrl.h file provides a fancy macro
+called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
+the pins from 0 in the upper left corner to 63 in the lower right corner,
+this enumeration was arbitrarily chosen, in practice you need to think
+through your numbering system so that it matches the layout of registers
+and such things in your driver, or the code may become complicated. You must
+also consider matching of offsets to the GPIO ranges that may be handled by
+the pin controller.
+
+For a padring with 467 pads, as opposed to actual pins, I used an enumeration
+like this, walking around the edge of the chip, which seems to be industry
+standard too (all these pads had names, too):
+
+
+     0 ..... 104
+   466        105
+     .        .
+     .        .
+   358        224
+    357 .... 225
+
+
+Interaction with the GPIO subsystem
+===================================
+
+The GPIO drivers may want to perform operations of various types on the same
+physical pins that are also registered as GPIO pins.
+
+Since the pin controller subsystem have its pinspace local to the pin
+controller we need a mapping so that the pin control subsystem can figure out
+which pin controller handles control of a certain GPIO pin. Since a single
+pin controller may be muxing several GPIO ranges (typically SoCs that have
+one set of pins but internally several GPIO silicon blocks, each modeled as
+a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
+instance like this:
+
+struct gpio_chip chip_a;
+struct gpio_chip chip_b;
+
+static struct pinctrl_gpio_range gpio_range_a = {
+	.name = "chip a",
+	.id = 0,
+	.base = 32,
+	.npins = 16,
+	.gc = &chip_a;
+};
+
+static struct pinctrl_gpio_range gpio_range_a = {
+	.name = "chip b",
+	.id = 0,
+	.base = 48,
+	.npins = 8,
+	.gc = &chip_b;
+};
+
+
+{
+	struct pinctrl_dev *pctl;
+	...
+	pinctrl_add_gpio_range(pctl, &gpio_range_a);
+	pinctrl_add_gpio_range(pctl, &gpio_range_b);
+}
+
+So this complex system has one pin controller handling two different
+GPIO chips. Chip a has 16 pins and chip b has 8 pins. They are mapped in
+the global GPIO pin space at:
+
+chip a: [32 .. 47]
+chip b: [48 .. 55]
+
+When GPIO-specific functions in the pin control subsystem are called, these
+ranges will be used to look up the apropriate pin controller by inspecting
+and matching the pin to the pin ranges across all controllers. When a
+pin controller handling the matching range is found, GPIO-specific functions
+will be called on that specific pin controller.
+
+For all functionalities dealing with pin biasing, pin muxing etc, the pin
+controller subsystem will subtract the range's .base offset from the passed
+in gpio pin number, and pass that on to the pin control driver, so the driver
+will get an offset into its handled number range. Further it is also passed
+the range ID value, so that the pin controller knows which range it should
+deal with.
+
+For example: if a user issues pinctrl_gpio_set_foo(50), the pin control
+subsystem will find that the second range on this pin controller matches,
+subtract the base 48 and call the
+pinctrl_driver_gpio_set_foo(pinctrl, range, 2) where the latter function has
+this signature:
+
+int pinctrl_driver_gpio_set_foo(struct pinctrl_dev *pctldev,
+    struct pinctrl_gpio_range *rangeid,
+    unsigned offset);
+
+Now the driver knows that we want to do some GPIO-specific operation on the
+second GPIO range handled by "chip b", at offset 2 in that specific range.
+
+(If the GPIO subsystem is ever refactored to use a local per-GPIO controller
+pin space, this mapping will need to be augmented accordingly.)
+
+
+PINMUX interfaces
+=================
+
+These calls use the pinmux_* naming prefix.  No other calls should use that
+prefix.
+
+
+What is pinmuxing?
+==================
+
+PINMUX, also known as padmux, ballmux, alternate functions or mission modes
+is a way for chip vendors producing some kind of electrical packages to use
+a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
+functions, depending on the application. By "application" in this context
+we usually mean a way of soldering or wiring the package into an electronic
+system, even though the framework makes it possible to also change the function
+at runtime.
+
+Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
+
+        A   B   C   D   E   F   G   H
+      +---+
+   8  | o | o   o   o   o   o   o   o
+      |   |
+   7  | o | o   o   o   o   o   o   o
+      |   |
+   6  | o | o   o   o   o   o   o   o
+      +---+---+
+   5  | o | o | o   o   o   o   o   o
+      +---+---+               +---+
+   4    o   o   o   o   o   o | o | o
+                              |   |
+   3    o   o   o   o   o   o | o | o
+                              |   |
+   2    o   o   o   o   o   o | o | o
+      +-------+-------+-------+---+---+
+   1  | o   o | o   o | o   o | o | o |
+      +-------+-------+-------+---+---+
+
+This is not tetris. The game to think of is chess. Not all PGA/BGA packages
+are chessboard-like, big ones have "holes" in some arrangement according to
+different design patterns, but we're using this as a simple example. Of the
+pins you see some will be taken by things like a few VCC and GND to feed power
+to the chip, and quite a few will be taken by large ports like an external
+memory interface. The remaining pins will often be subject to pin multiplexing.
+
+The example 8x8 PGA package above will have pin numbers 0 thru 63 assigned to
+its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
+pinctrl_register_pins_[sparse|dense]() and a suitable data set as shown
+earlier.
+
+In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
+(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
+some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
+be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
+we cannot use the SPI port and I2C port at the same time. However in the inside
+of the package the silicon performing the SPI logic can alternatively be routed
+out on pins { G4, G3, G2, G1 }.
+
+On the botton row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
+special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
+consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
+{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
+port on pins { G4, G3, G2, G1 } of course.
+
+This way the silicon blocks present inside the chip can be multiplexed "muxed"
+out on different pin ranges. Often contemporary SoC (systems on chip) will
+contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
+different pins by pinmux settings.
+
+Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
+common to be able to use almost any pin as a GPIO pin if it is not currently
+in use by some other I/O port.
+
+
+Pinmux conventions
+==================
+
+The purpose of the pinmux functionality in the pin controller subsystem is to
+abstract and provide pinmux settings to the devices you choose to instantiate
+in your machine configuration. It is inspired by the clk, GPIO and regulator
+subsystems, so devices will request their mux setting, but it's also possible
+to request a single pin for e.g. GPIO.
+
+Definitions:
+
+- FUNCTIONS can be switched in and out by a driver residing with the pin
+  control subsystem in the drivers/pinctrl/* directory of the kernel. The
+  pin control driver knows the possible functions. In the example above you can
+  identify three pinmux functions, two for spi and one for i2c.
+
+- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
+  In this case the array could be something like: { spi0, i2c0, mmc0 }
+  for the three available functions.
+
+- POSITIONS are applicable to each function, so if spi0 can appear on three
+  different sets of pins, say {0, 1}, {4, 5} and {12, 13} these three
+  positions are numbered 0, 1, 2.
+
+- FUNCTIONS + POSITION determine a certain function for a certain set of pins.
+  The knowledge of the functions and positions and it's machine-specific
+  particulars is kept inside the pinmux driver, from the outside only the
+  enumerators are known, and the driver core can request the name of a function
+  with a certain selector (>= 0) or the list of pins belonging to a certain
+  function selector + position.
+
+- FUNCTIONS with POSITIONs on a certain PIN CONTROLLER are MAPPED to a certain
+  device by the board file, device tree or similar machine setup configuration
+  mechanism, similar to how regulators are connected to devices, usually by
+  name. Defining a pin controller, function and position thus uniquely identify
+  the set of pins to be used by a certain device.
+
+  In the example case we can define that this particular machine shall
+  use device spi0 with pinmux function fspi0 position 0 and i2c0 on function
+  fi2c0  position 1, on the primary pin controller, we get quadruple mappings
+  like these:
+  { {spi0, pinctrl0, fspi0, 0}, {i2c0, pinctrl0, fi2c0, 1} }
+
+- FUNCTIONS on a certain POSITION on a certain PIN CONTROLLER are provided
+  on a first-come first-serve basis, so if some other device mux setting or
+  GPIO pin request has already taken your physical pin, you will be denied the
+  use of it. To get (activate) a new setting, the old one has to be put
+  (deactivated) first.
+
+Sometimes the documentation and hardware registers will be oriented around
+pads (or "fingers") rather than pins - these are the soldering surfaces on the
+silicon inside the package, and may or may not match the actual number of
+pins/balls underneath the capsule. Pick some enumeration that makes sense to
+you. Define enumerators only for the pins you can control if that makes sense.
+
+Assumptions:
+
+We assume that the number possible function maps to pins is limited by the
+hardware. I.e. we assume that there is no system where any function can be
+mapped to any pin, like in a phone exchange. So the available pins groups for
+a certain function will be limited to a few choices (say up to eight or so),
+not hundreds or any amount of choices. This is the characteristic we have found
+by inspecting available pinmux hardware.
+
+
+Pinmux drivers
+==============
+
+It is the responsibility of the pinmux driver to determine whether or not
+the requested function can actually be enabled, and in that case poke the
+hardware so that this happens.
+
+The driver will for all calls be provided an offset pin number into its own
+pin range. If you have 2 chips with 8x8 pins, the first chips pins will have
+numbers 0 thru 63 and the second one pins 64 thru 127, but the driver for the
+second chip will be passed numbers in the range 0 thru 63 anyway, base offset
+subtracted.
+
+Pinmux drivers are required to supply a few callback functions, some are
+optional. Usually the enable() and disable() functions are implemented,
+writing values into some certain registers to activate a certain mux setting
+for a certain pin.
+
+A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
+into some register named MUX to select a certain function on a certain position
+would works something like this:
+
+#include <linux/pinctrl/pinmux.h>
+
+struct foo_pmx_position {
+	unsigned pos;
+	const unsigned int *pins;
+	const unsigned num_pins;
+	u8 regbit;
+}
+
+struct foo_pmx_func {
+	char *name;
+	struct positions*;
+	unsigned num_positions;
+};
+
+static unsigned int spi0_0_pins[] = { 0, 8, 16, 24 };
+static unsigned int spi0_1_pins[] = { 38, 46, 54, 62 };
+
+static struct foo_pmx_position spi0_positions[] = {
+       {
+		.pos = 0,
+		.pins = spi0_0_pins,
+		.num_pins = ARRAY_SIZE(spi0_1_pins),
+		.regbit = 0x01,
+       },
+       {
+		.pos = 1,
+		.pins = spi0_1_pins,
+		.num_pins = ARRAY_SIZE(spi0_1_pins),
+		.regbit = 0x02,
+       },
+};
+
+static unsigned int i2c0_pins[] = { 24, 25 };
+
+static struct foo_pmx_position i2c0_positions[] = {
+       {
+		.pos = 0,
+		.pins = i2c0_pins,
+		.num_pins = ARRAY_SIZE(spi0_1_pins),
+		.regbit = 0x04,
+       },
+};
+
+static unsigned int mmc0_1_pins[] = { 56, 57 };
+static unsigned int mmc0_2_pins[] = { 56, 57, 58, 59 };
+static unsigned int mmc0_3_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63 };
+
+static struct foo_pmx_position mmc0_positions[] = {
+       {
+		.pos = 0,
+		.pins = mmc0_1_pins,
+		.num_pins = ARRAY_SIZE(mmc0_1_pins),
+		.regbit = 0x08,
+       },
+       {
+		.pos = 1,
+		.pins = mmc0_2_pins,
+		.num_pins = ARRAY_SIZE(mmc0_2_pins),
+		.regbit = 0x10,
+       },
+       {
+		.pos = 2,
+		.pins = mmc0_3_pins,
+		.num_pins = ARRAY_SIZE(mmc0_3_pins),
+		.regbit = 0x20,
+       },
+};
+
+static struct foo_pmx_func myfuncs[] = {
+	{
+		.name = "spi0",
+		.positions = spi0_positions,
+		.num_positions = ARRAY_SIZE(spi0_positions),
+	},
+	{
+		.name = "i2c0",
+		.positions = i2c0_positions,
+		.num_positions = ARRAY_SIZE(i2c0_positions),
+	},
+	{
+		.name = "mmc0",
+		.positions = mmc0_positions,
+		.num_positions = ARRAY_SIZE(mmc0_positions),
+	},
+};
+
+int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
+{
+	if (selector >= ARRAY_SIZE(myfuncs))
+		return -EINVAL;
+	return 0;
+}
+
+int foo_list_positions(struct pinctrl_dev *pctldev, unsigned selector,
+    			unsigned position)
+{
+	if (selector >= ARRAY_SIZE(myfuncs))
+		return -EINVAL;
+	if (position >= myfuncs[selector].num_positions)
+		return -EINVAL;
+	return 0;
+}
+
+const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
+{
+	return myfuncs[selector].name;
+}
+
+static int foo_get_pins(struct pinctrl_dev *pctldev, unsigned selector,
+       	   		unsigned position, unsigned ** const pins,
+			unsigned * const num_pins)
+{
+	*pins = myfuncs[selector].positions[position].pins;
+	*num_pins = myfuncs[selector].positions[position].num_pins;
+	return 0;
+}
+
+int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
+    		unsigned position)
+{
+	u8 regbit = myfuncs[selector].positions[position].regbit;
+
+	writeb((readb(MUX)|regbit), MUX)
+	return 0;
+}
+
+int foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
+    		unsigned position)
+{
+	u8 regbit = myfuncs[selector].positions[position].regbit;
+
+	writeb((readb(MUX) & ~(regbit)), MUX)
+	return 0;
+}
+
+struct pinmux_ops pmxops = {
+	.list_functions = foo_list_funcs,
+	.list_positions = foo_list_positions,
+	.get_function_name = foo_get_fname,
+	.get_function_pins = foo_get_pins,
+	.enable = foo_enable,
+	.disable = foo_disable,
+};
+
+/* Pinmux operations are handled by some pin controller */
+static struct pinctrl_desc foo_desc = {
+	...
+	.pmxops = pmxops,
+};
+
+Now the able reader will say: "wait - the driver needs to make sure it
+can set this and that bit at the same time, because else it will collide
+and wreak havoc in my electronics, and make sure noone else is using the
+other setting that it's incompatible with".
+
+In the example activating muxing 0 and 1 at the same time setting bits
+0 and 1, uses one pin in common so they would collide.
+
+The beauty of the pinmux subsystem is that since it keeps track of all
+pins and who is using them, it will already have denied an impossible
+request like that, so the driver does not need to worry about such
+things - when it gets a selector passed in, the pinmux subsystem makes
+sure no other device or GPIO assignment is already using the selected
+pins.
+
+The above functions except .list_positions are mandatory to implement for
+a pinmux driver. For hardware where each function can only exist in one
+position, you can omit this functions, and position 0 will be passed to all
+calls.
+
+
+Pinmux interaction with the GPIO subsystem
+==========================================
+
+The function list could become long, especially if you can convert every
+individual pin into a GPIO pin independent of any other pins, then your
+function array can become 64 entries for each GPIO setting and then the
+device functions. For this reason there is an additional function you
+can implement to enable only GPIO on an individual pin: pinmux_request_gpio()
+and pinmux_free_gpio().
+
+These functions use the .gpio_base and .gpio_pins members of the pin
+controller as described above for the pin controller, to look up the target
+pin controller.
+
+
+Pinmux board/machine configuration
+==================================
+
+Boards and machines define how a certain complete running system is put
+together, including how GPIOs and devices are muxed, how regulators are
+constrained and how the clock tree looks. Of course pinmux settings are also
+part of this.
+
+A pinmux config for a machine looks pretty much like a simple regulator
+configuration, so for the example array above we want to enable i2c and
+spi on the second function mapping:
+
+#include <linux/pinctrl/machine.h>
+
+static struct pinmux_map pmx_mapping[] = {
+	{
+		.ctrl_dev_name = "pinctrl.0",
+		.function = "spi0",
+		.position = 1,
+		.dev_name = "foo-spi.0",
+	},
+	{
+		.ctrl_dev_name = "pinctrl.0",
+		.function = "i2c0",
+		.position = 0,
+		.dev_name = "foo-i2c.0",
+	},
+	{
+		.ctrl_dev_name = "pinctrl.0",
+		.function = "mmc0",
+		.position = 1,
+		.dev_name = "foo-mmc.0",
+	},
+};
+
+As you can see we may have several pin controllers on the system and thus
+we need to specify which one of them that contain the functions we wish
+to map. The map can also use struct device * directly, so there is no
+inherent need to use strings to specify .dev_name or .ctrl_dev_name, these
+are for the situation where you do not have a handle to the struct device *,
+for example if they are not yet instantiated or cumbersome to obtain.
+
+Since the above construct is pretty common there is a helper macro to make
+it even more compact which assumes you want to use pinctrl.0 and position
+0 for mapping, for example:
+
+static struct pinmux_map pmx_mapping[] = {
+       PINMUX_MAP_PRIMARY("i2c0", "foo-i2c.0"),
+};
+
+The dev_name here matches to the unique device name that can be used to look
+up the device struct (just like with clockdev or regulators). The function name
+must match a function provided by the pinmux driver handling this pin range.
+You register this pinmux mapping to the pinmux subsystem by simply:
+
+       ret = pinmux_register_mappings(&pmx_mapping, ARRAY_SIZE(pmx_mapping));
+
+
+Pinmux requests from drivers
+============================
+
+A driver may request a certain mux to be activated, usually just the default
+mux like this:
+
+#include <linux/pinctrl/pinmux.h>
+
+struct foo_state {
+       struct pinmux *pmx;
+       ...
+};
+
+foo_probe()
+{
+	/* Allocate a state holder named "state" etc */
+	struct pinmux pmx;
+
+	pmx = pinmux_get(&device, NULL);
+	if IS_ERR(pmx)
+		return PTR_ERR(pmx);
+	pinmux_enable(pmx);
+
+	state->pmx = pmx;
+}
+
+foo_remove()
+{
+	pinmux_disable(state->pmx);
+	pinmux_put(state->pmx);
+}
+
+If you want to grab a specific mux mapping and not just the first one found for
+this device you can specify a specific mapping name, for example in the above
+example the second i2c0 setting: pinmux_get(&device, "spi0-pos-B");
+
+This get/enable/disable/put sequence can just as well be handled by bus drivers
+if you don't want each and every driver to handle it and you know the
+arrangement on your bus.
+
+The semantics of the get/enable respective disable/put is as follows:
+
+- pinmux_get() is called in process context to reserve the pins affected with
+  a certain mapping and set up the pinmux core and the driver. It will allocate
+  a struct from the kernel memory to hold the pinmux state.
+
+- pinmux_enable()/pinmux_disable() is quick and can be called from fastpath
+  (irq context) when you quickly want to set up/tear down the hardware muxing
+  when running a device driver. Usually it will just poke some values into a
+  register.
+
+- pinmux_disable() is called in process context to tear down the pin requests
+  and release the state holder struct for the mux setting.
+
+Usually the pinmux core handled the get/put pair and call out to the device
+drivers bookkeeping operations, like checking available functions and the
+associated pins, whereas the enable/disable pass on to the pin controller
+driver which takes care of activating and/or deactivating the mux setting by
+quickly poking some registers.
+
+The pins are allocated for your device when you issue the pinmux_get() call,
+after this you should be able to see this in the debugfs listing of all pins.
+
+
+Runtime pinmuxing
+=================
+
+It is possible to mux a certain function in and out at runtime, say to move
+an SPI port from one set of pins to another set of pins. Say for example for
+spi0 in the example above, we expose two different positions in the mapping
+to achieve this:
+
+static struct pinmux_map pmx_mapping[] = {
+	{
+		.name = "spi0-pos-A",
+		.ctrl_dev_name = "pinctrl.0",
+		.function = "spi0",
+		.position = 0,
+		.dev_name = "foo-spi.0",
+	},
+	{
+		.name = "spi0-pos-B",
+		.ctrl_dev_name = "pinctrl.0",
+		.function = "spi0",
+		.position = 1,
+		.dev_name = "foo-spi.0",
+	},
+	...
+};
+
+This snippet first muxes the function in position A, enables it, disables
+and releases it, and muxes it in on position B:
+
+foo_switch()
+{
+	struct pinmux pmx;
+
+	/* Enable on position A */
+	pmx = pinmux_get(&device, "spi0-pos-A");
+	if IS_ERR(pmx)
+		return PTR_ERR(pmx);
+	pinmux_enable(pmx);
+
+	/* This releases the pins again */
+	pinmux_disable(pmx);
+	pinmux_put(pmx);
+
+	/* Enable on position B */
+	pmx = pinmux_get(&device, "spi0-pos-B");
+	if IS_ERR(pmx)
+		return PTR_ERR(pmx);
+	pinmux_enable(pmx);
+	...
+}
+
+The above has to be done from process context.
diff --git a/MAINTAINERS b/MAINTAINERS
index 1d445f5..8c422d6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5001,6 +5001,11 @@ L:	linux-mtd at lists.infradead.org
 S:	Maintained
 F:	drivers/mtd/devices/phram.c
 
+PINMUX SUBSYSTEM
+M:	Linus Walleij <linus.walleij@linaro.org>
+S:	Maintained
+F:	drivers/pinmux/
+
 PKTCDVD DRIVER
 M:	Peter Osterlund <petero2@telia.com>
 S:	Maintained
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 95b9e7e..40d3e16 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -56,6 +56,10 @@ source "drivers/pps/Kconfig"
 
 source "drivers/ptp/Kconfig"
 
+# pinctrl before gpio - gpio drivers may need it
+
+source "drivers/pinctrl/Kconfig"
+
 source "drivers/gpio/Kconfig"
 
 source "drivers/w1/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 7fa433a..e7afb3a 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -5,6 +5,8 @@
 # Rewritten to use lists instead of if-statements.
 #
 
+# GPIO must come after pinctrl as gpios may need to mux pins etc
+obj-y				+= pinctrl/
 obj-y				+= gpio/
 obj-$(CONFIG_PCI)		+= pci/
 obj-$(CONFIG_PARISC)		+= parisc/
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
new file mode 100644
index 0000000..adb0be0
--- /dev/null
+++ b/drivers/pinctrl/Kconfig
@@ -0,0 +1,29 @@
+#
+# PINCTRL infrastructure and drivers
+#
+
+menuconfig PINCTRL
+	bool "PINCTRL Support"
+	depends on SYSFS && EXPERIMENTAL
+	help
+	  This enables the PINCTRL subsystem for controlling pins
+	  on chip packages, for example multiplexing pins on primarily
+	  PGA and BGA packages for systems on chip.
+
+	  If unsure, say N.
+
+if PINCTRL
+
+config PINMUX
+	bool "Support pinmux controllers"
+	help
+	  Say Y here if you want the pincontrol subsystem to handle pin
+	  multiplexing.
+
+config DEBUG_PINCTRL
+	bool "Debug PINCTRL calls"
+	depends on DEBUG_KERNEL
+	help
+	  Say Y here to add some extra checks and diagnostics to PINCTRL calls.
+
+endif
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
new file mode 100644
index 0000000..596ce9f
--- /dev/null
+++ b/drivers/pinctrl/Makefile
@@ -0,0 +1,6 @@
+# generic pinmux support
+
+ccflags-$(CONFIG_DEBUG_PINMUX)	+= -DDEBUG
+
+obj-$(CONFIG_PINCTRL)		+= core.o
+obj-$(CONFIG_PINMUX)		+= pinmux.o
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
new file mode 100644
index 0000000..762e9e8
--- /dev/null
+++ b/drivers/pinctrl/core.c
@@ -0,0 +1,539 @@
+/*
+ * Core driver for the pin control subsystem
+ *
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ * Based on bits of regulator core, gpio core and clk core
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#define pr_fmt(fmt) "pinctrl core: " fmt
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/radix-tree.h>
+#include <linux/err.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/sysfs.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/machine.h>
+#include "core.h"
+#include "pinmux.h"
+
+/* Global list of pin control devices */
+static DEFINE_MUTEX(pinctrldev_list_mutex);
+static LIST_HEAD(pinctrldev_list);
+
+/* sysfs interaction */
+static ssize_t pinctrl_name_show(struct device *dev,
+				struct device_attribute *attr, char *buf)
+{
+	struct pinctrl_dev *pctldev = dev_get_drvdata(dev);
+
+	return sprintf(buf, "%s\n", pctldev_get_name(pctldev));
+}
+
+static void pinctrl_dev_release(struct device *dev)
+{
+	struct pinctrl_dev *pctldev = dev_get_drvdata(dev);
+	kfree(pctldev);
+}
+
+static DEVICE_ATTR(name, S_IRUGO, pinctrl_name_show, NULL);
+
+static struct attribute *pinctrl_dev_attrs[] = {
+	&dev_attr_name.attr,
+	NULL
+};
+
+static struct attribute_group pinctrl_dev_attr_group = {
+	.attrs = pinctrl_dev_attrs,
+};
+
+static const struct attribute_group *pinctrl_dev_attr_groups[] = {
+	&pinctrl_dev_attr_group,
+	NULL
+};
+
+static struct bus_type pinctrl_bus = {
+	.name = "pinctrl",
+};
+
+static struct device_type pinctrl_type = {
+	.groups = pinctrl_dev_attr_groups,
+	.release = pinctrl_dev_release,
+};
+
+/**
+ * Looks up a pin control device matching a certain pinmux map
+ */
+struct pinctrl_dev *get_pctrldev_for_pinmux_map(struct pinmux_map const *map)
+{
+	struct pinctrl_dev *pctldev = NULL;
+	bool found = false;
+
+	mutex_lock(&pinctrldev_list_mutex);
+	list_for_each_entry(pctldev, &pinctrldev_list, node) {
+		if (map->ctrl_dev &&  &pctldev->dev == map->ctrl_dev) {
+			/* Matched on device */
+			found = true;
+			break;
+		}
+
+		if (map->ctrl_dev_name &&
+		    !strcmp(dev_name(&pctldev->dev), map->ctrl_dev_name)) {
+			/* Matched on device name */
+			found = true;
+			break;
+		}
+	}
+	mutex_unlock(&pinctrldev_list_mutex);
+
+	if (found)
+		return pctldev;
+
+	return NULL;
+}
+
+struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev, int pin)
+{
+	struct pin_desc *pindesc;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pctldev->pin_desc_tree_lock, flags);
+	pindesc = radix_tree_lookup(&pctldev->pin_desc_tree, pin);
+	spin_unlock_irqrestore(&pctldev->pin_desc_tree_lock, flags);
+
+	return pindesc;
+}
+
+/**
+ * Tell us whether a certain pin exist on a certain pin controller
+ * or not. Pin lists may be sparse, so some pins may not exist.
+ * @pctldev: the pin control device to check the pin on
+ * @pin: pin to check, use the local pin controller index number
+ */
+bool pin_is_valid(struct pinctrl_dev *pctldev, int pin)
+{
+	struct pin_desc *pindesc;
+
+	if (pin < 0)
+		return false;
+
+	pindesc = pin_desc_get(pctldev, pin);
+	if (pindesc == NULL)
+		return false;
+
+	return true;
+}
+EXPORT_SYMBOL_GPL(pin_is_valid);
+
+/* Deletes a range of pin descriptors */
+static void pinctrl_free_pindescs(struct pinctrl_dev *pctldev,
+				  const struct pinctrl_pin_desc *pins,
+				  unsigned num_pins)
+{
+	int i;
+
+	spin_lock(&pctldev->pin_desc_tree_lock);
+	for (i = 0; i < num_pins; i++) {
+		struct pin_desc *pindesc;
+
+		pindesc = radix_tree_lookup(&pctldev->pin_desc_tree,
+					    pins[i].number);
+		if (pindesc != NULL) {
+			radix_tree_delete(&pctldev->pin_desc_tree,
+					  pins[i].number);
+		}
+		kfree(pindesc);
+	}
+	spin_unlock(&pctldev->pin_desc_tree_lock);
+}
+
+static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev,
+				    unsigned number, const char *name)
+{
+	struct pin_desc *pindesc;
+
+	pindesc = pin_desc_get(pctldev, number);
+	if (pindesc != NULL) {
+		pr_err("pin %d already registered on %s\n", number,
+		       pctldev->desc->name);
+		return -EINVAL;
+	}
+
+	pindesc = kzalloc(sizeof(*pindesc), GFP_KERNEL);
+	if (pindesc == NULL)
+		return -ENOMEM;
+
+	/* Set owner */
+	pindesc->pctldev = pctldev;
+
+	/* Copy optional basic pin info */
+	if (name)
+		strlcpy(pindesc->name, name, sizeof(pindesc->name));
+
+	spin_lock(&pctldev->pin_desc_tree_lock);
+	radix_tree_insert(&pctldev->pin_desc_tree, number, pindesc);
+	spin_unlock(&pctldev->pin_desc_tree_lock);
+	pr_debug("registered pin %d (%s) on %s\n",
+		 number, name ? name : "(unnamed)", pctldev->desc->name);
+	return 0;
+}
+
+static int pinctrl_register_pins(struct pinctrl_dev *pctldev,
+				 struct pinctrl_pin_desc const *pins,
+				 unsigned num_descs)
+{
+	unsigned i;
+	int ret = 0;
+
+	for (i = 0; i < num_descs; i++) {
+		ret = pinctrl_register_one_pin(pctldev,
+					       pins[i].number, pins[i].name);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * pinctrl_match_gpio_range() - check if a certain GPIO pin is in the range of
+ * a certain pin controller, return the range or NULL
+ */
+static struct pinctrl_gpio_range *
+pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
+{
+	struct pinctrl_gpio_range *range = NULL;
+
+	/* Loop over the ranges */
+	spin_lock(&pctldev->gpio_ranges_lock);
+	list_for_each_entry(range, &pctldev->gpio_ranges, node) {
+		/* Check if we're in the valid range */
+		if (gpio >= range->base &&
+		    gpio < range->base + range->npins) {
+			spin_unlock(&pctldev->gpio_ranges_lock);
+			return range;
+		}
+	}
+	spin_unlock(&pctldev->gpio_ranges_lock);
+
+	return NULL;
+}
+
+/**
+ * pinctrl_get_device_gpio_range() - find the pin controller handling a certain
+ * pin from the pinspace in the GPIO subsystem, return the device and the
+ * matching GPIO range. Returns negative if the GPIO range could not be found
+ * in any device
+ * @gpio: the pin to locate the pin controller for
+ * @outdev: the pin control device if found
+ * @outrange: the GPIO range if found
+ */
+int pinctrl_get_device_gpio_range(unsigned gpio,
+				struct pinctrl_dev **outdev,
+				struct pinctrl_gpio_range **outrange)
+{
+	struct pinctrl_dev *pctldev = NULL;
+
+	/* Loop over the pin controllers */
+	mutex_lock(&pinctrldev_list_mutex);
+	list_for_each_entry(pctldev, &pinctrldev_list, node) {
+		struct pinctrl_gpio_range *range;
+
+		range = pinctrl_match_gpio_range(pctldev, gpio);
+		if (range != NULL) {
+			*outdev = pctldev;
+			*outrange = range;
+			return 0;
+		}
+	}
+	mutex_unlock(&pinctrldev_list_mutex);
+
+	return -EINVAL;
+}
+
+/**
+ * pinctrl_add_gpio_range() - this adds a range of GPIOs to be handled
+ * by a certain pin controller. Call this to register handled ranges after
+ * registering your pin controller.
+ * @pctldev: pin controller device to add the range to
+ * @range: the GPIO range to add
+ */
+void pinctrl_add_gpio_range(struct pinctrl_dev *pctldev,
+			    struct pinctrl_gpio_range *range)
+{
+	spin_lock(&pctldev->gpio_ranges_lock);
+	list_add(&range->node, &pctldev->gpio_ranges);
+	spin_unlock(&pctldev->gpio_ranges_lock);
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+static int pinctrl_pins_show(struct seq_file *s, void *what)
+{
+	struct pinctrl_dev *pctldev = s->private;
+	unsigned pin;
+
+	seq_printf(s, "registered pins: %d\n", pctldev->desc->npins);
+	seq_printf(s, "max pin number: %d\n", pctldev->desc->maxpin);
+
+	/* The highest pin number need to be included in the loop, thus <= */
+	for (pin = 0; pin <= pctldev->desc->maxpin; pin++) {
+		struct pin_desc *desc;
+
+		desc = pin_desc_get(pctldev, pin);
+		/* Pin space may be sparse */
+		if (desc == NULL)
+			continue;
+
+		seq_printf(s, "pin %d (%s)\n", pin,
+			   desc->name ? desc->name : "unnamed");
+	}
+
+	return 0;
+}
+
+static int pinctrl_gpioranges_show(struct seq_file *s, void *what)
+{
+	struct pinctrl_dev *pctldev = s->private;
+	struct pinctrl_gpio_range *range = NULL;
+
+	seq_puts(s, "GPIO ranges handled:\n");
+
+	/* Loop over the ranges */
+	spin_lock(&pctldev->gpio_ranges_lock);
+	list_for_each_entry(range, &pctldev->gpio_ranges, node) {
+		seq_printf(s, "%u: %s [%u - %u]\n", range->id, range->name,
+			   range->base, (range->base + range->npins - 1));
+	}
+	spin_unlock(&pctldev->gpio_ranges_lock);
+
+	return 0;
+}
+
+static int pinctrl_devices_show(struct seq_file *s, void *what)
+{
+	struct pinctrl_dev *pctldev;
+
+	seq_puts(s, "name [pinmux]\n");
+	mutex_lock(&pinctrldev_list_mutex);
+	list_for_each_entry(pctldev, &pinctrldev_list, node) {
+		seq_printf(s, "%s ", pctldev->desc->name);
+		if (pctldev->desc->pmxops)
+			seq_puts(s, "yes");
+		else
+			seq_puts(s, "no");
+		seq_puts(s, "\n");
+	}
+	mutex_unlock(&pinctrldev_list_mutex);
+
+	return 0;
+}
+
+static int pinctrl_pins_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, pinctrl_pins_show, inode->i_private);
+}
+
+static int pinctrl_gpioranges_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, pinctrl_gpioranges_show, inode->i_private);
+}
+
+static int pinctrl_devices_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, pinctrl_devices_show, NULL);
+}
+
+static const struct file_operations pinctrl_pins_ops = {
+	.open		= pinctrl_pins_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static const struct file_operations pinctrl_gpioranges_ops = {
+	.open		= pinctrl_gpioranges_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static const struct file_operations pinctrl_devices_ops = {
+	.open		= pinctrl_devices_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static struct dentry *debugfs_root;
+
+static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
+{
+	static struct dentry *device_root;
+
+	device_root = debugfs_create_dir(dev_name(&pctldev->dev),
+					 debugfs_root);
+	if (IS_ERR(device_root) || !device_root) {
+		pr_warn("failed to create debugfs directory for %s\n",
+			dev_name(&pctldev->dev));
+		return;
+	}
+	debugfs_create_file("pins", S_IFREG | S_IRUGO,
+			    device_root, pctldev, &pinctrl_pins_ops);
+	debugfs_create_file("gpio-ranges", S_IFREG | S_IRUGO,
+			    device_root, pctldev, &pinctrl_gpioranges_ops);
+	pinmux_init_device_debugfs(device_root, pctldev);
+}
+
+static void pinctrl_init_debugfs(void)
+{
+	debugfs_root = debugfs_create_dir("pinctrl", NULL);
+	if (IS_ERR(debugfs_root) || !debugfs_root) {
+		pr_warn("failed to create debugfs directory\n");
+		debugfs_root = NULL;
+		return;
+	}
+
+	debugfs_create_file("pinctrl-devices", S_IFREG | S_IRUGO,
+			    debugfs_root, NULL, &pinctrl_devices_ops);
+	pinmux_init_debugfs(debugfs_root);
+}
+
+#else /* CONFIG_DEBUG_FS */
+
+static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
+{
+}
+
+static void pinctrl_init_debugfs(void)
+{
+}
+
+#endif
+
+/**
+ * pinctrl_register() - register a pin controller device
+ * @pctldesc: descriptor for this pin controller
+ * @dev: parent device for this pin controller
+ * @driver_data: private pin controller data for this pin controller
+ */
+struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
+				    struct device *dev, void *driver_data)
+{
+	static atomic_t pinmux_no = ATOMIC_INIT(0);
+	struct pinctrl_dev *pctldev;
+	int ret;
+
+	if (pctldesc == NULL)
+		return ERR_PTR(-EINVAL);
+	if (pctldesc->name == NULL)
+		return ERR_PTR(-EINVAL);
+
+	/* If we're implementing pinmuxing, check the ops for sanity */
+	if (pctldesc->pmxops) {
+		ret = pinmux_check_ops(pctldesc->pmxops);
+		if (ret)
+			return ERR_PTR(ret);
+	}
+
+	pctldev = kzalloc(sizeof(struct pinctrl_dev), GFP_KERNEL);
+	if (pctldev == NULL)
+		return ERR_PTR(-ENOMEM);
+
+	/* Initialize pin control device struct */
+	pctldev->owner = pctldesc->owner;
+	pctldev->desc = pctldesc;
+	pctldev->driver_data = driver_data;
+	INIT_RADIX_TREE(&pctldev->pin_desc_tree, GFP_KERNEL);
+	spin_lock_init(&pctldev->pin_desc_tree_lock);
+	INIT_LIST_HEAD(&pctldev->gpio_ranges);
+	spin_lock_init(&pctldev->gpio_ranges_lock);
+
+	/* Register device with sysfs */
+	pctldev->dev.parent = dev;
+	pctldev->dev.bus = &pinctrl_bus;
+	pctldev->dev.type = &pinctrl_type;
+	dev_set_name(&pctldev->dev, "pinctrl.%d",
+		     atomic_inc_return(&pinmux_no) - 1);
+	ret = device_register(&pctldev->dev);
+	if (ret != 0) {
+		pr_err("error in device registration\n");
+		put_device(&pctldev->dev);
+		kfree(pctldev);
+		goto out_err;
+	}
+	dev_set_drvdata(&pctldev->dev, pctldev);
+
+	/* Register all the pins */
+	pr_debug("try to register %d pins on %s...\n",
+		 pctldesc->npins, pctldesc->name);
+	ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins);
+	if (ret) {
+		pr_err("error during pin registration\n");
+		pinctrl_free_pindescs(pctldev, pctldesc->pins,
+				      pctldesc->npins);
+		goto out_err;
+	}
+
+	pinctrl_init_device_debugfs(pctldev);
+	mutex_lock(&pinctrldev_list_mutex);
+	list_add(&pctldev->node, &pinctrldev_list);
+	mutex_unlock(&pinctrldev_list_mutex);
+	return pctldev;
+
+out_err:
+	put_device(&pctldev->dev);
+	kfree(pctldev);
+	return ERR_PTR(ret);
+}
+EXPORT_SYMBOL_GPL(pinctrl_register);
+
+/**
+ * pinctrl_unregister() - unregister pinmux
+ * @pctldev: pin controller to unregister
+ *
+ * Called by pinmux drivers to unregister a pinmux.
+ */
+void pinctrl_unregister(struct pinctrl_dev *pctldev)
+{
+	if (pctldev == NULL)
+		return;
+
+	mutex_lock(&pinctrldev_list_mutex);
+	list_del(&pctldev->node);
+	device_unregister(&pctldev->dev);
+	mutex_unlock(&pinctrldev_list_mutex);
+	/* Destroy descriptor tree */
+	pinctrl_free_pindescs(pctldev, pctldev->desc->pins,
+			      pctldev->desc->npins);
+}
+EXPORT_SYMBOL_GPL(pinctrl_unregister);
+
+static int __init pinctrl_init(void)
+{
+	int ret;
+
+	ret = bus_register(&pinctrl_bus);
+	if (ret) {
+		pr_crit("could not register pinctrl bus\n");
+		return ret;
+	}
+
+	pr_info("initialized pinctrl subsystem\n");
+	pinctrl_init_debugfs();
+	return 0;
+}
+
+/* init early since many drivers really need to initialized pinmux early */
+core_initcall(pinctrl_init);
diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
new file mode 100644
index 0000000..283007c
--- /dev/null
+++ b/drivers/pinctrl/core.h
@@ -0,0 +1,24 @@
+/**
+ * struct pin_desc - pin descriptor for each physical pin in the arch
+ * @pctldev: corresponding pin control device
+ * @name: a name for the pin, e.g. the name of the pin/pad/finger on a
+ *	datasheet or such
+ * @mux_requested: whether the pin is already requested by pinmux or not
+ * @mux_function: a named muxing function for the pin that will be passed to
+ *	subdrivers and shown in debugfs etc
+ */
+struct pin_desc {
+	struct pinctrl_dev *pctldev;
+	char	name[16];
+	/* These fields only added when supporting pinmux drivers */
+#ifdef CONFIG_PINMUX
+	bool	mux_requested;
+	char	mux_function[16];
+#endif
+};
+
+struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev, int pin);
+struct pinctrl_dev *get_pctrldev_for_pinmux_map(struct pinmux_map const *map);
+int pinctrl_get_device_gpio_range(unsigned gpio,
+				  struct pinctrl_dev **outdev,
+				  struct pinctrl_gpio_range **outrange);
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
new file mode 100644
index 0000000..310d344
--- /dev/null
+++ b/drivers/pinctrl/pinmux.c
@@ -0,0 +1,811 @@
+/*
+ * Core driver for the pin muxing portions of the pin control subsystem
+ *
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ * Based on bits of regulator core, gpio core and clk core
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#define pr_fmt(fmt) "pinmux core: " fmt
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/radix-tree.h>
+#include <linux/err.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/sysfs.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinmux.h>
+#include "core.h"
+
+/* Global list of pinmuxes */
+static DEFINE_MUTEX(pinmux_list_mutex);
+static LIST_HEAD(pinmux_list);
+
+/**
+ * struct pinmux - per-device pinmux state holder
+ * @node: global list node - only for internal use
+ * @dev: the device using this pinmux
+ * @map: corresponding pinmux map active for this pinmux setting
+ * @usecount: the number of active users of this mux setting, used to keep
+ *	track of nested use cases
+ * @pins: an array of discrete physical pins used in this mapping, taken
+ *	from the global pin enumeration space (copied from pinmux map)
+ * @num_pins: the number of pins in this mapping array, i.e. the number of
+ *	elements in .pins so we can iterate over that array (copied from
+ *	pinmux map)
+ * @pctldev: pin control device handling this pinmux
+ * @pmxdev_selector: the function selector for the pinmux device handling
+ *	this pinmux
+ * @pmxdev_position: the function position for the pinmux device and
+ *	selector handling this pinmux
+ * @mutex: a lock for the pinmux state holder
+ */
+struct pinmux {
+	struct list_head node;
+	struct device *dev;
+	struct pinmux_map const *map;
+	unsigned usecount;
+	struct pinctrl_dev *pctldev;
+	unsigned pmxdev_selector;
+	unsigned pmxdev_position;
+	struct mutex mutex;
+};
+
+/**
+ * pin_request() - request a single pin to be muxed in, typically for GPIO
+ * @pin: the pin number in the global pin space
+ * @function: a functional name to give to this pin, passed to the driver
+ *	so it knows what function to mux in, e.g. the string "gpioNN"
+ *	means that you want to mux in the pin for use as GPIO number NN
+ * @gpio: if this request concerns a single GPIO pin
+ * @gpio_range: the range matching the GPIO pin if this is a request for a
+ *	single GPIO pin
+ */
+static int pin_request(struct pinctrl_dev *pctldev,
+		       int pin, const char *function, bool gpio,
+		       struct pinctrl_gpio_range *gpio_range)
+{
+	struct pin_desc *desc;
+	const struct pinmux_ops *ops;
+	int status = -EINVAL;
+
+	pr_debug("request pin %d for %s\n", pin, function);
+
+	if (!pin_is_valid(pctldev, pin)) {
+		pr_err("pin is invalid\n");
+		return -EINVAL;
+	}
+
+	if (!function) {
+		pr_err("no function name given\n");
+		return -EINVAL;
+	}
+
+	desc = pin_desc_get(pctldev, pin);
+	if (desc == NULL) {
+		pr_err("pin is not registered so it cannot be requested\n");
+		goto out;
+	}
+	if (desc->mux_requested) {
+		pr_err("pin already requested\n");
+		goto out;
+	}
+	ops = pctldev->desc->pmxops;
+
+	/* Let each pin increase references to this module */
+	if (!try_module_get(pctldev->owner)) {
+		pr_err("could not increase module refcount for pin %d\n", pin);
+		status = -EINVAL;
+		goto out;
+	}
+
+	/*
+	 * If there is no kind of request function for the pin we just assume
+	 * we got it by default and proceed.
+	 */
+	if (gpio && ops->gpio_request_enable)
+		/* This requests and enables a single GPIO pin */
+		status = ops->gpio_request_enable(pctldev, gpio_range, pin);
+	else if (ops->request)
+		status = ops->request(pctldev, pin);
+	else
+		status = 0;
+
+	if (status) {
+		pr_err("->request on device %s failed "
+		       "for pin %d\n",
+		       pctldev->desc->name, pin);
+		goto out;
+	}
+
+	desc->mux_requested = true;
+	strncpy(desc->mux_function, function, sizeof(desc->mux_function));
+
+out:
+	if (status)
+		pr_err("pin-%d (%s) status %d\n",
+		       pin, function ? : "?", status);
+
+	return status;
+}
+
+/**
+ * pin_free() - release a single muxed in pin so something else can be muxed in
+ *	instead
+ * @pin: the pin to free
+ */
+static void pin_free(struct pinctrl_dev *pctldev, int pin)
+{
+	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+	struct pin_desc *desc;
+
+	desc = pin_desc_get(pctldev, pin);
+	if (desc == NULL) {
+		pr_err("pin is not registered so it cannot be freed\n");
+		return;
+	}
+
+	if (ops->free)
+		ops->free(pctldev, pin);
+
+	desc->mux_requested = false;
+	desc->mux_function[0] = '\0';
+	module_put(pctldev->owner);
+}
+
+/**
+ * pinmux_request_gpio() - request a single pin to be muxed in to be used
+ *	as a GPIO pin
+ * @gpio: the GPIO pin number from the GPIO subsystem number space
+ */
+int pinmux_request_gpio(unsigned gpio)
+{
+	char gpiostr[16];
+	struct pinctrl_dev *pctldev;
+	struct pinctrl_gpio_range *range;
+	int ret;
+	int pin;
+
+	ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
+	if (ret)
+		return -EINVAL;
+
+	/* Convert to the pin controllers number space */
+	pin = gpio - range->base;
+
+	/* Conjure some name stating what chip and pin this is taken by */
+	snprintf(gpiostr, 15, "%s:%d", range->name, gpio);
+
+	return pin_request(pctldev, pin, gpiostr, true, range);
+}
+EXPORT_SYMBOL_GPL(pinmux_request_gpio);
+
+/**
+ * pinmux_free_gpio() - free a single pin, currently muxed in to be used
+ *	as a GPIO pin
+ * @gpio: the GPIO pin number from the GPIO subsystem number space
+ */
+void pinmux_free_gpio(unsigned gpio)
+{
+	struct pinctrl_dev *pctldev;
+	struct pinctrl_gpio_range *range;
+	int ret;
+	int pin;
+
+	ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
+	if (ret)
+		return;
+
+	/* Convert to the pin controllers number space */
+	pin = gpio - range->base;
+
+	pin_free(pctldev, pin);
+}
+EXPORT_SYMBOL_GPL(pinmux_free_gpio);
+
+int pinmux_register_mappings(struct pinmux_map const *maps, unsigned num_maps)
+{
+	int ret = 0;
+	int i;
+
+	pr_debug("add %d functions\n", num_maps);
+	for (i = 0; i < num_maps; i++) {
+		struct pinmux *pmx;
+
+		/* Sanity check the mapping */
+		if (!maps[i].function) {
+			pr_err("failed to register map %d - no function ID given\n", i);
+			ret = -EINVAL;
+			goto out;
+		}
+
+		if (!maps[i].dev && !maps[i].dev_name)
+			pr_debug("add anonymous function %s with no device\n",
+				 maps[i].function);
+
+		/*
+		 * create the state cookie holder struct pinmux for each
+		 * mapping, this is what consumers will get when requesting
+		 * a pinmux handle with pinmux_get()
+		 */
+		pmx = kzalloc(sizeof(struct pinmux), GFP_KERNEL);
+		if (pmx == NULL) {
+			ret = -ENOMEM;
+			goto out;
+		}
+		mutex_init(&pmx->mutex);
+		pmx->map = &maps[i];
+
+		/* Add the pinmux */
+		mutex_lock(&pinmux_list_mutex);
+		list_add(&pmx->node, &pinmux_list);
+		mutex_unlock(&pinmux_list_mutex);
+		pr_debug("add function %s\n", maps[i].function);
+	}
+
+out:
+	return ret;
+}
+
+/**
+ * acquire_pins() - acquire all the pins for a certain funcion on a certain
+ *	pinmux device
+ * @pctldev: the device to take the pins on
+ * @selector: the function selector to acquire the pins for
+ * @position: the function position to acquire the pins for
+ */
+static int acquire_pins(struct pinctrl_dev *pctldev, unsigned selector,
+			unsigned position)
+{
+	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+	unsigned *pins;
+	unsigned num_pins;
+	const char *func = ops->get_function_name(pctldev, selector);
+	int ret;
+	int i;
+
+	ret = ops->get_function_pins(pctldev, selector, position,
+				     &pins, &num_pins);
+	if (ret)
+		return ret;
+
+	/* Try to allocate all pins in this pinmux map, one by one */
+	for (i = 0; i < num_pins; i++) {
+		ret = pin_request(pctldev, pins[i], func, false, NULL);
+		if (ret) {
+			pr_err("could not get pin %d for function %s "
+			       "on device %s - conflicting mux mappings?\n",
+			       pins[i], func ? : "(undefined)",
+			       pctldev->desc->name);
+			/* On error release all taken pins */
+			i--; /* this pin just failed */
+			for (; i >= 0; i--)
+				pin_free(pctldev, pins[i]);
+			return -ENODEV;
+		}
+	}
+	return 0;
+}
+
+/**
+ * release_pins() - release pins taken by earlier acquirement
+ * @pctldev: the device to free the pinx on
+ * @selector: the function selector to free the pins for
+ * @position: the function position to release the pins for
+ */
+static void release_pins(struct pinctrl_dev *pctldev, unsigned selector,
+			 unsigned position)
+{
+	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+	unsigned *pins;
+	unsigned num_pins;
+	int ret;
+	int i;
+
+	ret = ops->get_function_pins(pctldev, selector, position,
+				     &pins, &num_pins);
+	if (ret) {
+		dev_err(&pctldev->dev, "could not get pins to release for "
+			"selector %d, position %d\n",
+			selector, position);
+		return;
+	}
+	for (i = 0; i < num_pins; i++)
+		pin_free(pctldev, pins[i]);
+}
+
+/**
+ * pinmux_check_position() - check that the pinmux driver can supply the
+ * function in a certain position
+ * @pctldev: device to check the position for
+ * @selector: the selector to check the position for
+ * @position: the position to check
+ */
+static int pinmux_check_position(struct pinctrl_dev *pctldev,
+				 unsigned selector, unsigned position)
+{
+	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+	unsigned posit = 0;
+
+	/*
+	 * If the driver does not support different positions for the
+	 * functions, we only support position 0.
+	 */
+	if (!ops->list_positions) {
+		if (position != 0)
+			return -EINVAL;
+		return 0;
+	}
+
+	/* Else check that we support this position */
+	while (ops->list_positions(pctldev, selector, posit) >= 0) {
+		if (posit == position)
+			return 0;
+		posit++;
+	}
+
+	pr_err("%s does not support pinmux position %d for function %s\n",
+	       pctldev_get_name(pctldev), position,
+	       ops->get_function_name(pctldev, selector));
+	return -EINVAL;
+}
+
+/**
+ * pinmux_search_function() - search the pinmux driver for an applicable
+ * function in a specific position, returns the applicable selector if
+ * found
+ * @pctldev: device to check for function and position
+ * @map: function map containing the function and position to look for
+ */
+static int pinmux_search_function(struct pinctrl_dev *pctldev,
+				  struct pinmux_map const *map)
+{
+	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+	unsigned selector = 0;
+
+	/* See if this pctldev has this function */
+	while (ops->list_functions(pctldev, selector) >= 0) {
+		const char *fname = ops->get_function_name(pctldev,
+							   selector);
+		int ret;
+
+		if (!strcmp(map->function, fname)) {
+			/* Found the function, check position */
+			ret = pinmux_check_position(pctldev, selector,
+						    map->position);
+			if (ret < 0)
+				return ret;
+			return selector;
+		}
+		selector++;
+	}
+
+	pr_err("%s does not support function %s\n",
+	       pctldev_get_name(pctldev), map->function);
+	return -EINVAL;
+}
+
+
+/**
+ * pinmux_get() - retrieves the pinmux for a certain device
+ * @dev: the device to get the pinmux for
+ * @name: an optional specific mux mapping name or NULL, the name is only
+ *	needed if you want to have more than one mapping per device, or if you
+ *	need an anonymous pinmux (not tied to any specific device)
+ */
+struct pinmux *pinmux_get(struct device *dev, const char *name)
+{
+
+	struct pinmux_map const *map = NULL;
+	struct pinctrl_dev *pctldev = NULL;
+	const char *devname = NULL;
+	struct pinmux *pmx;
+	bool found_map = false;
+	int ret = -ENODEV;
+
+	/* We must have dev or ID or both */
+	if (!dev && !name)
+		return ERR_PTR(-EINVAL);
+
+	mutex_lock(&pinmux_list_mutex);
+
+	if (dev)
+		devname = dev_name(dev);
+
+	/* Iterate over the pinmux maps to locate the right one */
+	list_for_each_entry(pmx, &pinmux_list, node) {
+		map = pmx->map;
+
+		/*
+		 * First, try to find the pctldev given in the map
+		 */
+		pctldev = get_pctrldev_for_pinmux_map(map);
+		if (!pctldev) {
+			const char *devname = NULL;
+
+			if (map->ctrl_dev)
+				devname = dev_name(map->ctrl_dev);
+			else if (map->ctrl_dev_name)
+				devname = map->ctrl_dev_name;
+
+			pr_warning("could not find a pinctrl device for pinmux "
+				   "function %s, fishy, they shall all have one\n",
+				   map->function);
+			pr_warning("given pinctrl device name: %s",
+				   devname ? devname : "UNDEFINED");
+
+			/* Continue to check the other mappings anyway... */
+			continue;
+		}
+
+		pr_debug("found pctldev %s to handle function %s",
+			 dev_name(&pctldev->dev), map->function);
+
+
+		/*
+		 * If we're looking for a specific named map, this must match,
+		 * else we loop and look for the next.
+		 */
+		if (name != NULL) {
+			if (map->name == NULL)
+				continue;
+			if (strcmp(map->name, name))
+				continue;
+		}
+
+		/*
+		 * This is for the case where no device name is given, we
+		 * already know that the function name matches from above
+		 * code.
+		 */
+		if (!map->dev_name && (name != NULL)) {
+			found_map = true;
+			break;
+		}
+
+		/* If the mapping has a device set up it must match */
+		if (map->dev_name &&
+		    (!devname || !strcmp(map->dev_name, devname))) {
+			/* MATCH! */
+			found_map = true;
+			break;
+		}
+	}
+
+	mutex_unlock(&pinmux_list_mutex);
+
+	if (!found_map) {
+		pr_err("could not find mux map for device %s, ID %s\n",
+		       devname ? devname : "(anonymous)",
+		       name ? name : "(undefined)");
+		goto out;
+	}
+
+	/* Make sure that noone else is using this pinmux */
+	mutex_lock(&pmx->mutex);
+	if (pmx->dev) {
+		if (pmx->dev != dev) {
+			mutex_unlock(&pmx->mutex);
+			pr_err("mapping already in use device %s, ID %s\n",
+			       devname ? devname : "(anonymous)",
+			       name ? name : "(undefined)");
+			goto out;
+		} else {
+			/* We already fetched this and requested pins */
+			mutex_unlock(&pmx->mutex);
+			ret = 0;
+			goto out;
+		}
+	}
+	mutex_unlock(&pmx->mutex);
+
+	/* Now go into the driver and try to locate function @position */
+	ret = pinmux_search_function(pctldev, map);
+	if (ret < 0)
+		goto out;
+	else {
+		/* Found function @position */
+		unsigned selector = ret;
+
+		ret = acquire_pins(pctldev, selector, map->position);
+		if (ret)
+			goto out;
+		/* Found it! */
+		mutex_lock(&pmx->mutex);
+		pmx->dev = dev;
+		pmx->pctldev = pctldev;
+		pmx->pmxdev_selector = selector;
+		pmx->pmxdev_position = map->position;
+		mutex_unlock(&pmx->mutex);
+		ret = 0;
+		goto out;
+	}
+
+	/* We couldn't find the driver for this pinmux */
+	ret = -ENODEV;
+
+out:
+	if (ret)
+		pmx = ERR_PTR(ret);
+
+	return pmx;
+}
+EXPORT_SYMBOL_GPL(pinmux_get);
+
+/**
+ * pinmux_put() - release a previously claimed pinmux
+ * @pmx: a pinmux previously claimed by pinmux_get()
+ */
+void pinmux_put(struct pinmux *pmx)
+{
+	if (pmx == NULL)
+		return;
+	mutex_lock(&pmx->mutex);
+	if (pmx->usecount)
+		pr_warn("releasing pinmux with active users!\n");
+	/* Release all pins taken on pinmux_get() */
+	release_pins(pmx->pctldev, pmx->pmxdev_selector, pmx->pmxdev_position);
+	pmx->dev = NULL;
+	pmx->pctldev = NULL;
+	pmx->pmxdev_selector = 0;
+	mutex_unlock(&pmx->mutex);
+}
+EXPORT_SYMBOL_GPL(pinmux_put);
+
+/**
+ * pinmux_enable() - enable a certain pinmux setting
+ * @pmx: the pinmux to enable, previously claimed by pinmux_get()
+ */
+int pinmux_enable(struct pinmux *pmx)
+{
+	int ret = 0;
+
+	if (pmx == NULL)
+		return -EINVAL;
+	mutex_lock(&pmx->mutex);
+	if (pmx->usecount++ == 0) {
+		struct pinctrl_dev *pctldev = pmx->pctldev;
+		const struct pinmux_ops *ops = pctldev->desc->pmxops;
+
+		ret = ops->enable(pctldev, pmx->pmxdev_selector,
+				  pmx->pmxdev_position);
+		if (ret)
+			pmx->usecount--;
+	}
+	mutex_unlock(&pmx->mutex);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(pinmux_enable);
+
+/**
+ * pinmux_disable() - disable a certain pinmux setting
+ * @pmx: the pinmux to disable, previously claimed by pinmux_get()
+ */
+void pinmux_disable(struct pinmux *pmx)
+{
+	if (pmx == NULL)
+		return;
+
+	mutex_lock(&pmx->mutex);
+	if (--pmx->usecount == 0) {
+		struct pinctrl_dev *pctldev = pmx->pctldev;
+		const struct pinmux_ops *ops = pctldev->desc->pmxops;
+
+		ops->disable(pctldev, pmx->pmxdev_selector,
+			     pmx->pmxdev_position);
+	}
+	mutex_unlock(&pmx->mutex);
+}
+EXPORT_SYMBOL_GPL(pinmux_disable);
+
+/**
+ * pinmux_config() - configure a certain pinmux setting
+ * @pmx: the pinmux setting to configure
+ * @param: the parameter to configure
+ * @data: extra data to be passed to the configuration, also works as a
+ *	pointer to data returned from the function on success
+ */
+int pinmux_config(struct pinmux *pmx, u16 param, unsigned long *data)
+{
+	struct pinctrl_dev *pctldev;
+	const struct pinmux_ops *ops;
+	int ret = 0;
+
+	if (pmx == NULL)
+		return -ENODEV;
+
+	pctldev = pmx->pctldev;
+	ops = pctldev->desc->pmxops;
+
+	/* This operation is not mandatory to implement */
+	if (ops->config) {
+		mutex_lock(&pmx->mutex);
+		ret = ops->config(pctldev, pmx->pmxdev_selector, param, data);
+		mutex_unlock(&pmx->mutex);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(pinmux_config);
+
+int pinmux_check_ops(const struct pinmux_ops *ops)
+{
+	/* Check that we implement required operations */
+	if (!ops->list_functions ||
+	    !ops->get_function_name ||
+	    !ops->enable ||
+	    !ops->disable)
+		return -EINVAL;
+
+	return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+/* Called from pincontrol core */
+static int pinmux_functions_show(struct seq_file *s, void *what)
+{
+	struct pinctrl_dev *pctldev = s->private;
+	const struct pinmux_ops *ops = pctldev->desc->pmxops;
+	unsigned selector = 0;
+
+	while (ops->list_functions(pctldev, selector) >= 0) {
+		unsigned *pins;
+		unsigned num_pins;
+		const char *func = ops->get_function_name(pctldev, selector);
+		unsigned position = 0;
+		int ret;
+		int i;
+
+		while (ops->list_positions(pctldev, selector, position) >= 0) {
+			ret = ops->get_function_pins(pctldev, selector,
+						     position,
+						     &pins, &num_pins);
+
+			if (ret)
+				seq_printf(s, "%s [ERROR GETTING PINS]\n",
+					   func);
+
+			else {
+				seq_printf(s, "function: %s, position: %d pins = [ ",
+					   func, position);
+				for (i = 0; i < num_pins; i++)
+					seq_printf(s, "%d ", pins[i]);
+				seq_puts(s, "]\n");
+			}
+			position++;
+		}
+
+		selector++;
+
+	}
+
+	return 0;
+}
+
+static int pinmux_show(struct seq_file *s, void *what)
+{
+	struct pinmux *pmx;
+	const struct pinmux_map *map;
+
+	seq_puts(s, "System pinmuxes and their maps:\n");
+	list_for_each_entry(pmx, &pinmux_list, node) {
+		map = pmx->map;
+
+		seq_printf(s, "device: %s function: %s (%u), "
+			   "pos %u users: %u map-> %s\n",
+			   pmx->pctldev ? pctldev_get_name(pmx->pctldev) : "(no controller)",
+			   map->function,
+			   pmx->pmxdev_selector,
+			   map->position,
+			   pmx->usecount,
+			   pmx->dev ? dev_name(pmx->dev) : "(no device)");
+	}
+
+	return 0;
+}
+
+static int pinmux_pins_show(struct seq_file *s, void *what)
+{
+	struct pinctrl_dev *pctldev = s->private;
+	unsigned pin;
+
+	if (pctldev == NULL) {
+		seq_puts(s, "device is gone\n");
+		return 0;
+	}
+
+	if (pctldev->desc == NULL) {
+		seq_puts(s, "device is lacking descriptor\n");
+		return 0;
+	}
+
+	seq_puts(s, "Pinmux settings per pin\n");
+	seq_puts(s, "Format: pin (name): pinmuxfunction [driver specifics]\n");
+
+	/* The highest pin number need to be included in the loop, thus <= */
+	for (pin = 0; pin <= pctldev->desc->maxpin; pin++) {
+
+		struct pin_desc *desc;
+
+		desc = pin_desc_get(pctldev, pin);
+		/* Pin space may be sparse */
+		if (desc == NULL)
+			continue;
+
+		else {
+			seq_printf(s, "pin %d (%s): %s", pin,
+				   desc->name ? desc->name : "unnamed",
+				   desc->mux_requested ? desc->mux_function : "UNCLAIMED");
+
+			if (pctldev->desc->pmxops->dbg_show)
+				pctldev->desc->pmxops->dbg_show(pctldev, s, pin);
+		}
+		seq_puts(s, "\n");
+	}
+
+	return 0;
+}
+
+static int pinmux_functions_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, pinmux_functions_show, inode->i_private);
+}
+
+static int pinmux_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, pinmux_show, NULL);
+}
+
+static int pinmux_pins_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, pinmux_pins_show, inode->i_private);
+}
+
+static const struct file_operations pinmux_functions_ops = {
+	.open		= pinmux_functions_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static const struct file_operations pinmux_ops = {
+	.open		= pinmux_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static const struct file_operations pinmux_pins_ops = {
+	.open		= pinmux_pins_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+void pinmux_init_device_debugfs(struct dentry *devroot,
+			 struct pinctrl_dev *pctldev)
+{
+	debugfs_create_file("pinmux-functions", S_IFREG | S_IRUGO,
+			    devroot, pctldev, &pinmux_functions_ops);
+	debugfs_create_file("pinmux-pins", S_IFREG | S_IRUGO,
+			    devroot, pctldev, &pinmux_pins_ops);
+}
+
+void pinmux_init_debugfs(struct dentry *subsys_root)
+{
+	debugfs_create_file("pinmuxes", S_IFREG | S_IRUGO,
+			    subsys_root, NULL, &pinmux_ops);
+}
+
+#endif /* CONFIG_DEBUG_FS */
diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h
new file mode 100644
index 0000000..ab672ef
--- /dev/null
+++ b/drivers/pinctrl/pinmux.h
@@ -0,0 +1,4 @@
+int pinmux_check_ops(const struct pinmux_ops *ops);
+void pinmux_init_device_debugfs(struct dentry *devroot,
+				struct pinctrl_dev *pctldev);
+void pinmux_init_debugfs(struct dentry *subsys_root);
diff --git a/include/linux/pinctrl/machine.h b/include/linux/pinctrl/machine.h
new file mode 100644
index 0000000..6da2471
--- /dev/null
+++ b/include/linux/pinctrl/machine.h
@@ -0,0 +1,74 @@
+/*
+ * Machine interface for the pinctrl subsystem.
+ *
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ * Based on bits of regulator core, gpio core and clk core
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef __LINUX_PINMUX_MACHINE_H
+#define __LINUX_PINMUX_MACHINE_H
+
+/**
+ * struct pinmux_map - boards/machines shall provide this map for devices
+ * @name: the name of this specific map entry for the particular machine.
+ *	This is the second parameter passed to pinmux_get() when you want
+ *	to have several mappings to the same device
+ * @ctrl_dev: the pin control device to be used by this mapping, may be NULL
+ *	if you provide .ctrl_dev_name instead (this is more common)
+ * @ctrl_dev_name: the name of the device controlling this specific mapping,
+ *	the name must be the same as in your struct device*
+ * @function: a function in the driver to use for this mapping, the driver
+ *	will lookup the function referenced by this ID on the specified
+ *	pin control device
+ * @position: sometimes a function has several possible positions in the
+ *	pin space, so this parameter accepts a certain position enumerator.
+ *	If for example a certain port can be mapped in three different
+ *	locations this could be 0, 1 or 2
+ * @dev: the device using this specific mapping, may be NULL if you provide
+ *	.dev_name instead (this is more common)
+ * @dev_name: the name of the device using this specific mapping, the name
+ *	must be the same as in your struct device*
+ */
+struct pinmux_map {
+	const char *name;
+	struct device *ctrl_dev;
+	const char *ctrl_dev_name;
+	const char *function;
+	unsigned position;
+	struct device *dev;
+	const char *dev_name;
+};
+
+/*
+ * Convenience macro to set a simple map from a certain pin controller and a
+ * certain function to a named device
+ */
+#define PINMUX_MAP(a, b, c) \
+	{ .ctrl_dev_name = a, .function = b, .dev_name = c }
+/*
+ * Convenience macro to map a function onto the primary device pinctrl device
+ * this is especially helpful on systems that have only one pin controller
+ * or need to set up a lot of mappings on the primary controller.
+ */
+#define PINMUX_MAP_PRIMARY(a, b) \
+	{ .ctrl_dev_name = "pinctrl.0", .function = a, .dev_name = b }
+
+#ifdef CONFIG_PINMUX
+
+extern int pinmux_register_mappings(struct pinmux_map const *map,
+				unsigned num_maps);
+
+#else
+
+static inline int pinmux_register_mappings(struct pinmux_map const *map,
+					   unsigned num_maps)
+{
+	return 0;
+}
+
+#endif /* !CONFIG_PINCTRL */
+#endif
diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h
new file mode 100644
index 0000000..0294e39
--- /dev/null
+++ b/include/linux/pinctrl/pinctrl.h
@@ -0,0 +1,143 @@
+/*
+ * Interface the pinctrl subsystem
+ *
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ * This interface is used in the core to keep track of pins.
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef __LINUX_PINCTRL_PINCTRL_H
+#define __LINUX_PINCTRL_PINCTRL_H
+
+#ifdef CONFIG_PINCTRL
+
+#include <linux/radix-tree.h>
+#include <linux/spinlock.h>
+#include <linux/list.h>
+
+struct pinmux_ops;
+struct gpio_chip;
+
+/**
+ * struct pinctrl_pin_desc - boards/machines provide information on their
+ * pins, pads or other muxable units in this struct
+ * @number: unique pin number from the global pin number space
+ * @name: a name for this pin
+ */
+struct pinctrl_pin_desc {
+	unsigned number;
+	const char *name;
+};
+
+/* Convenience macro to define a single named or anonymous pin descriptor */
+#define PINCTRL_PIN(a, b) { .number = a, .name = b }
+#define PINCTRL_PIN_ANON(a) { .number = a }
+
+/**
+ * struct pinctrl_gpio_range - each pin controller can provide subranges of
+ * the GPIO number space to be handled by the controller
+ * @name: a name for the chip in this range
+ * @id: an ID number for the chip in this range
+ * @base: base offset of the GPIO range
+ * @npins: number of pins in the GPIO range, including the base number
+ * @gc: an optional pointer to a gpio_chip
+ * @node: list node for internal use
+ */
+struct pinctrl_gpio_range {
+	const char name[16];
+	unsigned int id;
+	unsigned int base;
+	unsigned int npins;
+	struct gpio_chip *gc;
+	struct list_head node;
+};
+
+/**
+ * struct pinctrl_desc - pin controller descriptor, register this to pin
+ * control subsystem
+ * @name: name for the pin controller
+ * @pins: an array of pin descriptors describing all the pins handled by
+ *	this pin controller
+ * @npins: number of descriptors in the array, usually just ARRAY_SIZE()
+ *	of the pins field above
+ * @maxpin: since pin spaces may be sparse, there can he "holes" in the
+ *	pin range, this attribute gives the maximum pin number in the
+ *	total range. This should not be lower than npins for example,
+ *	but may be equal to npins if you have no holes in the pin range.
+ * @pmxops: pinmux operation vtable, if you support pinmuxing in your driver
+ * @owner: module providing the pin controller, used for refcounting
+ */
+struct pinctrl_desc {
+	const char *name;
+	struct pinctrl_pin_desc const *pins;
+	unsigned int npins;
+	unsigned int maxpin;
+	struct pinmux_ops *pmxops;
+	struct module *owner;
+};
+
+/**
+ * struct pinctrl_dev - pin control class device
+ * @desc: the pin controller descriptor supplied when initializing this pin
+ *	controller
+ * @pin_desc_tree: each pin descriptor for this pin controller is stored in
+ *	this radix tree
+ * @pin_desc_tree_lock: lock for the descriptor tree
+ * @gpio_ranges: a list of GPIO ranges that is handled by this pin controller,
+ *	ranges are added to this list at runtime
+ * @gpio_ranges_lock: lock for the GPIO ranges list
+ * @dev: the device entry for this pin controller
+ * @owner: module providing the pin controller, used for refcounting
+ * @driver_data: driver data for drivers registering to the pin controller
+ *	subsystem
+ * @node: node to include this pin controller in the global pin controller list
+ *
+ * This should be dereferenced and used by the pin controller core ONLY
+ */
+struct pinctrl_dev {
+	struct pinctrl_desc *desc;
+	struct radix_tree_root pin_desc_tree;
+	spinlock_t pin_desc_tree_lock;
+	struct list_head gpio_ranges;
+	spinlock_t gpio_ranges_lock;
+	struct device dev;
+	struct module *owner;
+	void *driver_data;
+	struct list_head node;
+};
+
+/* These should only be used from drivers */
+static inline const char *pctldev_get_name(struct pinctrl_dev *pctldev)
+{
+	/* We're not allowed to register devices without name */
+	return pctldev->desc->name;
+}
+
+static inline void *pctldev_get_drvdata(struct pinctrl_dev *pctldev)
+{
+	return pctldev->driver_data;
+}
+
+/* External interface to pin controller */
+extern struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
+				struct device *dev, void *driver_data);
+extern void pinctrl_unregister(struct pinctrl_dev *pctldev);
+extern bool pin_is_valid(struct pinctrl_dev *pctldev, int pin);
+extern void pinctrl_add_gpio_range(struct pinctrl_dev *pctldev,
+				   struct pinctrl_gpio_range *range);
+#else
+
+struct pinctrl_dev;
+
+/* Sufficiently stupid default function when pinctrl is not in use */
+static inline bool pin_is_valid(struct pinctrl_dev *pctldev, int pin)
+{
+	return pin >= 0;
+}
+
+#endif /* !CONFIG_PINCTRL */
+
+#endif /* __LINUX_PINCTRL_PINCTRL_H */
diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h
new file mode 100644
index 0000000..2583cc7
--- /dev/null
+++ b/include/linux/pinctrl/pinmux.h
@@ -0,0 +1,135 @@
+/*
+ * Interface the pinmux subsystem
+ *
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Written on behalf of Linaro for ST-Ericsson
+ * Based on bits of regulator core, gpio core and clk core
+ *
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#ifndef __LINUX_PINCTRL_PINMUX_H
+#define __LINUX_PINCTRL_PINMUX_H
+
+#include <linux/list.h>
+#include <linux/seq_file.h>
+#include "pinctrl.h"
+
+/* This struct is private to the core and should be regarded as a cookie */
+struct pinmux;
+
+#ifdef CONFIG_PINMUX
+
+struct pinctrl_dev;
+
+/**
+ * struct pinmux_ops - pinmux operations, to be implemented by pin controller
+ * drivers that support pinmuxing
+ * @request: called by the core to see if a certain pin can be made available
+ *	available for muxing. This is called by the core to acquire the pins
+ *	before selecting any actual mux setting across a function. The driver
+ *	is allowed to answer "no" by returning a negative error code
+ * @free: the reverse function of the request() callback, frees a pin after
+ *	being requested
+ * @list_functions: list the number of selectable named functions available
+ *	in this pinmux driver, the core will begin on 0 and call this
+ *	repeatedly as long as it returns >= 0 to enumerate mux settings
+ * @list_positions: list the number of selectable positions for a certain
+ *	function selector, the core will begin on 0 and call this repeatedly
+ *	as long as it returns >= 0 to enumerate positions
+ * @get_function_name: return the function name of the muxing selector,
+ *	called by the core to figure out which mux setting it shall map a
+ *	certain device to
+ * @get_function_pins: return an array of pins corresponding to a certain
+ *	function selector and position in @pins, and the size of the array
+ *	in @num_pins
+ * @enable: enable a certain muxing function on a certain position. The driver
+ *	does not need to figure out whether enabling this function conflicts
+ *	some other use of the pins, such collisions are handled by the pinmux
+ *	subsystem
+ * @disable: disable a certain muxing selector on a certain position.
+ * @config: custom configuration function for a certain muxing selector -
+ *	this works a bit like an ioctl() and can pass in and return arbitrary
+ *	configuration data to the pinmux. Currently we do not pass in the
+ *	position to this call, refactor if need be
+ * @gpio_request_enable: requests and enables GPIO on a certain pin.
+ *	Implement this only if you can mux every pin individually as GPIO. The
+ *	affected GPIO range is passed along with an offset into that
+ *	specific GPIO range - function selectors and positions are orthogonal
+ *	to this, the core will however make sure the pins do not collide
+ * @dbg_show: optional debugfs display hook that will provide per-device
+ *	info for a certain pin in debugfs
+ */
+struct pinmux_ops {
+	int (*request) (struct pinctrl_dev *pctldev, unsigned offset);
+	int (*free) (struct pinctrl_dev *pctldev, unsigned offset);
+	int (*list_functions) (struct pinctrl_dev *pctldev, unsigned selector);
+	int (*list_positions) (struct pinctrl_dev *pctldev, unsigned selector,
+			       unsigned position);
+	const char *(*get_function_name) (struct pinctrl_dev *pctldev,
+					  unsigned selector);
+	int (*get_function_pins) (struct pinctrl_dev *pctldev,
+				  unsigned selector, unsigned position,
+				  unsigned ** const pins,
+				  unsigned * const num_pins);
+	int (*enable) (struct pinctrl_dev *pctldev, unsigned selector,
+		       unsigned position);
+	void (*disable) (struct pinctrl_dev *pctldev, unsigned selector,
+			 unsigned position);
+	int (*config) (struct pinctrl_dev *pctldev, unsigned selector,
+		       u16 param, unsigned long *data);
+	int (*gpio_request_enable) (struct pinctrl_dev *pctldev,
+				    struct pinctrl_gpio_range *range,
+				    unsigned offset);
+	void (*dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s,
+			  unsigned offset);
+};
+
+/* External interface to pinmux */
+extern int pinmux_request_gpio(unsigned gpio);
+extern void pinmux_free_gpio(unsigned gpio);
+extern struct pinmux *pinmux_get(struct device *dev, const char *name);
+extern void pinmux_put(struct pinmux *pmx);
+extern int pinmux_enable(struct pinmux *pmx);
+extern void pinmux_disable(struct pinmux *pmx);
+extern int pinmux_config(struct pinmux *pmx, u16 param, unsigned long *data);
+
+#else /* !CONFIG_PINMUX */
+
+static inline int pinmux_request_gpio(unsigned gpio)
+{
+	return 0;
+}
+
+static inline void pinmux_free_gpio(unsigned gpio)
+{
+}
+
+static inline struct pinmux *pinmux_get(struct device *dev, const char *name)
+{
+	return NULL;
+}
+
+static inline void pinmux_put(struct pinmux *pmx)
+{
+}
+
+static inline int pinmux_enable(struct pinmux *pmx)
+{
+	return 0;
+}
+
+static inline void pinmux_disable(struct pinmux *pmx)
+{
+}
+
+static inline int pinmux_config(struct pinmux *pmx, u16 param,
+				unsigned long *data)
+{
+	return 0;
+}
+
+#endif /* CONFIG_PINMUX */
+
+#endif /* __LINUX_PINCTRL_PINMUX_H */
-- 
1.7.3.2

^ permalink raw reply related	[flat|nested] 16+ messages in thread

* RE: [PATCH 1/4 v5] drivers: create a pin control subsystem v5
  2011-08-29  9:10 ` Linus Walleij
@ 2011-08-29 21:32   ` Stephen Warren
  -1 siblings, 0 replies; 16+ messages in thread
From: Stephen Warren @ 2011-08-29 21:32 UTC (permalink / raw)
  To: Linus Walleij, linux-kernel, linux-arm-kernel, Grant Likely
  Cc: Lee Jones, Joe Perches, Russell King, Linaro Dev, Sascha Hauer,
	David Brown, Barry Song, Linus Walleij, Grant Likely

Linus Walleij wrote at Monday, August 29, 2011 3:10 AM:
> This creates a subsystem for handling of pin control devices.
> These are devices that control different aspects of package
> pins.
...
> - Defined a "position" for each function, so the pin controller now
>   tracks a function in a certain position, and the pinmux maps define
>   what position you want the function in. (Feedback from Stephen
>   Warren and Sascha Hauer).

My thoughts:

I guess "positions" can be used to represent the muxing capabilities of
Tegra. However, I still don't think this is the right model.

1) There is still a 1:1 correspondence between what a function in the
pinmux core<->driver interface, and the pinmux mapping table. I believe
we need a 1:n correspondence.

HW typically has a set of pins (or pingroups on Tegra), and there's a
register field for each of these that indicates which signal (or set of
signals in the pin group case) are mux'd to it/them. At this level,
setting a pin/pingroup to a particular function isn't all that's required
to use a particular IO controller; you typically need to apply the same
function to many pins/pingroups.

However, the pinmux API defines a function as everything needed to use
a an entire driver/controller.

Now, I do see that the concept of "position" can encompass this, but I
don't think it's entirely right for it to do so:

* "Positions" don't map very well to the HW programming model I assert
above.

* With the current "position" usage, the data structures are not in
"normal form" (normalized), taking a leaf from database technology.

* Normalizing would help the "combinatorial explosion" problem mentioned
before.

i.e. rather than:

driver function/position list:
function@position pins
----------------- ----
mmc0@0            0, 1, 2, 3
mmc0@1            0, 1, 2, 3, 4, 5
mmc0@2            0, 1, 2, 3, 4, 5, 6, 7, 8, 9

core mapping table:
driver  name  function@position
------  ----  -----------------
mmc0    2-bit mmc0@0
mmc0    4-bit mmc0@1
mmc0    8-bit mmc0@2

I'd far rather see:

driver function list:
function
---------
mmc0

driver pin/pingrup list: (names of pins or pingroups):
pingroup
--------
A
B
C

core mapping table:
driver  name  position  function
------  ----  --------  ---------
mmc0    2-bit A         mmc0
mmc0    4-bit A         mmc0
mmc0    4-bit B         mmc0
mmc0    8-bit A         mmc0
mmc0    8-bit B         mmc0
mmc0    8-bit C         mmc0

Note again that I'm assuming above that the driver-supplied function and
pingroup list included all possible options the SoC HW supports, whereas
the mapping table would include just those configurations ever actually
used by the particular board the code is executed upon; from board files
or devicetree data. Hence, a given board would only need rows 0, 1+2, or
3+4+5 from the mapping table shown above, assuming the width of the MMC
port didn't vary at run-time.

2) "Positions" are defined per "function", rather than as a global concept.

This leads to positions having meaningless integer names. As such,
constructing the mapping table will be error-prone; who could remember
that position 0 is a 2-bit bus using a certain set of pins, yet position
1 is an 8-bit bus using a different set of pins? I suppose textual names
might help here. However, by replacing the concept of positions with
multiple explicit entries in the mapping table (as in my example above),
that problem is solved; we name the pins (or pingroups) to which we apply
the driver-level function in each entry, thus it's more self-documenting.

3) It's unclear how well pinmux_config() can be applied.

Some pin parameters might be defined per:

* Pin (probably most systems other than Tegra)
* Pin group (for pull-up/down, tristate on Tegra)
* Drive group (another set of groups of pins on Tegra that arbitrarily
overlap/intersect with the mux pin groups (for drive-strength settings
on Tegra).

For pinmux_config() to work, we'd need some API-level concept in order
to name what pin/group to apply various settings to. Currently, that
naming is an entry from the core mapping table, since pinmux_config()
works on functions returned by pinmux_get(). That doesn't seem right,
since it prevents the API being used for individual pins/pingroups. Even
where say 5 different pins/pingroups are used by the same mapping table
function, there's no reason to believe that their tristate or drive
strength attributes would all be identical; at least input and output
pins or control and data might be programmed differently.


So in summary, I really think the data model should be as below.

Now, I know you've referred to this as a "telephone exchange" model, and
argued that we don't need full telephone exchange support, but even if
that's true (and I'm not convinced), I really don't see the problem in
using it; it seems as simple for everything, simpler for some things,
and allows the API to implement any possible new SoC that might appear
in the future.

Driver-supplied data 1)

Table of functions, each entry containing:
* Name of function

Driver-supplied data 2)

Table of pins, each entry containing:
* Name of pin

Driver-supplied data 3)

Optional table of pingroups, each entry containing:
* Name of pingroup
* List of pins in the pingroup

Or, in more normalized fashion, with multiple rows per pingroup, each
entry containing:
* Name of pingroup
* One pin with in the pingroup

Driver-supplied data 4)

Table of legal functions per pin/pingroup; each entry containing:
* Name of pin or pingroup
* List of functions that can be legally mux'd to the pin or pingroup

Or, in more normalized fashion, with multiple rows per pingroup, each
entry containing:
* Name of pin or pingroup
* One legal function that can be legally mux'd to the pin or pingroup

Board-supplied data 1)

Mapping table, each entry containing:
* Driver name/pointer
* Name of function seen by driver
* Pin/pingroup name to configure
* Name of driver function to apply to pin/pingroup

Note that I assume there may be multiple rows for any combination of the
first two fields in this table, and that all will be operated on by a
single pinmux_get()/pinmux_enable() call.

Some enhancements in the above list of tables over previous times that I've
talked about this:

* Created a separate optional table for a list of pingroups, thus not
burdening SoCs other than Tegra with the pingroup concept.

* Allow either a pin or pingroup name in the driver's "table of legal
functions per pin" and the "mapping table"; core can simply look through
the pingroup table if present, then fall back to looking in pin table,
when determining what a pin/pingroup name means.

* I assume that entries in the "table of pins" or "table of pingroups"
might have no corresponding entries in " Table of legal functions per
pin"; in this case, those pin/pingroup names would only be useful for
pinmux_config() to operate on.


P.S. I'll be on vacation 9/2-9/17. I'm not sure if I'll have any form of
network access during this time or not. You may not see many more pinmux
comments from me during that time.

-- 
nvpublic


^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 1/4 v5] drivers: create a pin control subsystem v5
@ 2011-08-29 21:32   ` Stephen Warren
  0 siblings, 0 replies; 16+ messages in thread
From: Stephen Warren @ 2011-08-29 21:32 UTC (permalink / raw)
  To: linux-arm-kernel

Linus Walleij wrote at Monday, August 29, 2011 3:10 AM:
> This creates a subsystem for handling of pin control devices.
> These are devices that control different aspects of package
> pins.
...
> - Defined a "position" for each function, so the pin controller now
>   tracks a function in a certain position, and the pinmux maps define
>   what position you want the function in. (Feedback from Stephen
>   Warren and Sascha Hauer).

My thoughts:

I guess "positions" can be used to represent the muxing capabilities of
Tegra. However, I still don't think this is the right model.

1) There is still a 1:1 correspondence between what a function in the
pinmux core<->driver interface, and the pinmux mapping table. I believe
we need a 1:n correspondence.

HW typically has a set of pins (or pingroups on Tegra), and there's a
register field for each of these that indicates which signal (or set of
signals in the pin group case) are mux'd to it/them. At this level,
setting a pin/pingroup to a particular function isn't all that's required
to use a particular IO controller; you typically need to apply the same
function to many pins/pingroups.

However, the pinmux API defines a function as everything needed to use
a an entire driver/controller.

Now, I do see that the concept of "position" can encompass this, but I
don't think it's entirely right for it to do so:

* "Positions" don't map very well to the HW programming model I assert
above.

* With the current "position" usage, the data structures are not in
"normal form" (normalized), taking a leaf from database technology.

* Normalizing would help the "combinatorial explosion" problem mentioned
before.

i.e. rather than:

driver function/position list:
function at position pins
----------------- ----
mmc0 at 0            0, 1, 2, 3
mmc0 at 1            0, 1, 2, 3, 4, 5
mmc0 at 2            0, 1, 2, 3, 4, 5, 6, 7, 8, 9

core mapping table:
driver  name  function at position
------  ----  -----------------
mmc0    2-bit mmc0 at 0
mmc0    4-bit mmc0 at 1
mmc0    8-bit mmc0 at 2

I'd far rather see:

driver function list:
function
---------
mmc0

driver pin/pingrup list: (names of pins or pingroups):
pingroup
--------
A
B
C

core mapping table:
driver  name  position  function
------  ----  --------  ---------
mmc0    2-bit A         mmc0
mmc0    4-bit A         mmc0
mmc0    4-bit B         mmc0
mmc0    8-bit A         mmc0
mmc0    8-bit B         mmc0
mmc0    8-bit C         mmc0

Note again that I'm assuming above that the driver-supplied function and
pingroup list included all possible options the SoC HW supports, whereas
the mapping table would include just those configurations ever actually
used by the particular board the code is executed upon; from board files
or devicetree data. Hence, a given board would only need rows 0, 1+2, or
3+4+5 from the mapping table shown above, assuming the width of the MMC
port didn't vary at run-time.

2) "Positions" are defined per "function", rather than as a global concept.

This leads to positions having meaningless integer names. As such,
constructing the mapping table will be error-prone; who could remember
that position 0 is a 2-bit bus using a certain set of pins, yet position
1 is an 8-bit bus using a different set of pins? I suppose textual names
might help here. However, by replacing the concept of positions with
multiple explicit entries in the mapping table (as in my example above),
that problem is solved; we name the pins (or pingroups) to which we apply
the driver-level function in each entry, thus it's more self-documenting.

3) It's unclear how well pinmux_config() can be applied.

Some pin parameters might be defined per:

* Pin (probably most systems other than Tegra)
* Pin group (for pull-up/down, tristate on Tegra)
* Drive group (another set of groups of pins on Tegra that arbitrarily
overlap/intersect with the mux pin groups (for drive-strength settings
on Tegra).

For pinmux_config() to work, we'd need some API-level concept in order
to name what pin/group to apply various settings to. Currently, that
naming is an entry from the core mapping table, since pinmux_config()
works on functions returned by pinmux_get(). That doesn't seem right,
since it prevents the API being used for individual pins/pingroups. Even
where say 5 different pins/pingroups are used by the same mapping table
function, there's no reason to believe that their tristate or drive
strength attributes would all be identical; at least input and output
pins or control and data might be programmed differently.


So in summary, I really think the data model should be as below.

Now, I know you've referred to this as a "telephone exchange" model, and
argued that we don't need full telephone exchange support, but even if
that's true (and I'm not convinced), I really don't see the problem in
using it; it seems as simple for everything, simpler for some things,
and allows the API to implement any possible new SoC that might appear
in the future.

Driver-supplied data 1)

Table of functions, each entry containing:
* Name of function

Driver-supplied data 2)

Table of pins, each entry containing:
* Name of pin

Driver-supplied data 3)

Optional table of pingroups, each entry containing:
* Name of pingroup
* List of pins in the pingroup

Or, in more normalized fashion, with multiple rows per pingroup, each
entry containing:
* Name of pingroup
* One pin with in the pingroup

Driver-supplied data 4)

Table of legal functions per pin/pingroup; each entry containing:
* Name of pin or pingroup
* List of functions that can be legally mux'd to the pin or pingroup

Or, in more normalized fashion, with multiple rows per pingroup, each
entry containing:
* Name of pin or pingroup
* One legal function that can be legally mux'd to the pin or pingroup

Board-supplied data 1)

Mapping table, each entry containing:
* Driver name/pointer
* Name of function seen by driver
* Pin/pingroup name to configure
* Name of driver function to apply to pin/pingroup

Note that I assume there may be multiple rows for any combination of the
first two fields in this table, and that all will be operated on by a
single pinmux_get()/pinmux_enable() call.

Some enhancements in the above list of tables over previous times that I've
talked about this:

* Created a separate optional table for a list of pingroups, thus not
burdening SoCs other than Tegra with the pingroup concept.

* Allow either a pin or pingroup name in the driver's "table of legal
functions per pin" and the "mapping table"; core can simply look through
the pingroup table if present, then fall back to looking in pin table,
when determining what a pin/pingroup name means.

* I assume that entries in the "table of pins" or "table of pingroups"
might have no corresponding entries in " Table of legal functions per
pin"; in this case, those pin/pingroup names would only be useful for
pinmux_config() to operate on.


P.S. I'll be on vacation 9/2-9/17. I'm not sure if I'll have any form of
network access during this time or not. You may not see many more pinmux
comments from me during that time.

-- 
nvpublic

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH 1/4 v5] drivers: create a pin control subsystem v5
  2011-08-29  9:10 ` Linus Walleij
@ 2011-08-30 10:02   ` Jamie Iles
  -1 siblings, 0 replies; 16+ messages in thread
From: Jamie Iles @ 2011-08-30 10:02 UTC (permalink / raw)
  To: Linus Walleij
  Cc: linux-kernel, linux-arm-kernel, Grant Likely, Stephen Warren,
	Russell King, Sascha Hauer, Barry Song, Joe Perches, Linaro Dev,
	David Brown, Lee Jones, Linus Walleij

Hi Linus,

This is looking really great!  A couple of pedantic nits inline, but 
with the gpio ranges support I think this covers all of the bases that 
we need from pin control, so thanks!

Jamie

On Mon, Aug 29, 2011 at 11:10:01AM +0200, Linus Walleij wrote:
[...]
> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> new file mode 100644
> index 0000000..596ce9f
> --- /dev/null
> +++ b/drivers/pinctrl/Makefile
> @@ -0,0 +1,6 @@
> +# generic pinmux support
> +
> +ccflags-$(CONFIG_DEBUG_PINMUX)	+= -DDEBUG
> +
> +obj-$(CONFIG_PINCTRL)		+= core.o
> +obj-$(CONFIG_PINMUX)		+= pinmux.o
> diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
> new file mode 100644
> index 0000000..762e9e8
> --- /dev/null
> +++ b/drivers/pinctrl/core.c
> @@ -0,0 +1,539 @@
> +/*
> + * Core driver for the pin control subsystem
> + *
> + * Copyright (C) 2011 ST-Ericsson SA
> + * Written on behalf of Linaro for ST-Ericsson
> + * Based on bits of regulator core, gpio core and clk core
> + *
> + * Author: Linus Walleij <linus.walleij@linaro.org>
> + *
> + * License terms: GNU General Public License (GPL) version 2
> + */
> +#define pr_fmt(fmt) "pinctrl core: " fmt
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/device.h>
> +#include <linux/slab.h>
> +#include <linux/radix-tree.h>
> +#include <linux/err.h>
> +#include <linux/list.h>
> +#include <linux/mutex.h>
> +#include <linux/spinlock.h>
> +#include <linux/sysfs.h>
> +#include <linux/debugfs.h>
> +#include <linux/seq_file.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/pinctrl/machine.h>
> +#include "core.h"
> +#include "pinmux.h"
> +
> +/* Global list of pin control devices */
> +static DEFINE_MUTEX(pinctrldev_list_mutex);
> +static LIST_HEAD(pinctrldev_list);
> +
> +/* sysfs interaction */
> +static ssize_t pinctrl_name_show(struct device *dev,
> +				struct device_attribute *attr, char *buf)
> +{
> +	struct pinctrl_dev *pctldev = dev_get_drvdata(dev);

As you have a struct device in pctldev, you should be able to do:

#define to_pinctrl_dev(__dev) \
	container_of(__dev, struct pinctrl_dev, dev)

struct pinctrl_dev *pctldev = to_pinctrl_dev(dev);

then you don't need to use the driver data.

[...]
> +static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
> +{
> +	static struct dentry *device_root;

Does device_root need to be static?

> +
> +	device_root = debugfs_create_dir(dev_name(&pctldev->dev),
> +					 debugfs_root);
> +	if (IS_ERR(device_root) || !device_root) {
> +		pr_warn("failed to create debugfs directory for %s\n",
> +			dev_name(&pctldev->dev));
> +		return;
> +	}
> +	debugfs_create_file("pins", S_IFREG | S_IRUGO,
> +			    device_root, pctldev, &pinctrl_pins_ops);
> +	debugfs_create_file("gpio-ranges", S_IFREG | S_IRUGO,
> +			    device_root, pctldev, &pinctrl_gpioranges_ops);
> +	pinmux_init_device_debugfs(device_root, pctldev);
> +}
> +
> +static void pinctrl_init_debugfs(void)
> +{
> +	debugfs_root = debugfs_create_dir("pinctrl", NULL);
> +	if (IS_ERR(debugfs_root) || !debugfs_root) {

IS_ERR_OR_NULL()?

> +		pr_warn("failed to create debugfs directory\n");
> +		debugfs_root = NULL;
> +		return;
> +	}
> +
> +	debugfs_create_file("pinctrl-devices", S_IFREG | S_IRUGO,
> +			    debugfs_root, NULL, &pinctrl_devices_ops);
> +	pinmux_init_debugfs(debugfs_root);
> +}
> +
> +#else /* CONFIG_DEBUG_FS */
> +
> +static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
> +{
> +}
> +
> +static void pinctrl_init_debugfs(void)
> +{
> +}
> +
> +#endif
> +
> +/**
> + * pinctrl_register() - register a pin controller device
> + * @pctldesc: descriptor for this pin controller
> + * @dev: parent device for this pin controller
> + * @driver_data: private pin controller data for this pin controller
> + */
> +struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
> +				    struct device *dev, void *driver_data)
> +{
> +	static atomic_t pinmux_no = ATOMIC_INIT(0);
> +	struct pinctrl_dev *pctldev;
> +	int ret;
> +
> +	if (pctldesc == NULL)
> +		return ERR_PTR(-EINVAL);
> +	if (pctldesc->name == NULL)
> +		return ERR_PTR(-EINVAL);
> +
> +	/* If we're implementing pinmuxing, check the ops for sanity */
> +	if (pctldesc->pmxops) {
> +		ret = pinmux_check_ops(pctldesc->pmxops);
> +		if (ret)
> +			return ERR_PTR(ret);
> +	}
> +
> +	pctldev = kzalloc(sizeof(struct pinctrl_dev), GFP_KERNEL);
> +	if (pctldev == NULL)
> +		return ERR_PTR(-ENOMEM);
> +
> +	/* Initialize pin control device struct */
> +	pctldev->owner = pctldesc->owner;
> +	pctldev->desc = pctldesc;
> +	pctldev->driver_data = driver_data;
> +	INIT_RADIX_TREE(&pctldev->pin_desc_tree, GFP_KERNEL);
> +	spin_lock_init(&pctldev->pin_desc_tree_lock);
> +	INIT_LIST_HEAD(&pctldev->gpio_ranges);
> +	spin_lock_init(&pctldev->gpio_ranges_lock);
> +
> +	/* Register device with sysfs */
> +	pctldev->dev.parent = dev;
> +	pctldev->dev.bus = &pinctrl_bus;
> +	pctldev->dev.type = &pinctrl_type;
> +	dev_set_name(&pctldev->dev, "pinctrl.%d",
> +		     atomic_inc_return(&pinmux_no) - 1);
> +	ret = device_register(&pctldev->dev);
> +	if (ret != 0) {
> +		pr_err("error in device registration\n");
> +		put_device(&pctldev->dev);
> +		kfree(pctldev);

I don't think you need the kfree() here as it should get called in the 
devices release method.

> +		goto out_err;
> +	}
> +	dev_set_drvdata(&pctldev->dev, pctldev);
> +
> +	/* Register all the pins */
> +	pr_debug("try to register %d pins on %s...\n",
> +		 pctldesc->npins, pctldesc->name);
> +	ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins);
> +	if (ret) {
> +		pr_err("error during pin registration\n");
> +		pinctrl_free_pindescs(pctldev, pctldesc->pins,
> +				      pctldesc->npins);
> +		goto out_err;
> +	}
> +
> +	pinctrl_init_device_debugfs(pctldev);
> +	mutex_lock(&pinctrldev_list_mutex);
> +	list_add(&pctldev->node, &pinctrldev_list);
> +	mutex_unlock(&pinctrldev_list_mutex);
> +	return pctldev;
> +
> +out_err:
> +	put_device(&pctldev->dev);
> +	kfree(pctldev);

I think this needs to be a device_unregister() rather than put device, 
and the kfree() can be dropped.

Possibly also do a dev_set_drvdata(&pctldev->dev, NULL) here too?

> diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
> new file mode 100644
> index 0000000..310d344
> --- /dev/null
> +++ b/drivers/pinctrl/pinmux.c
> @@ -0,0 +1,811 @@
> +/*
> + * Core driver for the pin muxing portions of the pin control subsystem
> + *
> + * Copyright (C) 2011 ST-Ericsson SA
> + * Written on behalf of Linaro for ST-Ericsson
> + * Based on bits of regulator core, gpio core and clk core
> + *
> + * Author: Linus Walleij <linus.walleij@linaro.org>
> + *
> + * License terms: GNU General Public License (GPL) version 2
> + */
> +#define pr_fmt(fmt) "pinmux core: " fmt
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/device.h>
> +#include <linux/slab.h>
> +#include <linux/radix-tree.h>
> +#include <linux/err.h>
> +#include <linux/list.h>
> +#include <linux/mutex.h>
> +#include <linux/spinlock.h>
> +#include <linux/sysfs.h>
> +#include <linux/debugfs.h>
> +#include <linux/seq_file.h>
> +#include <linux/pinctrl/machine.h>
> +#include <linux/pinctrl/pinmux.h>
> +#include "core.h"
> +
> +/* Global list of pinmuxes */
> +static DEFINE_MUTEX(pinmux_list_mutex);
> +static LIST_HEAD(pinmux_list);
> +
> +/**
> + * struct pinmux - per-device pinmux state holder
> + * @node: global list node - only for internal use
> + * @dev: the device using this pinmux
> + * @map: corresponding pinmux map active for this pinmux setting
> + * @usecount: the number of active users of this mux setting, used to keep
> + *	track of nested use cases
> + * @pins: an array of discrete physical pins used in this mapping, taken
> + *	from the global pin enumeration space (copied from pinmux map)
> + * @num_pins: the number of pins in this mapping array, i.e. the number of
> + *	elements in .pins so we can iterate over that array (copied from
> + *	pinmux map)
> + * @pctldev: pin control device handling this pinmux
> + * @pmxdev_selector: the function selector for the pinmux device handling
> + *	this pinmux
> + * @pmxdev_position: the function position for the pinmux device and
> + *	selector handling this pinmux
> + * @mutex: a lock for the pinmux state holder
> + */
> +struct pinmux {
> +	struct list_head node;
> +	struct device *dev;
> +	struct pinmux_map const *map;
> +	unsigned usecount;
> +	struct pinctrl_dev *pctldev;
> +	unsigned pmxdev_selector;
> +	unsigned pmxdev_position;
> +	struct mutex mutex;
> +};
> +
> +/**
> + * pin_request() - request a single pin to be muxed in, typically for GPIO
> + * @pin: the pin number in the global pin space
> + * @function: a functional name to give to this pin, passed to the driver
> + *	so it knows what function to mux in, e.g. the string "gpioNN"
> + *	means that you want to mux in the pin for use as GPIO number NN
> + * @gpio: if this request concerns a single GPIO pin
> + * @gpio_range: the range matching the GPIO pin if this is a request for a
> + *	single GPIO pin
> + */
> +static int pin_request(struct pinctrl_dev *pctldev,
> +		       int pin, const char *function, bool gpio,
> +		       struct pinctrl_gpio_range *gpio_range)

@gpio_range is only valid if @gpio == true, so we could drop @gpio and 
only do gpio_request_enable if gpio_range != NULL?  At least that way we 
can't call gpio_request_enable with a NULL gpio_range (which I don't 
think is valid?).

[...]
> +/**
> + * pinmux_config() - configure a certain pinmux setting
> + * @pmx: the pinmux setting to configure
> + * @param: the parameter to configure
> + * @data: extra data to be passed to the configuration, also works as a
> + *	pointer to data returned from the function on success
> + */
> +int pinmux_config(struct pinmux *pmx, u16 param, unsigned long *data)
> +{
> +	struct pinctrl_dev *pctldev;
> +	const struct pinmux_ops *ops;
> +	int ret = 0;
> +
> +	if (pmx == NULL)
> +		return -ENODEV;
> +
> +	pctldev = pmx->pctldev;
> +	ops = pctldev->desc->pmxops;
> +
> +	/* This operation is not mandatory to implement */
> +	if (ops->config) {
> +		mutex_lock(&pmx->mutex);
> +		ret = ops->config(pctldev, pmx->pmxdev_selector, param, data);
> +		mutex_unlock(&pmx->mutex);
> +	}
> +
> +	return 0;

Shouldn't this return ret from ops->config()?

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 1/4 v5] drivers: create a pin control subsystem v5
@ 2011-08-30 10:02   ` Jamie Iles
  0 siblings, 0 replies; 16+ messages in thread
From: Jamie Iles @ 2011-08-30 10:02 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Linus,

This is looking really great!  A couple of pedantic nits inline, but 
with the gpio ranges support I think this covers all of the bases that 
we need from pin control, so thanks!

Jamie

On Mon, Aug 29, 2011 at 11:10:01AM +0200, Linus Walleij wrote:
[...]
> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> new file mode 100644
> index 0000000..596ce9f
> --- /dev/null
> +++ b/drivers/pinctrl/Makefile
> @@ -0,0 +1,6 @@
> +# generic pinmux support
> +
> +ccflags-$(CONFIG_DEBUG_PINMUX)	+= -DDEBUG
> +
> +obj-$(CONFIG_PINCTRL)		+= core.o
> +obj-$(CONFIG_PINMUX)		+= pinmux.o
> diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
> new file mode 100644
> index 0000000..762e9e8
> --- /dev/null
> +++ b/drivers/pinctrl/core.c
> @@ -0,0 +1,539 @@
> +/*
> + * Core driver for the pin control subsystem
> + *
> + * Copyright (C) 2011 ST-Ericsson SA
> + * Written on behalf of Linaro for ST-Ericsson
> + * Based on bits of regulator core, gpio core and clk core
> + *
> + * Author: Linus Walleij <linus.walleij@linaro.org>
> + *
> + * License terms: GNU General Public License (GPL) version 2
> + */
> +#define pr_fmt(fmt) "pinctrl core: " fmt
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/device.h>
> +#include <linux/slab.h>
> +#include <linux/radix-tree.h>
> +#include <linux/err.h>
> +#include <linux/list.h>
> +#include <linux/mutex.h>
> +#include <linux/spinlock.h>
> +#include <linux/sysfs.h>
> +#include <linux/debugfs.h>
> +#include <linux/seq_file.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/pinctrl/machine.h>
> +#include "core.h"
> +#include "pinmux.h"
> +
> +/* Global list of pin control devices */
> +static DEFINE_MUTEX(pinctrldev_list_mutex);
> +static LIST_HEAD(pinctrldev_list);
> +
> +/* sysfs interaction */
> +static ssize_t pinctrl_name_show(struct device *dev,
> +				struct device_attribute *attr, char *buf)
> +{
> +	struct pinctrl_dev *pctldev = dev_get_drvdata(dev);

As you have a struct device in pctldev, you should be able to do:

#define to_pinctrl_dev(__dev) \
	container_of(__dev, struct pinctrl_dev, dev)

struct pinctrl_dev *pctldev = to_pinctrl_dev(dev);

then you don't need to use the driver data.

[...]
> +static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
> +{
> +	static struct dentry *device_root;

Does device_root need to be static?

> +
> +	device_root = debugfs_create_dir(dev_name(&pctldev->dev),
> +					 debugfs_root);
> +	if (IS_ERR(device_root) || !device_root) {
> +		pr_warn("failed to create debugfs directory for %s\n",
> +			dev_name(&pctldev->dev));
> +		return;
> +	}
> +	debugfs_create_file("pins", S_IFREG | S_IRUGO,
> +			    device_root, pctldev, &pinctrl_pins_ops);
> +	debugfs_create_file("gpio-ranges", S_IFREG | S_IRUGO,
> +			    device_root, pctldev, &pinctrl_gpioranges_ops);
> +	pinmux_init_device_debugfs(device_root, pctldev);
> +}
> +
> +static void pinctrl_init_debugfs(void)
> +{
> +	debugfs_root = debugfs_create_dir("pinctrl", NULL);
> +	if (IS_ERR(debugfs_root) || !debugfs_root) {

IS_ERR_OR_NULL()?

> +		pr_warn("failed to create debugfs directory\n");
> +		debugfs_root = NULL;
> +		return;
> +	}
> +
> +	debugfs_create_file("pinctrl-devices", S_IFREG | S_IRUGO,
> +			    debugfs_root, NULL, &pinctrl_devices_ops);
> +	pinmux_init_debugfs(debugfs_root);
> +}
> +
> +#else /* CONFIG_DEBUG_FS */
> +
> +static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev)
> +{
> +}
> +
> +static void pinctrl_init_debugfs(void)
> +{
> +}
> +
> +#endif
> +
> +/**
> + * pinctrl_register() - register a pin controller device
> + * @pctldesc: descriptor for this pin controller
> + * @dev: parent device for this pin controller
> + * @driver_data: private pin controller data for this pin controller
> + */
> +struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
> +				    struct device *dev, void *driver_data)
> +{
> +	static atomic_t pinmux_no = ATOMIC_INIT(0);
> +	struct pinctrl_dev *pctldev;
> +	int ret;
> +
> +	if (pctldesc == NULL)
> +		return ERR_PTR(-EINVAL);
> +	if (pctldesc->name == NULL)
> +		return ERR_PTR(-EINVAL);
> +
> +	/* If we're implementing pinmuxing, check the ops for sanity */
> +	if (pctldesc->pmxops) {
> +		ret = pinmux_check_ops(pctldesc->pmxops);
> +		if (ret)
> +			return ERR_PTR(ret);
> +	}
> +
> +	pctldev = kzalloc(sizeof(struct pinctrl_dev), GFP_KERNEL);
> +	if (pctldev == NULL)
> +		return ERR_PTR(-ENOMEM);
> +
> +	/* Initialize pin control device struct */
> +	pctldev->owner = pctldesc->owner;
> +	pctldev->desc = pctldesc;
> +	pctldev->driver_data = driver_data;
> +	INIT_RADIX_TREE(&pctldev->pin_desc_tree, GFP_KERNEL);
> +	spin_lock_init(&pctldev->pin_desc_tree_lock);
> +	INIT_LIST_HEAD(&pctldev->gpio_ranges);
> +	spin_lock_init(&pctldev->gpio_ranges_lock);
> +
> +	/* Register device with sysfs */
> +	pctldev->dev.parent = dev;
> +	pctldev->dev.bus = &pinctrl_bus;
> +	pctldev->dev.type = &pinctrl_type;
> +	dev_set_name(&pctldev->dev, "pinctrl.%d",
> +		     atomic_inc_return(&pinmux_no) - 1);
> +	ret = device_register(&pctldev->dev);
> +	if (ret != 0) {
> +		pr_err("error in device registration\n");
> +		put_device(&pctldev->dev);
> +		kfree(pctldev);

I don't think you need the kfree() here as it should get called in the 
devices release method.

> +		goto out_err;
> +	}
> +	dev_set_drvdata(&pctldev->dev, pctldev);
> +
> +	/* Register all the pins */
> +	pr_debug("try to register %d pins on %s...\n",
> +		 pctldesc->npins, pctldesc->name);
> +	ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins);
> +	if (ret) {
> +		pr_err("error during pin registration\n");
> +		pinctrl_free_pindescs(pctldev, pctldesc->pins,
> +				      pctldesc->npins);
> +		goto out_err;
> +	}
> +
> +	pinctrl_init_device_debugfs(pctldev);
> +	mutex_lock(&pinctrldev_list_mutex);
> +	list_add(&pctldev->node, &pinctrldev_list);
> +	mutex_unlock(&pinctrldev_list_mutex);
> +	return pctldev;
> +
> +out_err:
> +	put_device(&pctldev->dev);
> +	kfree(pctldev);

I think this needs to be a device_unregister() rather than put device, 
and the kfree() can be dropped.

Possibly also do a dev_set_drvdata(&pctldev->dev, NULL) here too?

> diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
> new file mode 100644
> index 0000000..310d344
> --- /dev/null
> +++ b/drivers/pinctrl/pinmux.c
> @@ -0,0 +1,811 @@
> +/*
> + * Core driver for the pin muxing portions of the pin control subsystem
> + *
> + * Copyright (C) 2011 ST-Ericsson SA
> + * Written on behalf of Linaro for ST-Ericsson
> + * Based on bits of regulator core, gpio core and clk core
> + *
> + * Author: Linus Walleij <linus.walleij@linaro.org>
> + *
> + * License terms: GNU General Public License (GPL) version 2
> + */
> +#define pr_fmt(fmt) "pinmux core: " fmt
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/device.h>
> +#include <linux/slab.h>
> +#include <linux/radix-tree.h>
> +#include <linux/err.h>
> +#include <linux/list.h>
> +#include <linux/mutex.h>
> +#include <linux/spinlock.h>
> +#include <linux/sysfs.h>
> +#include <linux/debugfs.h>
> +#include <linux/seq_file.h>
> +#include <linux/pinctrl/machine.h>
> +#include <linux/pinctrl/pinmux.h>
> +#include "core.h"
> +
> +/* Global list of pinmuxes */
> +static DEFINE_MUTEX(pinmux_list_mutex);
> +static LIST_HEAD(pinmux_list);
> +
> +/**
> + * struct pinmux - per-device pinmux state holder
> + * @node: global list node - only for internal use
> + * @dev: the device using this pinmux
> + * @map: corresponding pinmux map active for this pinmux setting
> + * @usecount: the number of active users of this mux setting, used to keep
> + *	track of nested use cases
> + * @pins: an array of discrete physical pins used in this mapping, taken
> + *	from the global pin enumeration space (copied from pinmux map)
> + * @num_pins: the number of pins in this mapping array, i.e. the number of
> + *	elements in .pins so we can iterate over that array (copied from
> + *	pinmux map)
> + * @pctldev: pin control device handling this pinmux
> + * @pmxdev_selector: the function selector for the pinmux device handling
> + *	this pinmux
> + * @pmxdev_position: the function position for the pinmux device and
> + *	selector handling this pinmux
> + * @mutex: a lock for the pinmux state holder
> + */
> +struct pinmux {
> +	struct list_head node;
> +	struct device *dev;
> +	struct pinmux_map const *map;
> +	unsigned usecount;
> +	struct pinctrl_dev *pctldev;
> +	unsigned pmxdev_selector;
> +	unsigned pmxdev_position;
> +	struct mutex mutex;
> +};
> +
> +/**
> + * pin_request() - request a single pin to be muxed in, typically for GPIO
> + * @pin: the pin number in the global pin space
> + * @function: a functional name to give to this pin, passed to the driver
> + *	so it knows what function to mux in, e.g. the string "gpioNN"
> + *	means that you want to mux in the pin for use as GPIO number NN
> + * @gpio: if this request concerns a single GPIO pin
> + * @gpio_range: the range matching the GPIO pin if this is a request for a
> + *	single GPIO pin
> + */
> +static int pin_request(struct pinctrl_dev *pctldev,
> +		       int pin, const char *function, bool gpio,
> +		       struct pinctrl_gpio_range *gpio_range)

@gpio_range is only valid if @gpio == true, so we could drop @gpio and 
only do gpio_request_enable if gpio_range != NULL?  At least that way we 
can't call gpio_request_enable with a NULL gpio_range (which I don't 
think is valid?).

[...]
> +/**
> + * pinmux_config() - configure a certain pinmux setting
> + * @pmx: the pinmux setting to configure
> + * @param: the parameter to configure
> + * @data: extra data to be passed to the configuration, also works as a
> + *	pointer to data returned from the function on success
> + */
> +int pinmux_config(struct pinmux *pmx, u16 param, unsigned long *data)
> +{
> +	struct pinctrl_dev *pctldev;
> +	const struct pinmux_ops *ops;
> +	int ret = 0;
> +
> +	if (pmx == NULL)
> +		return -ENODEV;
> +
> +	pctldev = pmx->pctldev;
> +	ops = pctldev->desc->pmxops;
> +
> +	/* This operation is not mandatory to implement */
> +	if (ops->config) {
> +		mutex_lock(&pmx->mutex);
> +		ret = ops->config(pctldev, pmx->pmxdev_selector, param, data);
> +		mutex_unlock(&pmx->mutex);
> +	}
> +
> +	return 0;

Shouldn't this return ret from ops->config()?

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH 1/4 v5] drivers: create a pin control subsystem v5
  2011-08-29  9:10 ` Linus Walleij
@ 2011-08-31  9:45   ` Barry Song
  -1 siblings, 0 replies; 16+ messages in thread
From: Barry Song @ 2011-08-31  9:45 UTC (permalink / raw)
  To: Linus Walleij
  Cc: linux-kernel, linux-arm-kernel, Grant Likely, Stephen Warren,
	Lee Jones, Joe Perches, Russell King, Linaro Dev, Sascha Hauer,
	David Brown, Linus Walleij

> +Interaction with the GPIO subsystem
> +===================================
> +
> +The GPIO drivers may want to perform operations of various types on the
> same
> +physical pins that are also registered as GPIO pins.
> +
> +Since the pin controller subsystem have its pinspace local to the pin
> +controller we need a mapping so that the pin control subsystem can figure
> out
> +which pin controller handles control of a certain GPIO pin. Since a single
> +pin controller may be muxing several GPIO ranges (typically SoCs that have
> +one set of pins but internally several GPIO silicon blocks, each modeled as
> +a struct gpio_chip) any number of GPIO ranges can be added to a pin
> controller
> +instance like this:
> +
> +struct gpio_chip chip_a;
> +struct gpio_chip chip_b;
> +
> +static struct pinctrl_gpio_range gpio_range_a = {
> +	.name = "chip a",
> +	.id = 0,
> +	.base = 32,
> +	.npins = 16,
> +	.gc = &chip_a;
> +};
> +
> +static struct pinctrl_gpio_range gpio_range_a = {
> +	.name = "chip b",
> +	.id = 0,
> +	.base = 48,
> +	.npins = 8,
> +	.gc = &chip_b;
> +};
> +
> +
> +{
> +	struct pinctrl_dev *pctl;
> +	...
> +	pinctrl_add_gpio_range(pctl, &gpio_range_a);
> +	pinctrl_add_gpio_range(pctl, &gpio_range_b);

people might like a pinctrl_add_gpio_range*s* too.

-barry

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 1/4 v5] drivers: create a pin control subsystem v5
@ 2011-08-31  9:45   ` Barry Song
  0 siblings, 0 replies; 16+ messages in thread
From: Barry Song @ 2011-08-31  9:45 UTC (permalink / raw)
  To: linux-arm-kernel

> +Interaction with the GPIO subsystem
> +===================================
> +
> +The GPIO drivers may want to perform operations of various types on the
> same
> +physical pins that are also registered as GPIO pins.
> +
> +Since the pin controller subsystem have its pinspace local to the pin
> +controller we need a mapping so that the pin control subsystem can figure
> out
> +which pin controller handles control of a certain GPIO pin. Since a single
> +pin controller may be muxing several GPIO ranges (typically SoCs that have
> +one set of pins but internally several GPIO silicon blocks, each modeled as
> +a struct gpio_chip) any number of GPIO ranges can be added to a pin
> controller
> +instance like this:
> +
> +struct gpio_chip chip_a;
> +struct gpio_chip chip_b;
> +
> +static struct pinctrl_gpio_range gpio_range_a = {
> +	.name = "chip a",
> +	.id = 0,
> +	.base = 32,
> +	.npins = 16,
> +	.gc = &chip_a;
> +};
> +
> +static struct pinctrl_gpio_range gpio_range_a = {
> +	.name = "chip b",
> +	.id = 0,
> +	.base = 48,
> +	.npins = 8,
> +	.gc = &chip_b;
> +};
> +
> +
> +{
> +	struct pinctrl_dev *pctl;
> +	...
> +	pinctrl_add_gpio_range(pctl, &gpio_range_a);
> +	pinctrl_add_gpio_range(pctl, &gpio_range_b);

people might like a pinctrl_add_gpio_range*s* too.

-barry

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH 1/4 v5] drivers: create a pin control subsystem v5
  2011-08-29 21:32   ` Stephen Warren
@ 2011-09-01  8:59     ` Linus Walleij
  -1 siblings, 0 replies; 16+ messages in thread
From: Linus Walleij @ 2011-09-01  8:59 UTC (permalink / raw)
  To: Stephen Warren
  Cc: Linus Walleij, linux-kernel, linux-arm-kernel, Grant Likely,
	Lee Jones, Joe Perches, Russell King, Linaro Dev, Sascha Hauer,
	David Brown, Barry Song

On Mon, Aug 29, 2011 at 11:32 PM, Stephen Warren <swarren@nvidia.com> wrote:

> 1) There is still a 1:1 correspondence between what a function in the
> pinmux core<->driver interface, and the pinmux mapping table. I believe
> we need a 1:n correspondence.

Yes I know that, but the positions were never
about solving that issue.

What you are requesting (just like earlier) is
that one requlator_get() should be able to
retrieve multiple map entries and enable/disable
them.

I 've been working on that, it's just a bit tricky.

> i.e. rather than:
>
> driver function/position list:
> function@position pins
> ----------------- ----
> mmc0@0            0, 1, 2, 3
> mmc0@1            0, 1, 2, 3, 4, 5
> mmc0@2            0, 1, 2, 3, 4, 5, 6, 7, 8, 9
>
> core mapping table:
> driver  name  function@position
> ------  ----  -----------------
> mmc0    2-bit mmc0@0
> mmc0    4-bit mmc0@1
> mmc0    8-bit mmc0@2

There is no combined function@postion,
these are two were separate fields in the
struct pinmux_map.

What I wanted to express was the noted feature of the
hardware to have the same function in several positions
simply, believing it would be more intuitive.

But since the positions does not seem to be the
answer to the question I've just ripped them out
again. It is now (v6) replaced with a pin group
concept which I hope is closer to what you want.

> I'd far rather see:
>
> driver function list:
> function
> ---------
> mmc0

Can now be found in
<debugfs>/pinctrl/pinctrl.0/pinmux-functions

It will now show the list of different groups that the
function can use.

So a function has 1..* groups associated with it.

Example from U300:

root@ME:/debug/pinctrl/pinctrl.0 cat pinmux-functions
function: power, groups = [ powergrp ]
function: uart0, groups = [ uart0grp ]
function: mmc0, groups = [ mmc0grp ]
function: spi0, groups = [ spi0grp ]

Just one group per function here but can be many.

> driver pin/pingrup list: (names of pins or pingroups):
> pingroup
> --------
> A
> B
> C

Can now be found in
<debugfs>/pinctrl/pinctrl.0/pingroups

Example from U300:

root@ME:/debug/pinctrl/pinctrl.0 cat pingroups
registered pin groups:
group: powergrp, pins = [ 0 1 3 31 46 47 49 50 61 62 63 64 78 79 80 81
92 93 94 95 101 102 103 104 115 116 117 118 130 131 132 133 145 146
147 148 159 160 172 173 174 175 187 188 189 190 201 202 211 212 213
214 215 218 223 224 225 226 231 232 237 238 239 240 245 246 251 252
256 257 258 259 264 265 270 271 276 277 278 279 284 285 290 291 295
296 299 300 301 302 303 309 310 311 312 319 320 321 322 329 330 331
332 341 342 343 344 358 359 360 361 372 373 374 375 388 389 390 391
402 403 404 405 413 414 415 416 427 428 429 430 443 444 455 456 457
458 ]
group: uart0grp, pins = [ 134 135 136 137 ]
group: mmc0grp, pins = [ 166 167 168 169 170 171 176 177 ]
group: spi0grp, pins = [ 420 421 422 423 424 425 ]

Notice that it's not prefixed with the string
"pinmux-", it's just a number of groups of pins,
which can be used for anything, one usecase is
muxing. So I now have an abstract pin group
concept and the pinmux function has atleast
one such group associated.

> core mapping table:
> driver  name  position  function
> ------  ----  --------  ---------
> mmc0    2-bit A         mmc0
> mmc0    4-bit A         mmc0
> mmc0    4-bit B         mmc0
> mmc0    8-bit A         mmc0
> mmc0    8-bit B         mmc0
> mmc0    8-bit C         mmc0

Now the struct pinmux_map entries look
like this:

struct pinmux_map {
        const char *name;
        struct device *ctrl_dev;
        const char *ctrl_dev_name;
        const char *function;
        const char *group;
        struct device *dev;
        const char *dev_name;
};

Correspondance per above would be:

dev_name, name, group, function

function and group names shall match what is
presented from the pin controller driver.

You can thing of this as SQL:

SELECT ctrl_dev_name,
TOP 1
  FROM MAPS
  WHERE dev_name = device_name
  AND ctrl_dev_name = ctrl_dev_name
  AND function = function
  AND group = group

(the struct device * entries are for the shiny world
where we can access all struct device * at boot or
so)

Then it's the first point about multiple maps
per mux again I guess, when you write like this:

> mmc0    8-bit A         mmc0
> mmc0    8-bit B         mmc0
> mmc0    8-bit C         mmc0

I assume you mean that semantically this shall
be a 1..* relation, so that if I say:

pmx = pinmux_get(&dev, "8-bit");

Then all pins in the union {A, B, C} shall be
allocated and enabled/disabled simultaneously.

so it'd be like the database equivalent:

I am working on that...

> Note again that I'm assuming above that the driver-supplied function and
> pingroup list included all possible options the SoC HW supports, whereas
> the mapping table would include just those configurations ever actually
> used by the particular board the code is executed upon; from board files
> or devicetree data.

This is my current working assumption also.

The pinmux driver should nominally expose all functions in all
possible positions.

Then the pinmux_map maps usually one but sometimes
more of these {function, position} tuples to the device.

And, you also request the currently not implemented
extenstion that a mux can match multiple map entries.

I'll fix.

> Hence, a given board would only need rows 0, 1+2, or
> 3+4+5 from the mapping table shown above, assuming the width of the MMC
> port didn't vary at run-time.

OK we're on the same page I think. If I fix this, then
you're happy?

> 2) "Positions" are defined per "function", rather than as a global concept.
>
> This leads to positions having meaningless integer names. As such,
> constructing the mapping table will be error-prone; who could remember
> that position 0 is a 2-bit bus using a certain set of pins, yet position
> 1 is an 8-bit bus using a different set of pins? I suppose textual names
> might help here. However, by replacing the concept of positions with
> multiple explicit entries in the mapping table (as in my example above),
> that problem is solved; we name the pins (or pingroups) to which we apply
> the driver-level function in each entry, thus it's more self-documenting.

Again I can replace position integers with strings if that is what
you want?

> 3) It's unclear how well pinmux_config() can be applied.

Agee. I will delete this function from pinmux_ops since
it seems it will only be abused for things that are
unrelated to muxing. No shoehorning...

> Some pin parameters might be defined per:
>
> * Pin (probably most systems other than Tegra)
> * Pin group (for pull-up/down, tristate on Tegra)
> * Drive group (another set of groups of pins on Tegra that arbitrarily
> overlap/intersect with the mux pin groups (for drive-strength settings
> on Tegra).

Since these things are unrelated to muxing I prefer that
we add that as a separate set of ops in struct pinctrl_device.

The driver can very well reuse the same groups internally,
nothing prevents that.

I am not intending to address the issue of pin bias,
driver strength, load capacitance, schmitt-trigger input
etc etc etc in this first iteration of the pin control subsystem,
what I want is to get the infrastructure and pin muxing
into the kernel then extend it with other pin control.

I'm trying to avoid excess upfront design.

Do you think these features are needed from day 1
to be of any use for Tegra?

> For pinmux_config() to work, we'd need some API-level concept in order
> to name what pin/group to apply various settings to.
>
> Currently, that
> naming is an entry from the core mapping table, since pinmux_config()
> works on functions returned by pinmux_get(). That doesn't seem right,
> since it prevents the API being used for individual pins/pingroups. Even
> where say 5 different pins/pingroups are used by the same mapping table
> function, there's no reason to believe that their tristate or drive
> strength attributes would all be identical; at least input and output
> pins or control and data might be programmed differently.

Let's avoid trying to solve the things that are not really pinmuxing
with any concept from <linux/pinmux.h>, and let's have separation
of concerns.

I'll kill the (*config) callback for now.

> So in summary, I really think the data model should be as below.
>
> Driver-supplied data 1)
>
> Table of functions, each entry containing:
> * Name of function

This we have I think.

> Driver-supplied data 2)
>
> Table of pins, each entry containing:
> * Name of pin

This we have too I think.

> Driver-supplied data 3)
>
> Optional table of pingroups, each entry containing:
> * Name of pingroup
> * List of pins in the pingroup

OK introduced this as a generic concept in the
v6 patch set.

> Or, in more normalized fashion, with multiple rows per pingroup, each
> entry containing:
> * Name of pingroup
> * One pin with in the pingroup

I don't get this "one pin within the the pingroup"
what if the same pin is part of multiple groups?

The first suggestion seems more solid to me.

> Driver-supplied data 4)
>
> Table of legal functions per pin/pingroup; each entry containing:
> * Name of pin or pingroup

OK I have this now, e.g. inspect the file
<debugfs>/pinctrl.0/groups

> * List of functions that can be legally mux'd to the pin or pingroup
>
> Or, in more normalized fashion, with multiple rows per pingroup, each
> entry containing:
> * Name of pin or pingroup
> * One legal function that can be legally mux'd to the pin or pingroup
>
> Board-supplied data 1)
>
> Mapping table, each entry containing:
> * Driver name/pointer
> * Name of function seen by driver
> * Pin/pingroup name to configure
> * Name of driver function to apply to pin/pingroup
>
> Note that I assume there may be multiple rows for any combination of the
> first two fields in this table, and that all will be operated on by a
> single pinmux_get()/pinmux_enable() call.
>
> Some enhancements in the above list of tables over previous times that I've
> talked about this:
>
> * Created a separate optional table for a list of pingroups, thus not
> burdening SoCs other than Tegra with the pingroup concept.
>
> * Allow either a pin or pingroup name in the driver's "table of legal
> functions per pin" and the "mapping table"; core can simply look through
> the pingroup table if present, then fall back to looking in pin table,
> when determining what a pin/pingroup name means.
>
> * I assume that entries in the "table of pins" or "table of pingroups"
> might have no corresponding entries in " Table of legal functions per
> pin"; in this case, those pin/pingroup names would only be useful for
> pinmux_config() to operate on.
>
>
> P.S. I'll be on vacation 9/2-9/17. I'm not sure if I'll have any form of
> network access during this time or not. You may not see many more pinmux
> comments from me during that time.
>
> --
> nvpublic
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/
>

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 1/4 v5] drivers: create a pin control subsystem v5
@ 2011-09-01  8:59     ` Linus Walleij
  0 siblings, 0 replies; 16+ messages in thread
From: Linus Walleij @ 2011-09-01  8:59 UTC (permalink / raw)
  To: linux-arm-kernel

On Mon, Aug 29, 2011 at 11:32 PM, Stephen Warren <swarren@nvidia.com> wrote:

> 1) There is still a 1:1 correspondence between what a function in the
> pinmux core<->driver interface, and the pinmux mapping table. I believe
> we need a 1:n correspondence.

Yes I know that, but the positions were never
about solving that issue.

What you are requesting (just like earlier) is
that one requlator_get() should be able to
retrieve multiple map entries and enable/disable
them.

I 've been working on that, it's just a bit tricky.

> i.e. rather than:
>
> driver function/position list:
> function at position pins
> ----------------- ----
> mmc0 at 0 ? ? ? ? ? ?0, 1, 2, 3
> mmc0 at 1 ? ? ? ? ? ?0, 1, 2, 3, 4, 5
> mmc0 at 2 ? ? ? ? ? ?0, 1, 2, 3, 4, 5, 6, 7, 8, 9
>
> core mapping table:
> driver ?name ?function at position
> ------ ?---- ?-----------------
> mmc0 ? ?2-bit mmc0 at 0
> mmc0 ? ?4-bit mmc0 at 1
> mmc0 ? ?8-bit mmc0 at 2

There is no combined function at postion,
these are two were separate fields in the
struct pinmux_map.

What I wanted to express was the noted feature of the
hardware to have the same function in several positions
simply, believing it would be more intuitive.

But since the positions does not seem to be the
answer to the question I've just ripped them out
again. It is now (v6) replaced with a pin group
concept which I hope is closer to what you want.

> I'd far rather see:
>
> driver function list:
> function
> ---------
> mmc0

Can now be found in
<debugfs>/pinctrl/pinctrl.0/pinmux-functions

It will now show the list of different groups that the
function can use.

So a function has 1..* groups associated with it.

Example from U300:

root at ME:/debug/pinctrl/pinctrl.0 cat pinmux-functions
function: power, groups = [ powergrp ]
function: uart0, groups = [ uart0grp ]
function: mmc0, groups = [ mmc0grp ]
function: spi0, groups = [ spi0grp ]

Just one group per function here but can be many.

> driver pin/pingrup list: (names of pins or pingroups):
> pingroup
> --------
> A
> B
> C

Can now be found in
<debugfs>/pinctrl/pinctrl.0/pingroups

Example from U300:

root at ME:/debug/pinctrl/pinctrl.0 cat pingroups
registered pin groups:
group: powergrp, pins = [ 0 1 3 31 46 47 49 50 61 62 63 64 78 79 80 81
92 93 94 95 101 102 103 104 115 116 117 118 130 131 132 133 145 146
147 148 159 160 172 173 174 175 187 188 189 190 201 202 211 212 213
214 215 218 223 224 225 226 231 232 237 238 239 240 245 246 251 252
256 257 258 259 264 265 270 271 276 277 278 279 284 285 290 291 295
296 299 300 301 302 303 309 310 311 312 319 320 321 322 329 330 331
332 341 342 343 344 358 359 360 361 372 373 374 375 388 389 390 391
402 403 404 405 413 414 415 416 427 428 429 430 443 444 455 456 457
458 ]
group: uart0grp, pins = [ 134 135 136 137 ]
group: mmc0grp, pins = [ 166 167 168 169 170 171 176 177 ]
group: spi0grp, pins = [ 420 421 422 423 424 425 ]

Notice that it's not prefixed with the string
"pinmux-", it's just a number of groups of pins,
which can be used for anything, one usecase is
muxing. So I now have an abstract pin group
concept and the pinmux function has atleast
one such group associated.

> core mapping table:
> driver ?name ?position ?function
> ------ ?---- ?-------- ?---------
> mmc0 ? ?2-bit A ? ? ? ? mmc0
> mmc0 ? ?4-bit A ? ? ? ? mmc0
> mmc0 ? ?4-bit B ? ? ? ? mmc0
> mmc0 ? ?8-bit A ? ? ? ? mmc0
> mmc0 ? ?8-bit B ? ? ? ? mmc0
> mmc0 ? ?8-bit C ? ? ? ? mmc0

Now the struct pinmux_map entries look
like this:

struct pinmux_map {
        const char *name;
        struct device *ctrl_dev;
        const char *ctrl_dev_name;
        const char *function;
        const char *group;
        struct device *dev;
        const char *dev_name;
};

Correspondance per above would be:

dev_name, name, group, function

function and group names shall match what is
presented from the pin controller driver.

You can thing of this as SQL:

SELECT ctrl_dev_name,
TOP 1
  FROM MAPS
  WHERE dev_name = device_name
  AND ctrl_dev_name = ctrl_dev_name
  AND function = function
  AND group = group

(the struct device * entries are for the shiny world
where we can access all struct device * at boot or
so)

Then it's the first point about multiple maps
per mux again I guess, when you write like this:

> mmc0    8-bit A         mmc0
> mmc0    8-bit B         mmc0
> mmc0    8-bit C         mmc0

I assume you mean that semantically this shall
be a 1..* relation, so that if I say:

pmx = pinmux_get(&dev, "8-bit");

Then all pins in the union {A, B, C} shall be
allocated and enabled/disabled simultaneously.

so it'd be like the database equivalent:

I am working on that...

> Note again that I'm assuming above that the driver-supplied function and
> pingroup list included all possible options the SoC HW supports, whereas
> the mapping table would include just those configurations ever actually
> used by the particular board the code is executed upon; from board files
> or devicetree data.

This is my current working assumption also.

The pinmux driver should nominally expose all functions in all
possible positions.

Then the pinmux_map maps usually one but sometimes
more of these {function, position} tuples to the device.

And, you also request the currently not implemented
extenstion that a mux can match multiple map entries.

I'll fix.

> Hence, a given board would only need rows 0, 1+2, or
> 3+4+5 from the mapping table shown above, assuming the width of the MMC
> port didn't vary at run-time.

OK we're on the same page I think. If I fix this, then
you're happy?

> 2) "Positions" are defined per "function", rather than as a global concept.
>
> This leads to positions having meaningless integer names. As such,
> constructing the mapping table will be error-prone; who could remember
> that position 0 is a 2-bit bus using a certain set of pins, yet position
> 1 is an 8-bit bus using a different set of pins? I suppose textual names
> might help here. However, by replacing the concept of positions with
> multiple explicit entries in the mapping table (as in my example above),
> that problem is solved; we name the pins (or pingroups) to which we apply
> the driver-level function in each entry, thus it's more self-documenting.

Again I can replace position integers with strings if that is what
you want?

> 3) It's unclear how well pinmux_config() can be applied.

Agee. I will delete this function from pinmux_ops since
it seems it will only be abused for things that are
unrelated to muxing. No shoehorning...

> Some pin parameters might be defined per:
>
> * Pin (probably most systems other than Tegra)
> * Pin group (for pull-up/down, tristate on Tegra)
> * Drive group (another set of groups of pins on Tegra that arbitrarily
> overlap/intersect with the mux pin groups (for drive-strength settings
> on Tegra).

Since these things are unrelated to muxing I prefer that
we add that as a separate set of ops in struct pinctrl_device.

The driver can very well reuse the same groups internally,
nothing prevents that.

I am not intending to address the issue of pin bias,
driver strength, load capacitance, schmitt-trigger input
etc etc etc in this first iteration of the pin control subsystem,
what I want is to get the infrastructure and pin muxing
into the kernel then extend it with other pin control.

I'm trying to avoid excess upfront design.

Do you think these features are needed from day 1
to be of any use for Tegra?

> For pinmux_config() to work, we'd need some API-level concept in order
> to name what pin/group to apply various settings to.
>
> Currently, that
> naming is an entry from the core mapping table, since pinmux_config()
> works on functions returned by pinmux_get(). That doesn't seem right,
> since it prevents the API being used for individual pins/pingroups. Even
> where say 5 different pins/pingroups are used by the same mapping table
> function, there's no reason to believe that their tristate or drive
> strength attributes would all be identical; at least input and output
> pins or control and data might be programmed differently.

Let's avoid trying to solve the things that are not really pinmuxing
with any concept from <linux/pinmux.h>, and let's have separation
of concerns.

I'll kill the (*config) callback for now.

> So in summary, I really think the data model should be as below.
>
> Driver-supplied data 1)
>
> Table of functions, each entry containing:
> * Name of function

This we have I think.

> Driver-supplied data 2)
>
> Table of pins, each entry containing:
> * Name of pin

This we have too I think.

> Driver-supplied data 3)
>
> Optional table of pingroups, each entry containing:
> * Name of pingroup
> * List of pins in the pingroup

OK introduced this as a generic concept in the
v6 patch set.

> Or, in more normalized fashion, with multiple rows per pingroup, each
> entry containing:
> * Name of pingroup
> * One pin with in the pingroup

I don't get this "one pin within the the pingroup"
what if the same pin is part of multiple groups?

The first suggestion seems more solid to me.

> Driver-supplied data 4)
>
> Table of legal functions per pin/pingroup; each entry containing:
> * Name of pin or pingroup

OK I have this now, e.g. inspect the file
<debugfs>/pinctrl.0/groups

> * List of functions that can be legally mux'd to the pin or pingroup
>
> Or, in more normalized fashion, with multiple rows per pingroup, each
> entry containing:
> * Name of pin or pingroup
> * One legal function that can be legally mux'd to the pin or pingroup
>
> Board-supplied data 1)
>
> Mapping table, each entry containing:
> * Driver name/pointer
> * Name of function seen by driver
> * Pin/pingroup name to configure
> * Name of driver function to apply to pin/pingroup
>
> Note that I assume there may be multiple rows for any combination of the
> first two fields in this table, and that all will be operated on by a
> single pinmux_get()/pinmux_enable() call.
>
> Some enhancements in the above list of tables over previous times that I've
> talked about this:
>
> * Created a separate optional table for a list of pingroups, thus not
> burdening SoCs other than Tegra with the pingroup concept.
>
> * Allow either a pin or pingroup name in the driver's "table of legal
> functions per pin" and the "mapping table"; core can simply look through
> the pingroup table if present, then fall back to looking in pin table,
> when determining what a pin/pingroup name means.
>
> * I assume that entries in the "table of pins" or "table of pingroups"
> might have no corresponding entries in " Table of legal functions per
> pin"; in this case, those pin/pingroup names would only be useful for
> pinmux_config() to operate on.
>
>
> P.S. I'll be on vacation 9/2-9/17. I'm not sure if I'll have any form of
> network access during this time or not. You may not see many more pinmux
> comments from me during that time.
>
> --
> nvpublic
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at ?http://www.tux.org/lkml/
>

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH 1/4 v5] drivers: create a pin control subsystem v5
  2011-09-01  8:59     ` Linus Walleij
@ 2011-09-01  9:13       ` Linus Walleij
  -1 siblings, 0 replies; 16+ messages in thread
From: Linus Walleij @ 2011-09-01  9:13 UTC (permalink / raw)
  To: Stephen Warren, Arnd Bergmann
  Cc: Linus Walleij, linux-kernel, linux-arm-kernel, Grant Likely,
	Lee Jones, Joe Perches, Russell King, Linaro Dev, Sascha Hauer,
	David Brown, Barry Song

Damn gmail punished me when writing the reply, sent by mistake :-(

And I intended to post v6 first.

These parts were being typed as I screwed up:

On Thu, Sep 1, 2011 at 10:59 AM, Linus Walleij <linus.walleij@linaro.org> wrote:

> function and group names shall match what is
> presented from the pin controller driver.
>
> You can thing of this as SQL:
>
> SELECT ctrl_dev_name,
> TOP 1
>  FROM MAPS
>  WHERE dev_name = device_name
>  AND ctrl_dev_name = ctrl_dev_name
>  AND function = function
>  AND group = group

I don't know the exact SQL syntax anymore, thing
is that it selects one matching row only.

>> mmc0    8-bit A         mmc0
>> mmc0    8-bit B         mmc0
>> mmc0    8-bit C         mmc0
>
> I assume you mean that semantically this shall
> be a 1..* relation, so that if I say:
>
> pmx = pinmux_get(&dev, "8-bit");
>
> Then all pins in the union {A, B, C} shall be
> allocated and enabled/disabled simultaneously.
>
> so it'd be like the database equivalent:

What I wanted to illustrate here is that the database
return multiple matching rows.

Anyway, I'm onto that.

I will need Arnds or similars advice on it so we don't
grow a lib/mysql into the kernel with this kind of
schemes and get slammed for overcomplicating
things when trying to merge the beast.

So I'm still a bit reluctant about this part  :-/

> Then the pinmux_map maps usually one but sometimes
> more of these {function, position} tuples to the device.

{ function, group } it is.

> And, you also request the currently not implemented
> extenstion that a mux can match multiple map entries.
>
> I'll fix.

Or rather, I'll try.

>> 2) "Positions" are defined per "function", rather than as a global concept.
>>
>> This leads to positions having meaningless integer names. As such,
>> constructing the mapping table will be error-prone; who could remember
>> that position 0 is a 2-bit bus using a certain set of pins, yet position
>> 1 is an 8-bit bus using a different set of pins? I suppose textual names
>> might help here. However, by replacing the concept of positions with
>> multiple explicit entries in the mapping table (as in my example above),
>> that problem is solved; we name the pins (or pingroups) to which we apply
>> the driver-level function in each entry, thus it's more self-documenting.
>
> Again I can replace position integers with strings if that is what
> you want?

Forget this, part of earlier reply.

positions are replaced with groups, which have names.

>> Driver-supplied data 4)
>>
>> Table of legal functions per pin/pingroup; each entry containing:
>> * Name of pin or pingroup
>
> OK I have this now, e.g. inspect the file
> <debugfs>/pinctrl.0/groups

Should be pingroups, and output was correct in the first letter.

>> Board-supplied data 1)
>>
>> Mapping table, each entry containing:
>> * Driver name/pointer
>> * Name of function seen by driver
>> * Pin/pingroup name to configure
>> * Name of driver function to apply to pin/pingroup

This I think is what we have now.

>> Note that I assume there may be multiple rows for any combination of the
>> first two fields in this table, and that all will be operated on by a
>> single pinmux_get()/pinmux_enable() call.

We don't have these multiple rows yet. But I'll try
to implement that.

>> Some enhancements in the above list of tables over previous times that I've
>> talked about this:
>>
>> * Created a separate optional table for a list of pingroups, thus not
>> burdening SoCs other than Tegra with the pingroup concept.

Nah I made it compulsory for pinmux drivers to define their
affected group of pins using an associated abstract pin group.
Makes more sense to me and makes for code reuse if the
groups are used for other things.

>> * Allow either a pin or pingroup name in the driver's "table of legal
>> functions per pin" and the "mapping table"; core can simply look through
>> the pingroup table if present, then fall back to looking in pin table,
>> when determining what a pin/pingroup name means.

Simplified by mandating to use groups. I hope.
A pin table would be equivalent to a group anyway,
just not having its own data structure.

>> * I assume that entries in the "table of pins" or "table of pingroups"
>> might have no corresponding entries in " Table of legal functions per
>> pin"; in this case, those pin/pingroup names would only be useful for
>> pinmux_config() to operate on.

I made it compulsory to associate at least one group of
pins to each function, easier to grasp.

>> P.S. I'll be on vacation 9/2-9/17. I'm not sure if I'll have any form of
>> network access during this time or not. You may not see many more pinmux
>> comments from me during that time.

No problem, I have all life to sort this out.

Thanks,
Linus Walleij

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 1/4 v5] drivers: create a pin control subsystem v5
@ 2011-09-01  9:13       ` Linus Walleij
  0 siblings, 0 replies; 16+ messages in thread
From: Linus Walleij @ 2011-09-01  9:13 UTC (permalink / raw)
  To: linux-arm-kernel

Damn gmail punished me when writing the reply, sent by mistake :-(

And I intended to post v6 first.

These parts were being typed as I screwed up:

On Thu, Sep 1, 2011 at 10:59 AM, Linus Walleij <linus.walleij@linaro.org> wrote:

> function and group names shall match what is
> presented from the pin controller driver.
>
> You can thing of this as SQL:
>
> SELECT ctrl_dev_name,
> TOP 1
> ?FROM MAPS
> ?WHERE dev_name = device_name
> ?AND ctrl_dev_name = ctrl_dev_name
> ?AND function = function
> ?AND group = group

I don't know the exact SQL syntax anymore, thing
is that it selects one matching row only.

>> mmc0 ? ?8-bit A ? ? ? ? mmc0
>> mmc0 ? ?8-bit B ? ? ? ? mmc0
>> mmc0 ? ?8-bit C ? ? ? ? mmc0
>
> I assume you mean that semantically this shall
> be a 1..* relation, so that if I say:
>
> pmx = pinmux_get(&dev, "8-bit");
>
> Then all pins in the union {A, B, C} shall be
> allocated and enabled/disabled simultaneously.
>
> so it'd be like the database equivalent:

What I wanted to illustrate here is that the database
return multiple matching rows.

Anyway, I'm onto that.

I will need Arnds or similars advice on it so we don't
grow a lib/mysql into the kernel with this kind of
schemes and get slammed for overcomplicating
things when trying to merge the beast.

So I'm still a bit reluctant about this part  :-/

> Then the pinmux_map maps usually one but sometimes
> more of these {function, position} tuples to the device.

{ function, group } it is.

> And, you also request the currently not implemented
> extenstion that a mux can match multiple map entries.
>
> I'll fix.

Or rather, I'll try.

>> 2) "Positions" are defined per "function", rather than as a global concept.
>>
>> This leads to positions having meaningless integer names. As such,
>> constructing the mapping table will be error-prone; who could remember
>> that position 0 is a 2-bit bus using a certain set of pins, yet position
>> 1 is an 8-bit bus using a different set of pins? I suppose textual names
>> might help here. However, by replacing the concept of positions with
>> multiple explicit entries in the mapping table (as in my example above),
>> that problem is solved; we name the pins (or pingroups) to which we apply
>> the driver-level function in each entry, thus it's more self-documenting.
>
> Again I can replace position integers with strings if that is what
> you want?

Forget this, part of earlier reply.

positions are replaced with groups, which have names.

>> Driver-supplied data 4)
>>
>> Table of legal functions per pin/pingroup; each entry containing:
>> * Name of pin or pingroup
>
> OK I have this now, e.g. inspect the file
> <debugfs>/pinctrl.0/groups

Should be pingroups, and output was correct in the first letter.

>> Board-supplied data 1)
>>
>> Mapping table, each entry containing:
>> * Driver name/pointer
>> * Name of function seen by driver
>> * Pin/pingroup name to configure
>> * Name of driver function to apply to pin/pingroup

This I think is what we have now.

>> Note that I assume there may be multiple rows for any combination of the
>> first two fields in this table, and that all will be operated on by a
>> single pinmux_get()/pinmux_enable() call.

We don't have these multiple rows yet. But I'll try
to implement that.

>> Some enhancements in the above list of tables over previous times that I've
>> talked about this:
>>
>> * Created a separate optional table for a list of pingroups, thus not
>> burdening SoCs other than Tegra with the pingroup concept.

Nah I made it compulsory for pinmux drivers to define their
affected group of pins using an associated abstract pin group.
Makes more sense to me and makes for code reuse if the
groups are used for other things.

>> * Allow either a pin or pingroup name in the driver's "table of legal
>> functions per pin" and the "mapping table"; core can simply look through
>> the pingroup table if present, then fall back to looking in pin table,
>> when determining what a pin/pingroup name means.

Simplified by mandating to use groups. I hope.
A pin table would be equivalent to a group anyway,
just not having its own data structure.

>> * I assume that entries in the "table of pins" or "table of pingroups"
>> might have no corresponding entries in " Table of legal functions per
>> pin"; in this case, those pin/pingroup names would only be useful for
>> pinmux_config() to operate on.

I made it compulsory to associate at least one group of
pins to each function, easier to grasp.

>> P.S. I'll be on vacation 9/2-9/17. I'm not sure if I'll have any form of
>> network access during this time or not. You may not see many more pinmux
>> comments from me during that time.

No problem, I have all life to sort this out.

Thanks,
Linus Walleij

^ permalink raw reply	[flat|nested] 16+ messages in thread

* RE: [PATCH 1/4 v5] drivers: create a pin control subsystem v5
  2011-09-01  9:13       ` Linus Walleij
@ 2011-09-01 19:43         ` Stephen Warren
  -1 siblings, 0 replies; 16+ messages in thread
From: Stephen Warren @ 2011-09-01 19:43 UTC (permalink / raw)
  To: Linus Walleij, Arnd Bergmann
  Cc: Linus Walleij, linux-kernel, linux-arm-kernel, Grant Likely,
	Lee Jones, Joe Perches, Russell King, Linaro Dev, Sascha Hauer,
	David Brown, Barry Song

Linus Walleij wrote at Thursday, September 01, 2011 3:13 AM:
...
> I will need Arnds or similars advice on it so we don't
> grow a lib/mysql into the kernel with this kind of
> schemes and get slammed for overcomplicating
> things when trying to merge the beast.

I /think/ the whole multi-row thing is just doing this:

for each row of table:
    if it matches search terms:
        Activate the specified function on the group

Whereas handling just one entry is almost the same:

for each row of table:
    if it matches search terms:
        Activate the specified function on the group
        break

Of course, in the former case, the error-handling also has to iterate
over all the already-processed rows and unreserved/unprogram the HW too,
but that should be a pretty simple loop too.

And replying to your immediately earlier email:

...
> > Hence, a given board would only need rows 0, 1+2, or
> > 3+4+5 from the mapping table shown above, assuming the width of the MMC
> > port didn't vary at run-time.
> 
> OK we're on the same page I think. If I fix this, then
> you're happy?

I haven't read patchset 6 yet, but from the descriptions in your email
and the patch 0 changelog, it certainly sounds like we're on very
similar pages now.

> > Some pin parameters might be defined per:
> >
> > * Pin (probably most systems other than Tegra)
> > * Pin group (for pull-up/down, tristate on Tegra)
> > * Drive group (another set of groups of pins on Tegra that arbitrarily
> > overlap/intersect with the mux pin groups (for drive-strength settings
> > on Tegra).
> 
> Since these things are unrelated to muxing I prefer that
> we add that as a separate set of ops in struct pinctrl_device.
> 
> The driver can very well reuse the same groups internally,
> nothing prevents that.
> 
> I am not intending to address the issue of pin bias,
> driver strength, load capacitance, schmitt-trigger input
> etc etc etc in this first iteration of the pin control subsystem,
> what I want is to get the infrastructure and pin muxing
> into the kernel then extend it with other pin control.
> 
> I'm trying to avoid excess upfront design.
> 
> Do you think these features are needed from day 1
> to be of any use for Tegra?

I think having just muxing support would work fine for a first pass.

Looking forward a little, I expect that different SoCs have such a
different set of biasing/driver-strength/... options that actually having
some formalized semantic representation of what those options are doesn't
make sense; all we need is a standard API to set the values for a given
pin or pingroup; just like the config API you already had, but applied
to pingroups rather than explicitly GPIOs, and where the driver supplies
the names for the settings and interprets what the values mean for a
given setting. I imagine having the config API in the first pass wouldn't
be contentious, provided it applied to pingroups.

Just possibly, I could imagine needing config entries in the mapping table,
so when switching between mapping entries at run-time you could both program
muxing and other configuration. However, that's definitely not a first-pass
thing, as you say. And I'm just guessing if it'll be needed anyway.

> > Or, in more normalized fashion, with multiple rows per pingroup, each
> > entry containing:
> > * Name of pingroup
> > * One pin with in the pingroup
> 
> I don't get this "one pin within the the pingroup"
> what if the same pin is part of multiple groups?

It was just a data-representation thing. You could either have:

struct {
    char * pingroup;
    int npins;
    int * pins;
};

Where one row represents everything about a pingroup, or:

struct {
    char * pingroup;
    int pin;
};

Where you'd need a row for each pin in a pingroup.

Go with whatever you find is easiest; I was just thinking databases for
a while!

-- 
nvpublic


^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 1/4 v5] drivers: create a pin control subsystem v5
@ 2011-09-01 19:43         ` Stephen Warren
  0 siblings, 0 replies; 16+ messages in thread
From: Stephen Warren @ 2011-09-01 19:43 UTC (permalink / raw)
  To: linux-arm-kernel

Linus Walleij wrote at Thursday, September 01, 2011 3:13 AM:
...
> I will need Arnds or similars advice on it so we don't
> grow a lib/mysql into the kernel with this kind of
> schemes and get slammed for overcomplicating
> things when trying to merge the beast.

I /think/ the whole multi-row thing is just doing this:

for each row of table:
    if it matches search terms:
        Activate the specified function on the group

Whereas handling just one entry is almost the same:

for each row of table:
    if it matches search terms:
        Activate the specified function on the group
        break

Of course, in the former case, the error-handling also has to iterate
over all the already-processed rows and unreserved/unprogram the HW too,
but that should be a pretty simple loop too.

And replying to your immediately earlier email:

...
> > Hence, a given board would only need rows 0, 1+2, or
> > 3+4+5 from the mapping table shown above, assuming the width of the MMC
> > port didn't vary at run-time.
> 
> OK we're on the same page I think. If I fix this, then
> you're happy?

I haven't read patchset 6 yet, but from the descriptions in your email
and the patch 0 changelog, it certainly sounds like we're on very
similar pages now.

> > Some pin parameters might be defined per:
> >
> > * Pin (probably most systems other than Tegra)
> > * Pin group (for pull-up/down, tristate on Tegra)
> > * Drive group (another set of groups of pins on Tegra that arbitrarily
> > overlap/intersect with the mux pin groups (for drive-strength settings
> > on Tegra).
> 
> Since these things are unrelated to muxing I prefer that
> we add that as a separate set of ops in struct pinctrl_device.
> 
> The driver can very well reuse the same groups internally,
> nothing prevents that.
> 
> I am not intending to address the issue of pin bias,
> driver strength, load capacitance, schmitt-trigger input
> etc etc etc in this first iteration of the pin control subsystem,
> what I want is to get the infrastructure and pin muxing
> into the kernel then extend it with other pin control.
> 
> I'm trying to avoid excess upfront design.
> 
> Do you think these features are needed from day 1
> to be of any use for Tegra?

I think having just muxing support would work fine for a first pass.

Looking forward a little, I expect that different SoCs have such a
different set of biasing/driver-strength/... options that actually having
some formalized semantic representation of what those options are doesn't
make sense; all we need is a standard API to set the values for a given
pin or pingroup; just like the config API you already had, but applied
to pingroups rather than explicitly GPIOs, and where the driver supplies
the names for the settings and interprets what the values mean for a
given setting. I imagine having the config API in the first pass wouldn't
be contentious, provided it applied to pingroups.

Just possibly, I could imagine needing config entries in the mapping table,
so when switching between mapping entries at run-time you could both program
muxing and other configuration. However, that's definitely not a first-pass
thing, as you say. And I'm just guessing if it'll be needed anyway.

> > Or, in more normalized fashion, with multiple rows per pingroup, each
> > entry containing:
> > * Name of pingroup
> > * One pin with in the pingroup
> 
> I don't get this "one pin within the the pingroup"
> what if the same pin is part of multiple groups?

It was just a data-representation thing. You could either have:

struct {
    char * pingroup;
    int npins;
    int * pins;
};

Where one row represents everything about a pingroup, or:

struct {
    char * pingroup;
    int pin;
};

Where you'd need a row for each pin in a pingroup.

Go with whatever you find is easiest; I was just thinking databases for
a while!

-- 
nvpublic

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH 1/4 v5] drivers: create a pin control subsystem v5
  2011-09-01 19:43         ` Stephen Warren
@ 2011-09-02  8:07           ` Linus Walleij
  -1 siblings, 0 replies; 16+ messages in thread
From: Linus Walleij @ 2011-09-02  8:07 UTC (permalink / raw)
  To: Stephen Warren
  Cc: Arnd Bergmann, Linus Walleij, linux-kernel, linux-arm-kernel,
	Grant Likely, Lee Jones, Joe Perches, Russell King, Linaro Dev,
	Sascha Hauer, David Brown, Barry Song

On Thu, Sep 1, 2011 at 9:43 PM, Stephen Warren <swarren@nvidia.com> wrote:

> Looking forward a little, I expect that different SoCs have such a
> different set of biasing/driver-strength/... options that actually having
> some formalized semantic representation of what those options are doesn't
> make sense; all we need is a standard API to set the values for a given
> pin or pingroup;

I'm still thinking about this thing, when I (and others) wer trying to
shoehorn this kind of stuff into the GPIO layer I actually started to
enumerate the different things you could do with a pin, beginning
like this:

+/*
+ * Bias modes for GPIOs - if you have more biases, add them here or provide
+ * custom enumerators for your driver if you find they are not generally
+ * useful.
+ *
+ * GPIO_CONFIG_BIAS_UNKNOWN: this bias mode is not known to us
+ * GPIO_CONFIG_BIAS_FLOAT: no specific bias, the GPIO will float or state
+ *     is not controlled by software
+ * GPIO_CONFIG_BIAS_PULL_UP: the GPIO will be pulled up (usually with high
+ *     impedance to VDD)
+ * GPIO_CONFIG_BIAS_PULL_DOWN: the GPIO will be pulled down (usually with high
+ *     impedance to GROUND)
+ * GPIO_BIAS_HIGH: the GPIO will be wired high, connected to VDD
+ * GPIO_BIAS_GROUND: the GPIO will be grounded, connected to GROUND
+ */
+#define GPIO_CONFIG_BIAS_UNKNOWN       0x1000
+#define GPIO_CONFIG_BIAS_FLOAT         0x1001
+#define GPIO_CONFIG_BIAS_PULL_UP       0x1002
+#define GPIO_CONFIG_BIAS_PULL_DOWN     0x1003
+#define GPIO_CONFIG_BIAS_HIGH          0x1004
+#define GPIO_CONFIG_BIAS_GROUND        0x1005
+
+/*
+ * Drive modes for GPIOs (output) - if you have more custom modes either
+ * add them here or keep them to your driver if you think they are not
+ * generally useful.
+ *
+ * GPIO_CONFIG_DRIVE_UNKNOWN: we don't know the drive mode of this GPIO, for
+ *     example since it is controlled by hardware or the information is not
+ *     accessible but we need a meaningful enumerator in e.g. initialization
+ *     code
+ * GPIO_CONFIG_DRIVE_PUSH_PULL: the GPIO will be driven actively high and
+ *     low, this is the most typical case and is typically achieved with two
+ *     active transistors on the output
+ * GPIO_CONFIG_DRIVE_OPEN_DRAIN: the GPIO will be driven with open drain (open
+ *     collector) which means it is usually wired with other output ports
+ *     which are then pulled up with an external resistor
+ * GPIO_CONFIG_DRIVE_OPEN_SOURCE: the GPIO will be driven with open drain
+ *     (open emitter) which is the same as open drain mutatis mutandis but
+ *     pulled to ground
+ * GPIO_CONFIG_DRIVE_OFF: the GPIO pin is set to inactive mode, off
+ */
+#define GPIO_CONFIG_DRIVE_UNKNOWN      0x2010
+#define GPIO_CONFIG_DRIVE_PUSH_PULL    0x2011
+#define GPIO_CONFIG_DRIVE_OPEN_DRAIN   0x2012
+#define GPIO_CONFIG_DRIVE_OPEN_SOURCE  0x2013
+#define GPIO_CONFIG_DRIVE_OFF          0x2014

The basic assumption is that there are not that infinitely many
things you may want to do with a pin after all.

I can already think about interesting enumerators for
GPIO_CONFIG_INPUT_SCHMITT_TRIGGER
GPIO_CONFIG_INPUT_LOAD_CAPACITANCE
etc. But not unenumerable things.

The upside of this scheme is that we might have some handle on
trying to consolidate common functionality between drivers,
also to sort of consolidate the knowledge of what you can
do with pins in one place, even if you can't share any code.

For a stupid example the generic debugfs files could give you a list
of all pins in any system and what bias mode they're in, no
matter what platform we're dealing with, which would give the
some kind of cosy consensus for developers that platforms
are not that different after all.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH 1/4 v5] drivers: create a pin control subsystem v5
@ 2011-09-02  8:07           ` Linus Walleij
  0 siblings, 0 replies; 16+ messages in thread
From: Linus Walleij @ 2011-09-02  8:07 UTC (permalink / raw)
  To: linux-arm-kernel

On Thu, Sep 1, 2011 at 9:43 PM, Stephen Warren <swarren@nvidia.com> wrote:

> Looking forward a little, I expect that different SoCs have such a
> different set of biasing/driver-strength/... options that actually having
> some formalized semantic representation of what those options are doesn't
> make sense; all we need is a standard API to set the values for a given
> pin or pingroup;

I'm still thinking about this thing, when I (and others) wer trying to
shoehorn this kind of stuff into the GPIO layer I actually started to
enumerate the different things you could do with a pin, beginning
like this:

+/*
+ * Bias modes for GPIOs - if you have more biases, add them here or provide
+ * custom enumerators for your driver if you find they are not generally
+ * useful.
+ *
+ * GPIO_CONFIG_BIAS_UNKNOWN: this bias mode is not known to us
+ * GPIO_CONFIG_BIAS_FLOAT: no specific bias, the GPIO will float or state
+ *     is not controlled by software
+ * GPIO_CONFIG_BIAS_PULL_UP: the GPIO will be pulled up (usually with high
+ *     impedance to VDD)
+ * GPIO_CONFIG_BIAS_PULL_DOWN: the GPIO will be pulled down (usually with high
+ *     impedance to GROUND)
+ * GPIO_BIAS_HIGH: the GPIO will be wired high, connected to VDD
+ * GPIO_BIAS_GROUND: the GPIO will be grounded, connected to GROUND
+ */
+#define GPIO_CONFIG_BIAS_UNKNOWN       0x1000
+#define GPIO_CONFIG_BIAS_FLOAT         0x1001
+#define GPIO_CONFIG_BIAS_PULL_UP       0x1002
+#define GPIO_CONFIG_BIAS_PULL_DOWN     0x1003
+#define GPIO_CONFIG_BIAS_HIGH          0x1004
+#define GPIO_CONFIG_BIAS_GROUND        0x1005
+
+/*
+ * Drive modes for GPIOs (output) - if you have more custom modes either
+ * add them here or keep them to your driver if you think they are not
+ * generally useful.
+ *
+ * GPIO_CONFIG_DRIVE_UNKNOWN: we don't know the drive mode of this GPIO, for
+ *     example since it is controlled by hardware or the information is not
+ *     accessible but we need a meaningful enumerator in e.g. initialization
+ *     code
+ * GPIO_CONFIG_DRIVE_PUSH_PULL: the GPIO will be driven actively high and
+ *     low, this is the most typical case and is typically achieved with two
+ *     active transistors on the output
+ * GPIO_CONFIG_DRIVE_OPEN_DRAIN: the GPIO will be driven with open drain (open
+ *     collector) which means it is usually wired with other output ports
+ *     which are then pulled up with an external resistor
+ * GPIO_CONFIG_DRIVE_OPEN_SOURCE: the GPIO will be driven with open drain
+ *     (open emitter) which is the same as open drain mutatis mutandis but
+ *     pulled to ground
+ * GPIO_CONFIG_DRIVE_OFF: the GPIO pin is set to inactive mode, off
+ */
+#define GPIO_CONFIG_DRIVE_UNKNOWN      0x2010
+#define GPIO_CONFIG_DRIVE_PUSH_PULL    0x2011
+#define GPIO_CONFIG_DRIVE_OPEN_DRAIN   0x2012
+#define GPIO_CONFIG_DRIVE_OPEN_SOURCE  0x2013
+#define GPIO_CONFIG_DRIVE_OFF          0x2014

The basic assumption is that there are not that infinitely many
things you may want to do with a pin after all.

I can already think about interesting enumerators for
GPIO_CONFIG_INPUT_SCHMITT_TRIGGER
GPIO_CONFIG_INPUT_LOAD_CAPACITANCE
etc. But not unenumerable things.

The upside of this scheme is that we might have some handle on
trying to consolidate common functionality between drivers,
also to sort of consolidate the knowledge of what you can
do with pins in one place, even if you can't share any code.

For a stupid example the generic debugfs files could give you a list
of all pins in any system and what bias mode they're in, no
matter what platform we're dealing with, which would give the
some kind of cosy consensus for developers that platforms
are not that different after all.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 16+ messages in thread

end of thread, other threads:[~2011-09-02  8:07 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-08-29  9:10 [PATCH 1/4 v5] drivers: create a pin control subsystem v5 Linus Walleij
2011-08-29  9:10 ` Linus Walleij
2011-08-29 21:32 ` Stephen Warren
2011-08-29 21:32   ` Stephen Warren
2011-09-01  8:59   ` Linus Walleij
2011-09-01  8:59     ` Linus Walleij
2011-09-01  9:13     ` Linus Walleij
2011-09-01  9:13       ` Linus Walleij
2011-09-01 19:43       ` Stephen Warren
2011-09-01 19:43         ` Stephen Warren
2011-09-02  8:07         ` Linus Walleij
2011-09-02  8:07           ` Linus Walleij
2011-08-30 10:02 ` Jamie Iles
2011-08-30 10:02   ` Jamie Iles
2011-08-31  9:45 ` Barry Song
2011-08-31  9:45   ` Barry Song

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