From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2B82C10DCE for ; Thu, 12 Mar 2020 10:43:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7497E206BE for ; Thu, 12 Mar 2020 10:43:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="uFc/Rnj7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726641AbgCLKnN (ORCPT ); Thu, 12 Mar 2020 06:43:13 -0400 Received: from mail-ua1-f68.google.com ([209.85.222.68]:38296 "EHLO mail-ua1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725268AbgCLKnM (ORCPT ); Thu, 12 Mar 2020 06:43:12 -0400 Received: by mail-ua1-f68.google.com with SMTP id y3so1918451uaq.5 for ; Thu, 12 Mar 2020 03:43:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=BgQ1lKYAzrP/ZqvfkvUxViMKhdPH7tv6/C3fxPaFEQY=; b=uFc/Rnj7BPhDv4t4FAjhtf6HefM/cUWleVgCwidPMZimPodrl4dJssAP3T3K6129Ms X6I248jjt5LmwFQ8caxaAqN1oeFaKo1Ya5dZcoZ3xqA+phWAF1vxDBPkgP2wRUvKtlL6 L66DL6EanjUby5+HVZ0PScCqDJJwaJ0wr/moWLArnZYtRElQ14X/qJkQKW9+OoW1tm/i 08Atd1I+leUXC1Dgph8tB7aNcuA+2cZ68rzG3KkpCpRepCoe6dDJa1fn4FYVtnYUsEmj Ufg1TYZudMkVkBdxK42xZscarqs2x3+9/FovvHXw4lQwpY50lZsUp6baVvh2k0HznQmr 4itw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=BgQ1lKYAzrP/ZqvfkvUxViMKhdPH7tv6/C3fxPaFEQY=; b=D3guHsF0rJDL8bxiOrX7u/ndgc4unWUiW6/wso81jthe6rcp+IVMG5wnd+eCly0JtJ xRInVWKziqUJgGh2V5YAvMlPi18JlCvaFmqEWaAxYYglyYVjI3PjwKzrW5MNy6JHUj8x BHV+wJgJM2e/5W4jD37qFG5mflYKpB5upjdfktWhiiRW2nUVF8tXjLR8qEDvqhNYx55r kw0aKDNh9olyE4g9M9qcDVObZs30PllGUkHucOsAIoVEP884SF4ygstjOnxoGBHV2bUI wpI/LRxcQuTOmInSCq+vmroLJYud+WEs/KsnEDor5/UN2dn48KLs5jjo2Wb4Q0R9P0yt bkOg== X-Gm-Message-State: ANhLgQ1QLtPpQAVu1Mz5XXlzqu0lcWkZYn11B8plvUNo5KVvORXz5qon VQgMKBkWq98HfjEnUsjkczJi/Mh9VCH2KBLpTa80uw== X-Google-Smtp-Source: ADFU+vteH2YbvQ5WHO+nQE8IL8GqQeob2h6Q9zbcvIMlxnHywyMFpqBtkl374HZeCDIHXJK4gLn7KkvLEmaRcuRp9Rs= X-Received: by 2002:ab0:5ea9:: with SMTP id y41mr4347432uag.10.1584009791099; Thu, 12 Mar 2020 03:43:11 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Linus Walleij Date: Thu, 12 Mar 2020 11:43:00 +0100 Message-ID: Subject: Re: gpio-omap: add support gpiolib bias (pull-up/down) flags? To: Drew Fustini Cc: Grygorii Strashko , Santosh Shilimkar , Kevin Hilman , "linux-gpio@vger.kernel.org" , Bartosz Golaszewski , Drew Fustini , Kent Gibson , Jason Kridner , Robert Nelson Content-Type: text/plain; charset="UTF-8" Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Drew, On Sun, Mar 8, 2020 at 2:07 PM Drew Fustini wrote: > I would like the BeagleBone, which has the TI AM3358 SoC, to be able > to use the bias flags as well. The AM3358 uses the gpio-omap GPIO > driver. However, gpio-omap does not support these flags [8]. > > Do you have any feedback on whether this is possible to implement? Do we have a datasheet for this GPIO block somewhere? Should be the datasheet for the ASIC. We already have the required .set_config() callback on the OMAP driver, it's just that it only uses it for debounce. The driver is a bit convoluted with register offsets in a struct omap_gpio_reg_offs depending on variant, but if they have a register for this I'd say just get hacking. If the GPIO driver is using pin control as back-end you are looking at something more complex similar to what Intel is doing inside drivers/pinctrl/intel/pinctrl-intel.c: this driver is just calling up to gpiochip_generic_config() which will try to configure the lines behind the GPIO using pin config, which works if the proper ranges are defined so the framework can map a GPIO line to a pin control pin. Yours, Linus Walleij