From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E36AC2D0CF for ; Mon, 16 Dec 2019 08:32:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3414D20828 for ; Mon, 16 Dec 2019 08:32:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="YoxUQn0M" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726881AbfLPIcc (ORCPT ); Mon, 16 Dec 2019 03:32:32 -0500 Received: from mail-vs1-f67.google.com ([209.85.217.67]:35625 "EHLO mail-vs1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726788AbfLPIcc (ORCPT ); Mon, 16 Dec 2019 03:32:32 -0500 Received: by mail-vs1-f67.google.com with SMTP id x123so3621269vsc.2 for ; Mon, 16 Dec 2019 00:32:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=JkgTe7RiiAq5QhSu2PZNU7m2RnEe6PES0VorJPFQMuI=; b=YoxUQn0M3SuXi8l42WvhOcaLVs9FtT4yYaFQt1JnF7fyLfINtK8IH7LjURdGPX5cQ1 R8URrTHR/tj+puo4KBNXX1HKPhXcrqFlXy1ed8ZAsrUqVCXYWsnWJV0l7kex0g1yZoXR ri9Oi04z+9x1kjq1esub91N9X6+vdJ8E7w/+ezYVaY537kG05SnQU8+6Xy8y7GSwZuMx UEn5PjruDsQcgqx6ab95Q8EB3LntrQNSNE2lq25zQg8eSVkdAhtnJpNcOC53TKRZYFvy YxYi/hR2QW9Fsb0DW3Xi9SGjCXGwlS7mHg66lIyjG/P95hwzr5KnTr73Eh/SyycJOIqa 3sDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=JkgTe7RiiAq5QhSu2PZNU7m2RnEe6PES0VorJPFQMuI=; b=tRW848kOE9QVUIEhBHa9SxL8452cRxp04k7caKQbAFPsmn+TPmLIw2PgcdNjL67PvX fATH/dVYH1/iTavlALlz2fSEKmC0NMRvkmIRSmsXSVq6C6oFVz9wFDbm1jovZw11S+jy yFpQAVx2aUv+ODXf9A07CybOjVvHauInDK12JuBpJwCAn7X3K0h8BrXyOMqwsQcaVQ7D ibyTfgj/BXyNtbPncpj6V9/EHwKJc+YwMl3wMUB1gt//B/Mz+uMvCu37KZ+aph8TNPbI xM3RBSTJm0gL3A5OuYzfRGYlVgMT2er/TkoX3m/BHWT6vY2NsNlyXYBA4qOQ9+abw907 k8mA== X-Gm-Message-State: APjAAAXqF1ztyW3cIwOPyH2cFh1k9Cv90+J04Y8Q3bdyFbEYkdEoQcKC JGV9z2L6cDy//FXzIO/ioS2sVv+AsMKMMI9urQPYjw== X-Google-Smtp-Source: APXvYqy6s+VOmPyj3eK02h1e4bwZVh9q2OoyCiemRBTtBkO775i3aGAeU2EoW0Amob5gIdaXOUj0ObPrX0yIOlsfXQ0= X-Received: by 2002:a67:d592:: with SMTP id m18mr20661597vsj.85.1576485151530; Mon, 16 Dec 2019 00:32:31 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Linus Walleij Date: Mon, 16 Dec 2019 09:32:20 +0100 Message-ID: Subject: Re: [PATCH v6 13/15] gpio: bd71828: Initial support for ROHM BD71828 PMIC GPIOs To: Matti Vaittinen Cc: Matti Vaittinen , Jacek Anaszewski , Pavel Machek , Dan Murphy , Rob Herring , Mark Rutland , Lee Jones , Liam Girdwood , Mark Brown , Jonathan Corbet , Michael Turquette , Stephen Boyd , Bartosz Golaszewski , Alessandro Zummo , Alexandre Belloni , Greg Kroah-Hartman , Arnd Bergmann , Mauro Carvalho Chehab , Wolfram Sang , Phil Edworthy , =?UTF-8?Q?Noralf_Tr=C3=B8nnes?= , Linux LED Subsystem , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "linux-kernel@vger.kernel.org" , Linux Doc Mailing List , linux-clk , "open list:GPIO SUBSYSTEM" , linux-rtc@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Sender: linux-leds-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-leds@vger.kernel.org On Wed, Dec 11, 2019 at 10:49 AM Matti Vaittinen wrote: > ROHM BD71828 PMIC contains 4 pins which can be configured by OTP > to be used for general purposes. First 3 can be used as outputs > and 4.th pin can be used as input. Allow them to be controlled > via GPIO framework. > > The driver assumes all of the pins are configured as GPIOs and > trusts that the reserved pins in other OTP configurations are > excluded from control using "gpio-reserved-ranges" device tree > property (or left untouched by GPIO users). > > Typical use for 4.th pin (input) is to use it as HALL sensor > input so that this pin state is toggled when HALL sensor detects > LID position change (from close to open or open to close). PMIC > HW implements some extra logic which allows PMIC to power-up the > system when this pin is toggled. Please see the data sheet for > details of GPIO options which can be selected by OTP settings. > > Signed-off-by: Matti Vaittinen > Reviewed-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Yours, Linus Walleij