From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6541C43334 for ; Thu, 30 Jun 2022 09:17:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ad1ViBT8lDwuD5LzpqkMkiw1wxDTHLYqqrdCjhTlSO0=; b=yIC+4rzuQjtec+ sgmw+OJaO6OTl4/VjI48wL5CXWqyODv/RccruW7tFZcrIaXDsmpvbXYPdO9v0homU4HaizvOjj12m evRh9pDr2VilnoT3jKluQ9nbwA3RESfeb3E3kETT7ZQGpu8EYbw9hlnGr6M1hHKnNmQ4ZZC4J3N37 wxdYuM4NGoBJwhRIeweCdIc2qnl9KUDYJd9ukwFTmps3I9A1HmYoMbQeyyOxc55zTLZXW1RRfrBkS mrHzN0Tw8iOMstI7syRA4TOtZqP7c9yr532Ex3ViE63W+BQGI4l4A139EyqTnu6oPMcoZMMtavG11 7xF0XG7vXPYMPcFrEKnQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o6qI9-00GChe-Ci; Thu, 30 Jun 2022 09:16:53 +0000 Received: from mail-yw1-x1135.google.com ([2607:f8b0:4864:20::1135]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o6qI6-00GCgG-0p for linux-arm-kernel@lists.infradead.org; Thu, 30 Jun 2022 09:16:51 +0000 Received: by mail-yw1-x1135.google.com with SMTP id 00721157ae682-31780ad7535so172688397b3.8 for ; Thu, 30 Jun 2022 02:16:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=y2VcWUn76owMkahIiSpe6u3dmJvIJ7O7/SunZB5ovaY=; b=EIZ5mBcgizaSwAGmq8RVN4Ev0EgefBfQ1Zkam3vTcFZbuOMtG8vnYJWocqRzbgnrqp Hyzh/VH2EDFZWQs5uN738AesOeGyPhc5e45LDg+anBaRy2a/EN28QLRuUcxDG6InguBL pOALxDvaFC8nD2KIw6whHPam9YQAA4HbTu7zN9ag0BnhNxbWZDVQCAlBupiGGjRkroZc zqCG8/QOEmVkq9Rxpb7H/Uk7/vbJqADBHWAqo0UNOxAROQET3/nNxpJmgENWPr6uP2am q0DOqGm9kzthmJVC+WO1GuLwK1cWU7dKrDuHI4ShAORa95YMl1DfAI6HD9Z5WInpN8nO TWgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=y2VcWUn76owMkahIiSpe6u3dmJvIJ7O7/SunZB5ovaY=; b=cyGozvDRgQQDxlyPBKCRIq8uQgXmebs4L46zGC5CdgJXBmdH65RB8PsdZZ6gB6+QfF 93AmEDUYsVwlxcuaUuOttxyGhiwrLxdB1s+YrvNaVsj3aCMNYLd2UOH1SZ0iRX1L9k4x +ujMEz3auPM928BzFL3SRvW+voNRHzNJPLmlhha17Q7C6DFhTfPsuj+hvLuLUWwVojNA NEedv5Eyv9Ila5/BblvZpqvgtNTNhjulj+cIwbM1QqnjpBUGnzP7fgj9qccLmG0Agc66 JtwAtGJzL2Ynnydi0wAPO/dnCWH7M4FvZouy1AkgqW4SFTk4o3/mhQcEpL2wH3djDXsY nxsQ== X-Gm-Message-State: AJIora9i+hHLbhMhjUV1S8s1PKYhBdGpNAH46aWKsG8MnAJmIwgr3TmX wI6sT8pkZyQn6hnqQ7j5PiBwvGQYfwmxCc+71x2m/Q== X-Google-Smtp-Source: AGRyM1tjLZ153j7Np3XGNGpSK5G64rKc8JOpc+/Fc3g7HcwAIDXbcAmIMxNFbsul/0N0Bx967t8Cyw5rxHBJe9cOL4w= X-Received: by 2002:a81:71c6:0:b0:318:38d5:37f3 with SMTP id m189-20020a8171c6000000b0031838d537f3mr9507316ywc.268.1656580607004; Thu, 30 Jun 2022 02:16:47 -0700 (PDT) MIME-Version: 1.0 References: <20220629102304.65712-1-chanho61.park@samsung.com> <20220629102304.65712-3-chanho61.park@samsung.com> In-Reply-To: <20220629102304.65712-3-chanho61.park@samsung.com> From: Linus Walleij Date: Thu, 30 Jun 2022 11:16:35 +0200 Message-ID: Subject: Re: [PATCH v3 2/4] spi: s3c64xx: support custom value of internal clock divider To: Chanho Park Cc: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220630_021650_105232_6B6AE71F X-CRM114-Status: GOOD ( 12.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jun 29, 2022 at 12:27 PM Chanho Park wrote: > Modern exynos SoCs such as Exynos Auto v9 have different internal clock > divider, for example "4". To support this internal value, this adds > clk_div of the s3c64xx_spi_port_config and assign "2" as the default > value to existing s3c64xx_spi_port_config. > > Signed-off-by: Chanho Park While this gives a way to set up the default clock divider (which is fair) I think you should probably go the extra mile and make this clock divider a proper clock abstraction, so the driver can respect the DT standard property spi-max-frequency from Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml This actually isn't very hard: look for example in the PL111 driver, a hardware block that contains a similar internal clock divider: drivers/gpu/drm/pl111/pl111_display.c check how we define a clock from pl111_clk_div_ops. in pl111_init_clock_divider(). Then the driver probe() just grabs that clock and sets the frequency. The algorithms should be pretty much copy/paste. Yours, Linus Walleij _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CE42CCA47E for ; Thu, 30 Jun 2022 09:18:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233414AbiF3JSd (ORCPT ); Thu, 30 Jun 2022 05:18:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234148AbiF3JSC (ORCPT ); Thu, 30 Jun 2022 05:18:02 -0400 Received: from mail-yw1-x112b.google.com (mail-yw1-x112b.google.com [IPv6:2607:f8b0:4864:20::112b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B15D43FBF2 for ; Thu, 30 Jun 2022 02:16:47 -0700 (PDT) Received: by mail-yw1-x112b.google.com with SMTP id 00721157ae682-31bf327d4b5so83387897b3.13 for ; Thu, 30 Jun 2022 02:16:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=y2VcWUn76owMkahIiSpe6u3dmJvIJ7O7/SunZB5ovaY=; b=EIZ5mBcgizaSwAGmq8RVN4Ev0EgefBfQ1Zkam3vTcFZbuOMtG8vnYJWocqRzbgnrqp Hyzh/VH2EDFZWQs5uN738AesOeGyPhc5e45LDg+anBaRy2a/EN28QLRuUcxDG6InguBL pOALxDvaFC8nD2KIw6whHPam9YQAA4HbTu7zN9ag0BnhNxbWZDVQCAlBupiGGjRkroZc zqCG8/QOEmVkq9Rxpb7H/Uk7/vbJqADBHWAqo0UNOxAROQET3/nNxpJmgENWPr6uP2am q0DOqGm9kzthmJVC+WO1GuLwK1cWU7dKrDuHI4ShAORa95YMl1DfAI6HD9Z5WInpN8nO TWgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=y2VcWUn76owMkahIiSpe6u3dmJvIJ7O7/SunZB5ovaY=; b=xEI8FElRDb4DDYQy63aXesXCIZn6j2m50AWQm3YGQMIbLrzSnit4F2PcGCuXLUtGc1 67KMKWHbhQu+ahAQ/N5YTsaJDxjRg3E7pdtq77UYchYDYyGKnegiQuK/MJCQXjmnHK1u kmC3re47wq1eRWmyKTDKaWb65dSuCbResgWPLVCXBxukiAL1M0vjBssQ6i4m9sh/1/ff Jr5Gboe0K2S2e+Kxkg9DzYTDyZfkCK3ADel2FMEppMbpPv+s53DBucsYpyoF43xwGOYd cVlDpophB97Yo1E+DgTvMEebWMbZmSSIuU8ghgTxibD6pEVfrsYq0gQrkl+ovA6ivd74 //Bw== X-Gm-Message-State: AJIora8U6ZXU5OjHen+qGozU0bKmS/Pat4lOZaAWEWid4DhHul4eIg8N dM7Zrxv9XPgmQRNUeb1R8b2H24WYNUNr7ZqHVzxX0g== X-Google-Smtp-Source: AGRyM1tjLZ153j7Np3XGNGpSK5G64rKc8JOpc+/Fc3g7HcwAIDXbcAmIMxNFbsul/0N0Bx967t8Cyw5rxHBJe9cOL4w= X-Received: by 2002:a81:71c6:0:b0:318:38d5:37f3 with SMTP id m189-20020a8171c6000000b0031838d537f3mr9507316ywc.268.1656580607004; Thu, 30 Jun 2022 02:16:47 -0700 (PDT) MIME-Version: 1.0 References: <20220629102304.65712-1-chanho61.park@samsung.com> <20220629102304.65712-3-chanho61.park@samsung.com> In-Reply-To: <20220629102304.65712-3-chanho61.park@samsung.com> From: Linus Walleij Date: Thu, 30 Jun 2022 11:16:35 +0200 Message-ID: Subject: Re: [PATCH v3 2/4] spi: s3c64xx: support custom value of internal clock divider To: Chanho Park Cc: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Jun 29, 2022 at 12:27 PM Chanho Park wrote: > Modern exynos SoCs such as Exynos Auto v9 have different internal clock > divider, for example "4". To support this internal value, this adds > clk_div of the s3c64xx_spi_port_config and assign "2" as the default > value to existing s3c64xx_spi_port_config. > > Signed-off-by: Chanho Park While this gives a way to set up the default clock divider (which is fair) I think you should probably go the extra mile and make this clock divider a proper clock abstraction, so the driver can respect the DT standard property spi-max-frequency from Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml This actually isn't very hard: look for example in the PL111 driver, a hardware block that contains a similar internal clock divider: drivers/gpu/drm/pl111/pl111_display.c check how we define a clock from pl111_clk_div_ops. in pl111_init_clock_divider(). Then the driver probe() just grabs that clock and sets the frequency. The algorithms should be pretty much copy/paste. Yours, Linus Walleij