From mboxrd@z Thu Jan 1 00:00:00 1970 From: Linus Walleij Subject: Re: [RFC PATCH V2 3/8] genirq: Add runtime power management support for IRQ chips Date: Fri, 5 Feb 2016 15:37:17 +0100 Message-ID: References: <1450349309-8107-1-git-send-email-jonathanh@nvidia.com> <1450349309-8107-4-git-send-email-jonathanh@nvidia.com> <569E1366.8070005@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Return-path: In-Reply-To: Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Thomas Gleixner , Marc Zyngier Cc: Ulf Hansson , Jon Hunter , Jason Cooper , Jiang Liu , Stephen Warren , Thierry Reding , Kevin Hilman , Geert Uytterhoeven , Grygorii Strashko , Lars-Peter Clausen , Soren Brinkmann , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "Rafael J. Wysocki" List-Id: linux-tegra@vger.kernel.org On Thu, Jan 21, 2016 at 8:51 PM, Thomas Gleixner wrote: > So as long as an interrupt handler is installed, there is no sane way that we > can decide to power down the irq chip, unless that chip has the magic ability > to relay incoming interrupts while powered down :) Actually isn't that exactly what almost every SoC that supports deepsleep does? They power off the primary interrupt controller and arm the padring of the SoC with an asynchronous edge detector to wake up as soon as something happens on a few select lines, like a keypad button or whatnot. The asynchronous edge detector is handled by the ROM or some power-management microcontroller, which wakes up the system and restores power to the CPU and primary interrupt controller. That is the magic ability right there. Of course as the wakeup signal may be deasserted at the point the system actually comes back up, so the magic ROM power management unit then needs to latch any latent IRQs from some shadow register to the primary interrupt controller, which as far as I've seen is done by out-of-tree hacks similar to the irq_[get/set]_irqchip_state() implemented by Marc Zyngier, albeit for virtualization. I've not seen it on any non-primary interrupt controller though. Yours, Linus Walleij From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753286AbcBEOhW (ORCPT ); Fri, 5 Feb 2016 09:37:22 -0500 Received: from mail-ob0-f182.google.com ([209.85.214.182]:36064 "EHLO mail-ob0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752851AbcBEOhS (ORCPT ); Fri, 5 Feb 2016 09:37:18 -0500 MIME-Version: 1.0 In-Reply-To: References: <1450349309-8107-1-git-send-email-jonathanh@nvidia.com> <1450349309-8107-4-git-send-email-jonathanh@nvidia.com> <569E1366.8070005@nvidia.com> Date: Fri, 5 Feb 2016 15:37:17 +0100 Message-ID: Subject: Re: [RFC PATCH V2 3/8] genirq: Add runtime power management support for IRQ chips From: Linus Walleij To: Thomas Gleixner , Marc Zyngier Cc: Ulf Hansson , Jon Hunter , Jason Cooper , Jiang Liu , Stephen Warren , Thierry Reding , Kevin Hilman , Geert Uytterhoeven , Grygorii Strashko , Lars-Peter Clausen , Soren Brinkmann , "linux-kernel@vger.kernel.org" , "linux-tegra@vger.kernel.org" , "linux-pm@vger.kernel.org" , "Rafael J. Wysocki" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 21, 2016 at 8:51 PM, Thomas Gleixner wrote: > So as long as an interrupt handler is installed, there is no sane way that we > can decide to power down the irq chip, unless that chip has the magic ability > to relay incoming interrupts while powered down :) Actually isn't that exactly what almost every SoC that supports deepsleep does? They power off the primary interrupt controller and arm the padring of the SoC with an asynchronous edge detector to wake up as soon as something happens on a few select lines, like a keypad button or whatnot. The asynchronous edge detector is handled by the ROM or some power-management microcontroller, which wakes up the system and restores power to the CPU and primary interrupt controller. That is the magic ability right there. Of course as the wakeup signal may be deasserted at the point the system actually comes back up, so the magic ROM power management unit then needs to latch any latent IRQs from some shadow register to the primary interrupt controller, which as far as I've seen is done by out-of-tree hacks similar to the irq_[get/set]_irqchip_state() implemented by Marc Zyngier, albeit for virtualization. I've not seen it on any non-primary interrupt controller though. Yours, Linus Walleij