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* [RESEND, PATCH] mmc: sdhci-pci-gli: A workaround to allow GL9755 to enter ASPM L1.2
@ 2022-04-14  9:49 Ben Chuang
  2022-04-19 11:45 ` Adrian Hunter
  2022-04-21 13:54 ` Ulf Hansson
  0 siblings, 2 replies; 4+ messages in thread
From: Ben Chuang @ 2022-04-14  9:49 UTC (permalink / raw)
  To: adrian.hunter, ulf.hansson
  Cc: SeanHY.Chen, ben.chuang, greg.tu, linux-kernel, linux-mmc, Ben Chuang

From: Ben Chuang <ben.chuang@genesyslogic.com.tw>

When GL9755 enters ASPM L1 sub-states, it will stay at L1.1 and will not
enter L1.2. The workaround is to toggle PM state to allow GL9755 to enter
ASPM L1.2.

Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
---
 drivers/mmc/host/sdhci-pci-gli.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index 97035d77c18c..52230857388f 100644
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -137,6 +137,9 @@
 #define PCI_GLI_9755_SerDes  0x70
 #define PCI_GLI_9755_SCP_DIS   BIT(19)
 
+#define PCI_GLI_9755_PM_CTRL     0xFC
+#define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)
+
 #define GLI_MAX_TUNING_LOOP 40
 
 /* Genesys Logic chipset */
@@ -597,6 +600,13 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
 			    GLI_9755_CFG2_L1DLY_VALUE);
 	pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
 
+	/* toggle PM state to allow GL9755 to enter ASPM L1.2 */
+	pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value);
+	value |= PCI_GLI_9755_PM_STATE;
+	pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
+	value &= ~PCI_GLI_9755_PM_STATE;
+	pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
+
 	gl9755_wt_off(pdev);
 }
 
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [RESEND, PATCH] mmc: sdhci-pci-gli: A workaround to allow GL9755 to enter ASPM L1.2
  2022-04-14  9:49 [RESEND, PATCH] mmc: sdhci-pci-gli: A workaround to allow GL9755 to enter ASPM L1.2 Ben Chuang
@ 2022-04-19 11:45 ` Adrian Hunter
  2022-04-21 13:54 ` Ulf Hansson
  1 sibling, 0 replies; 4+ messages in thread
From: Adrian Hunter @ 2022-04-19 11:45 UTC (permalink / raw)
  To: Ben Chuang, ulf.hansson
  Cc: SeanHY.Chen, ben.chuang, greg.tu, linux-kernel, linux-mmc

On 14/04/22 12:49, Ben Chuang wrote:
> From: Ben Chuang <ben.chuang@genesyslogic.com.tw>
> 
> When GL9755 enters ASPM L1 sub-states, it will stay at L1.1 and will not
> enter L1.2. The workaround is to toggle PM state to allow GL9755 to enter
> ASPM L1.2.
> 
> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-pci-gli.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index 97035d77c18c..52230857388f 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -137,6 +137,9 @@
>  #define PCI_GLI_9755_SerDes  0x70
>  #define PCI_GLI_9755_SCP_DIS   BIT(19)
>  
> +#define PCI_GLI_9755_PM_CTRL     0xFC
> +#define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)
> +
>  #define GLI_MAX_TUNING_LOOP 40
>  
>  /* Genesys Logic chipset */
> @@ -597,6 +600,13 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
>  			    GLI_9755_CFG2_L1DLY_VALUE);
>  	pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
>  
> +	/* toggle PM state to allow GL9755 to enter ASPM L1.2 */
> +	pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value);
> +	value |= PCI_GLI_9755_PM_STATE;
> +	pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
> +	value &= ~PCI_GLI_9755_PM_STATE;
> +	pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
> +
>  	gl9755_wt_off(pdev);
>  }
>  


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [RESEND, PATCH] mmc: sdhci-pci-gli: A workaround to allow GL9755 to enter ASPM L1.2
  2022-04-14  9:49 [RESEND, PATCH] mmc: sdhci-pci-gli: A workaround to allow GL9755 to enter ASPM L1.2 Ben Chuang
  2022-04-19 11:45 ` Adrian Hunter
@ 2022-04-21 13:54 ` Ulf Hansson
  2022-04-25  0:53   ` Ben Chuang
  1 sibling, 1 reply; 4+ messages in thread
From: Ulf Hansson @ 2022-04-21 13:54 UTC (permalink / raw)
  To: Ben Chuang
  Cc: adrian.hunter, SeanHY.Chen, ben.chuang, greg.tu, linux-kernel, linux-mmc

On Thu, 14 Apr 2022 at 11:49, Ben Chuang <benchuanggli@gmail.com> wrote:
>
> From: Ben Chuang <ben.chuang@genesyslogic.com.tw>
>
> When GL9755 enters ASPM L1 sub-states, it will stay at L1.1 and will not
> enter L1.2. The workaround is to toggle PM state to allow GL9755 to enter
> ASPM L1.2.
>
> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>

This didn't apply cleanly, I fixed it up this time. So, applied for
next, thanks!

Kind regards
Uffe


> ---
>  drivers/mmc/host/sdhci-pci-gli.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index 97035d77c18c..52230857388f 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -137,6 +137,9 @@
>  #define PCI_GLI_9755_SerDes  0x70
>  #define PCI_GLI_9755_SCP_DIS   BIT(19)
>
> +#define PCI_GLI_9755_PM_CTRL     0xFC
> +#define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)
> +
>  #define GLI_MAX_TUNING_LOOP 40
>
>  /* Genesys Logic chipset */
> @@ -597,6 +600,13 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
>                             GLI_9755_CFG2_L1DLY_VALUE);
>         pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
>
> +       /* toggle PM state to allow GL9755 to enter ASPM L1.2 */
> +       pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value);
> +       value |= PCI_GLI_9755_PM_STATE;
> +       pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
> +       value &= ~PCI_GLI_9755_PM_STATE;
> +       pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
> +
>         gl9755_wt_off(pdev);
>  }
>
> --
> 2.35.1
>

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [RESEND, PATCH] mmc: sdhci-pci-gli: A workaround to allow GL9755 to enter ASPM L1.2
  2022-04-21 13:54 ` Ulf Hansson
@ 2022-04-25  0:53   ` Ben Chuang
  0 siblings, 0 replies; 4+ messages in thread
From: Ben Chuang @ 2022-04-25  0:53 UTC (permalink / raw)
  To: Ulf Hansson
  Cc: Adrian Hunter, SeanHY.Chen, Ben Chuang, greg.tu,
	Linux Kernel Mailing List, linux-mmc

On Thu, Apr 21, 2022 at 9:55 PM Ulf Hansson <ulf.hansson@linaro.org> wrote:
>
> On Thu, 14 Apr 2022 at 11:49, Ben Chuang <benchuanggli@gmail.com> wrote:
> >
> > From: Ben Chuang <ben.chuang@genesyslogic.com.tw>
> >
> > When GL9755 enters ASPM L1 sub-states, it will stay at L1.1 and will not
> > enter L1.2. The workaround is to toggle PM state to allow GL9755 to enter
> > ASPM L1.2.
> >
> > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
>
> This didn't apply cleanly, I fixed it up this time. So, applied for
> next, thanks!
>
> Kind regards
> Uffe

I forgot to rebase to v5.18rc. I will pay more attention next time. Thank you.

Best regards,
Ben

>
>
> > ---
> >  drivers/mmc/host/sdhci-pci-gli.c | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> > index 97035d77c18c..52230857388f 100644
> > --- a/drivers/mmc/host/sdhci-pci-gli.c
> > +++ b/drivers/mmc/host/sdhci-pci-gli.c
> > @@ -137,6 +137,9 @@
> >  #define PCI_GLI_9755_SerDes  0x70
> >  #define PCI_GLI_9755_SCP_DIS   BIT(19)
> >
> > +#define PCI_GLI_9755_PM_CTRL     0xFC
> > +#define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)
> > +
> >  #define GLI_MAX_TUNING_LOOP 40
> >
> >  /* Genesys Logic chipset */
> > @@ -597,6 +600,13 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
> >                             GLI_9755_CFG2_L1DLY_VALUE);
> >         pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
> >
> > +       /* toggle PM state to allow GL9755 to enter ASPM L1.2 */
> > +       pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value);
> > +       value |= PCI_GLI_9755_PM_STATE;
> > +       pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
> > +       value &= ~PCI_GLI_9755_PM_STATE;
> > +       pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
> > +
> >         gl9755_wt_off(pdev);
> >  }
> >
> > --
> > 2.35.1
> >

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2022-04-25  0:53 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-14  9:49 [RESEND, PATCH] mmc: sdhci-pci-gli: A workaround to allow GL9755 to enter ASPM L1.2 Ben Chuang
2022-04-19 11:45 ` Adrian Hunter
2022-04-21 13:54 ` Ulf Hansson
2022-04-25  0:53   ` Ben Chuang

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